CN215600339U - Integrated circuit packaging body pressing device - Google Patents
Integrated circuit packaging body pressing device Download PDFInfo
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- CN215600339U CN215600339U CN202122162942.8U CN202122162942U CN215600339U CN 215600339 U CN215600339 U CN 215600339U CN 202122162942 U CN202122162942 U CN 202122162942U CN 215600339 U CN215600339 U CN 215600339U
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Abstract
The utility model relates to an integrated circuit packaging body pressing device, which comprises: base, place board and apron. The base includes: base main part, locating piece and positioning mechanism. The positioning block is arranged on the base main body and defines an accommodating space on the base main body. The positioning mechanism is arranged on the base main body and located in the accommodating space. The positioning mechanism includes: location main part and first pilot pin. The first positioning pin is arranged to be positioned on the positioning main body. The placing plate is arranged to be positioned on the base and positioned in the accommodating space. The cover plate is arranged to be positioned on the placing plate. Compared with the prior art, the integrated circuit packaging body pressing device provided by the embodiment of the utility model solves the problems of inaccurate pressing positioning, overlarge pressing deviation and the like by improving the structure of the existing pressing device, and improves the yield of integrated circuit products.
Description
Technical Field
The present invention relates generally to the field of integrated circuit technology, and more particularly, to a pressing device for an integrated circuit package.
Background
In the field of integrated circuits, it is often necessary to bond multiple layers of substrates together to form an integrated circuit package having multiple layers of substrates, such as a micro-electro-mechanical system (mems) microphone (also known as a "silicon microphone") package. However, when the existing pressing device is used to press a multi-layer substrate, problems such as inaccurate pressing and positioning, excessive pressing deviation and the like often occur, which easily results in cutting the copper rail of the substrate in the subsequent cutting process, and further causes product failure.
Therefore, there is a need for improvements in existing integrated circuit package lamination techniques, such as lamination devices.
SUMMERY OF THE UTILITY MODEL
An objective of an embodiment of the present invention is to provide a bonding apparatus for an integrated circuit package, which can solve the problems of inaccurate bonding positioning and excessive bonding offset of the conventional bonding apparatus.
According to an embodiment of the present invention, an integrated circuit package pressing apparatus includes: base, place board and apron. The base includes: base main part, locating piece and positioning mechanism. The positioning block is arranged on the base main body and defines an accommodating space on the base main body. The positioning mechanism is arranged on the base main body and located in the accommodating space. The positioning mechanism includes: location main part and first pilot pin. The first positioning pin is arranged to be positioned on the positioning main body. The placing plate is arranged to be positioned on the base and positioned in the accommodating space. The cover plate is arranged to be positioned on the placing plate.
Compared with the prior art, the integrated circuit packaging body pressing device provided by the embodiment of the utility model solves the problems of inaccurate pressing positioning, overlarge pressing deviation and the like by improving the structure of the existing pressing device, and improves the yield of integrated circuit products.
Drawings
Fig. 1 is a schematic overall structure diagram of an integrated circuit package bonding apparatus according to an embodiment of the utility model.
Fig. 2 is a schematic structural diagram of a base according to an embodiment of the utility model.
Fig. 3 is a schematic structural diagram of a placement board according to an embodiment of the utility model.
Fig. 4 is a schematic structural diagram of a cover plate according to an embodiment of the utility model.
Fig. 5 is a schematic structural diagram of an integrated circuit package having three substrates according to an embodiment of the utility model.
Fig. 6 is a schematic view showing a structure when the mounting plate shown in fig. 3 is placed on the base shown in fig. 2.
Fig. 7 is a schematic structural view of the first-layer substrate array placed on the placement board.
Fig. 8 is a schematic structural diagram of a handheld positioning post according to an embodiment of the utility model.
Fig. 9 is a press-fit flow chart according to an embodiment of the utility model.
Detailed Description
In order that the spirit of the utility model may be better understood, some preferred embodiments of the utility model are described below.
Fig. 1 is a schematic overall structure diagram of an integrated circuit package bonding apparatus according to an embodiment of the utility model.
As shown in fig. 1, the integrated circuit package bonding apparatus 10 includes a base 20, a placing plate 30 and a cover plate 40. The placing plate 30 is located on the base 20, and the cover plate 40 is located on the placing plate 30. When the integrated circuit package bonding apparatus 10 is used for bonding an integrated circuit package having a plurality of substrates, the plurality of substrates are disposed on the placing plate 30 and between the placing plate 30 and the cover plate 40.
The detailed structure of the base 20, the placing plate 30 and the cover plate 40 will be described in detail with reference to fig. 2 to 4. Specifically, fig. 2 is a schematic structural diagram of a base according to an embodiment of the utility model; FIG. 3 is a schematic structural diagram of a placement board according to an embodiment of the present invention; fig. 4 is a schematic structural diagram of a cover plate according to an embodiment of the utility model.
As shown in fig. 2, the base 20 includes a base body 202, a positioning block 204, a positioning mechanism 206, and positioning pins 208a-208 d.
The positioning block 204 is disposed on the base body 202, and defines an accommodating space on the base body 202. In the embodiment shown in fig. 2, the positioning blocks 204 are 4 right-angle positioning blocks, which are respectively disposed around the base main body 202. However, it should be understood that: the structure and number of the positioning blocks 204 shown in fig. 2 are only one embodiment of the present invention, and in other embodiments, the positioning blocks 204 may also be in other structural forms or numbers, which are not specifically limited herein.
The positioning mechanism 206 is disposed on the base body 202 and located in the accommodating space. The positioning mechanism 206 includes: a positioning body 210 and a positioning pin 212. The positioning pin 212 is disposed on the positioning body 210. The positioning body 210 includes a positioning hole 214 and an adjustable connecting member 216 connected to the positioning hole 214. In one embodiment of the present invention shown in FIG. 2, the positioning holes 214 are threaded holes and the adjustable connecting member 216 is a cross screw. In operation, the position of the positioning pins 212 can be finely adjusted by tightening the adjustable connection members 216 to overcome the position error between the substrates of different layers of the integrated circuit package. As shown in fig. 2, the positioning pins 212 are conical, so that the positioning holes on each layer of the substrate of the ic package can be easily handled when being fixed by the positioning pins 212. In one embodiment of the present invention, the conical shaped positioning pin 212 has a diameter of 1.0mm at the upper end and 1.48mm at the lower end. However, it should be understood that the positioning mechanism 206 shown in FIG. 2 is merely one embodiment of the present invention, and that the positioning mechanism 206 may have other dimensions or configurations. For example, the positioning pin 212 may be cylindrical, and the adjustable connection component 216 may be a straight screw, which is not limited herein.
The positioning pins 208a-208d are located in the receiving space and adjacent to the positioning block 204. The placement plate 30 may be mounted to the base 20 by the alignment pins 208a-208 d. As shown in fig. 2, the number of the positioning pins 208a to 208d is 4. In operation, the positioning pins 208a-208d may be spaced differently from the corresponding 4 positioning blocks 204 to prevent the placement plate 30 from being reversed. For example, in one embodiment of the present invention, the distance between the positioning pin 208a and the positioning pin 208d and the right angle of the adjacent right angle positioning block 204 is equal to 8 mm; the distances between the positioning pins 208b and 208c and the right angle of the adjacent right-angle positioning block 204 are equal and 10 mm; thereby, the placing plate 30 can be prevented from being placed upside down. However, it should be understood that: the structure and number of the positioning pins 208a-208d shown in fig. 2 are only one embodiment of the present invention, and in other embodiments, the positioning pins 208a-208d may have other structural forms or numbers, which are not limited herein.
As shown in fig. 3, the placement board 30 includes a placement board main body 302, positioning posts 304a-304h, positioning holes 306, positioning holes 308, and positioning holes 310.
The placement board main body 302 includes a nip area 302a and an outer area 302b provided at the periphery of the nip area 302 a. The pressing region 302a has a sinking groove structure and has a hollow grid 312. The sinker structure may function to position the multilayer substrate of the integrated circuit package. The depth of the nip region 302a is determined according to the thickness of the multi-layered substrate. In an embodiment of the utility model, when the thickness of the multi-layer substrate is 0.25mm, the depth of the pressing region 302a is 0.15 mm. The length and width of the bonding region 302a are greater than or equal to those of the multi-layer substrate, so that the multi-layer substrate of the integrated circuit package can be precisely disposed in the bonding region 302 a. The hollow grid 312 may enable the multi-layered substrate of the ic package to be heated more uniformly in the subsequent through-furnace heating process.
The positioning hole 306 is disposed in the pressing region 302 a. As shown in FIG. 4, in one embodiment of the present invention, the number of positioning holes 306 is 4. The position of the positioning hole 306 corresponds to the position of the positioning pin 212 on the base 20.
The positioning hole 308 is disposed in the outer region 302 b. As shown in FIG. 4, in one embodiment of the present invention, the number of positioning holes 308 is 8. The position of the positioning hole 308 corresponds to the position of the positioning hole 214 on the base 20.
In one embodiment of the present invention, the positioning holes 306 and 308 are kidney-shaped holes. The waist-shaped design may make it more convenient to mount the placement board 30 on the base body 202 in cooperation with the positioning mechanism 206 of the base 20.
The positioning hole 310 is disposed in the outer region 302 b. Specifically, the positioning holes 310 are provided around the placement plate main body 302. As shown in fig. 4, in an embodiment of the present invention, the number of the positioning holes 310 is 4. The positions of the 4 positioning holes 310 correspond to the positions of the positioning pins 208a-208d on the base 20, respectively.
It should be understood that the above description of the shape and number of the alignment holes 306, 308, and 310 is only one specific embodiment of the present invention. The shapes and the number of the positioning holes 306, 308 and 310 are determined according to actual needs.
As shown in fig. 4, the cover plate 40 includes a cover plate body 402, positioning holes 404, positioning holes 406, and an opening 408. In operation, the cover plate 40 is used to press the multi-layered substrate placed on the placing plate 30, so as to prevent the multi-layered substrate from being heated and tilted to cause the failure of the integrated circuit package.
The position of the positioning hole 404 corresponds to the position of the positioning hole 306 on the placement plate 30. The positioning holes 406 are positioned to correspond to the positioning posts 304a-304h on the placement board 30. In fig. 4, the number of positioning holes 404 is also 4, corresponding to the number of positioning holes 306 on the placement plate 30; in addition, the number of positioning holes 406 is also 8 corresponding to the number of positioning posts 304a to 304h on the placing plate 30. However, it should be understood that the number of alignment holes 404 and 406 corresponding to alignment holes 306 and alignment posts 304a-304h may be other numbers, and may depend on the actual needs. Fig. 4 is also intended to be only an embodiment of the present invention. In addition, in another embodiment of the present invention, the positioning holes 404 and 406 are kidney-shaped holes.
The opening 408 may be multiple in number, which functions to rapidly transfer heat and rapidly dissipate heat during a subsequent furnace heating process.
Fig. 5 is a schematic structural diagram of an integrated circuit package having three substrates according to an embodiment of the utility model. It should be understood that: fig. 5 is a schematic diagram of a single integrated circuit package 50 in an array of multiple integrated circuit packages distributed in an array.
As shown in fig. 5, the integrated circuit package 50 includes an upper substrate 502, a middle substrate 504, and a lower substrate 506. The intermediate substrate 504 has a cavity 508 and a metal contact 510. The lower substrate 506 has metal contacts 512. The upper substrate 502, the middle substrate 504 and the lower substrate 506 are pressed together by the integrated circuit package pressing apparatus 10, so that a single silicon microphone package can be formed. When the integrated circuit packages 50 form a plurality of integrated circuit package arrays distributed in an array, the lower substrate 506 is disposed on a first layer substrate array, the middle substrate 504 is disposed on a second layer substrate array, and the upper substrate 502 is disposed on a third layer substrate array.
Furthermore, it should be understood that the integrated circuit package 50 shown in fig. 5 is only one embodiment of the present invention, and is not limited to the integrated circuit package with a multi-layered substrate of the present invention. In other embodiments of the present invention, an integrated circuit package having a multi-layer substrate may have only two layers or have more than three layers of substrates. The structure of the integrated circuit package having the multilayer substrate may be different from that shown in fig. 5, and is not limited to the silicon microphone package. The integrated circuit package 50 shown in fig. 5 is merely an exemplary embodiment of the present invention.
Fig. 6 is a schematic view showing a structure when the mounting plate shown in fig. 3 is placed on the base shown in fig. 2.
Referring to fig. 2-3 and 6, the placing plate 30 is placed on the base 20 and is located in the receiving space defined by the positioning block 204. The positioning pins 212 on the base 20 are disposed in the positioning holes 306 on the placing plate 30, and protrude from the positioning holes 306. The adjustable connecting component 216 is further connected to the positioning hole 214 on the base 20 corresponding to the position thereof via the positioning hole 308 on the placing plate 30. Further, the positioning pins 208a to 208d on the base 20 are respectively provided in the 4 positioning holes 310 of the placing plate 30, and protrude from the positioning holes 310.
Fig. 7 is a schematic structural view of the first-layer substrate array placed on the placement board. Specifically, fig. 7 is a schematic structural diagram when the first layer substrate array 702 on which the lower substrate 506 is located in the integrated circuit package 50 shown in fig. 5 is placed on the placing plate 30.
Referring to fig. 2-3 and 7, the first layer substrate array 702 is disposed on the placing board 30 and located in the pressing area 302 a. The first layer of substrate array 702 has positioning holes 704 and positioning holes 706. The position of the positioning hole 704 corresponds to the position of the positioning hole 306 on the placement plate 30, so that the positioning pin 212 on the pedestal main body 202 can protrude from the positioning hole 306 on the placement plate 30 and the positioning hole 704 of the first-layer substrate array 702 in this order; the positioning holes 706 are located corresponding to the positioning posts 304a-304h on the placing plate 30 such that the positioning posts 304a-304h on the placing plate 30 can protrude from the positioning holes 706; thereby positioning the first layer substrate array 702.
In operation, the second layer substrate array of the middle substrate 504 of the integrated circuit package 50 is further disposed on the first layer substrate array 702 of the lower substrate 506, and the third layer substrate array of the upper substrate 502 of the integrated circuit package 50 is further disposed on the second layer substrate array of the middle substrate 504. The arrangement of the second layer substrate array of the middle substrate 504 and the third layer substrate array of the upper substrate 502 is the same as the arrangement of the first layer substrate array 702 of the lower substrate 506, and is not described herein again.
Referring back to fig. 1, fig. 1 is a schematic view illustrating an overall structure of an integrated circuit package bonding apparatus according to an embodiment of the utility model. Specifically, fig. 1 is a schematic structural view of the structure shown in fig. 7 after the cover plate 40 is placed thereon.
Referring to fig. 1 to 7, after the third layer substrate array on which the upper substrate 502 is located, the second layer substrate array on which the middle substrate 504 is located, and the first layer substrate array 702 on which the lower substrate 506 is located are all disposed on the placing plate 30 and located in the pressing region 302a, the cover plate 40 is then placed thereon.
The position of the positioning hole 404 on the cover plate 20 corresponds to the position of the positioning hole 704 of the first layer substrate array 702, so that the positioning pin 212 on the base body 202 can further protrude from the positioning hole 404; the positioning holes 406 on the cover plate 20 are located corresponding to the positioning holes 706 of the first layer substrate array 702, so that the positioning posts 304a-304h on the placing plate 30 can further protrude from the positioning holes 406; thereby further positioning the cover plate 20 as well.
Fig. 9 is a schematic structural diagram of a handheld positioning post according to an embodiment of the utility model. Specifically, the integrated circuit package bonding apparatus 10 further includes a hand-held positioning post 90.
As shown in fig. 9, hand-held locator post 90 includes a handle 902 and a locator post 904. The handle 902 may be conveniently hand-held. In an embodiment of the present invention, the number of the handheld positioning pillars 90 corresponds to the number of the positioning pins 212 on the base 20, and is 4. In another embodiment of the present invention, the diameter of the positioning post 904 is 1.48 mm. In other embodiments of the present invention, the head of the positioning post 904 is chamfered, which facilitates installation. After the cover plate 40 is placed on the structure shown in fig. 7 (i.e., corresponding to fig. 1), the placing plate 30 and the cover plate 40 are integrally removed from the base 20, transferred, and subjected to a subsequent furnace-passing heating process. However, since the placing plate 30 and the cover plate 40 are removed from the base 20, the positioning holes 306 on the placing plate 30, the corresponding positioning holes on the multi-layer substrate array (e.g., the positioning holes 704 on the first layer substrate array 702), and the positioning holes 404 on the cover plate 20 cannot be aligned by the positioning pins 212 on the base 20. At this time, in order to ensure the pressing and positioning of the integrated circuit package pressing device 10 and the multi-layer substrate array therein, and avoid the deviation thereof due to deformation during the furnace heating process, the hand-held positioning pillars 90 may be sequentially disposed in the positioning holes 404 on the cover plate 20, the corresponding positioning holes (e.g., the positioning holes 704 on the first layer substrate array 702) on the multi-layer substrate array, and the positioning holes 306 on the placing plate 30, so as to replace the positioning function of the positioning pins 212 on the base 20, thereby achieving the secondary positioning.
Fig. 9 is a press-fit flow chart according to an embodiment of the utility model. The pressing process is described below with reference to fig. 1-9.
In step S10, the placing board 30 is placed on the base 20. The positioning pins 212 and the positioning posts 208a-208d on the base 20 are used to position the placing plate 30.
In step S20, the first-layer substrate array is placed on the placing board 30. The first layer substrate array (e.g., the lower substrate array 702) is positioned by the positioning pins 212 on the base 20 and the positioning posts 304a-304h on the placing plate 30.
In step S30, a second layer substrate array is placed on the first layer substrate array. The second layer substrate array is also positioned by the positioning pins 212 on the base 20 and the positioning posts 304a-304h on the placing plate 30.
In step S40, a third layer substrate array is placed on the second layer substrate array. The third layer substrate array is also positioned by the positioning pins 212 on the base 20 and the positioning posts 304a-304h on the placing plate 30.
In step S50, the cover 40 is placed on the uppermost layer. The cover plate 40 is also positioned by the positioning pins 212 on the base 20 and the positioning posts 304a-304h on the placement plate 30.
In step S60, the placement board 30 is removed as a whole from the cover 40, and the hand positioning post 90 is attached. Specifically, the placement board 30, the cover board 40, and the first layer substrate array, the second layer substrate array, and the third layer substrate array located therein are removed from the base 20, and the hand-held positioning posts 90 are mounted into the positioning holes 404 on the cover board 40 and extend into the corresponding positioning holes 404 on the multi-layer substrate array (e.g., positioning holes 704 on the first layer substrate array 702) and positioning holes 306 on the placement board 30, instead of the positioning pins 212 on the base 20.
In step S70, a furnace heating process is performed. Specifically, the placement board 30, the cover board 40, the first layer substrate array, the second layer substrate array, and the third layer substrate array located therein, and the hand-held positioning posts 90 are collectively fed into the through-furnace heating process apparatus.
Compared with the integrated circuit package pressing device in the prior art, the integrated circuit package pressing device provided by the embodiment of the utility model improves the integrated circuit package pressing device in the prior art, provides adjustable positioning and secondary positioning, and improves the pressing precision of the multilayer substrate. Experiments prove that the integrated circuit package pressing device provided by the embodiment of the utility model can control the pressing precision of the multilayer substrate within + -50um, and effectively improve the yield of pressing deviation. Therefore, the integrated circuit packaging body pressing device provided by the embodiment of the utility model solves the problems in the prior art and improves the yield of integrated circuit products.
It should be noted that reference throughout this specification to "one embodiment of the utility model" or similar terms means that a particular feature, structure or characteristic described in connection with the other embodiments is included in at least one embodiment and may not necessarily be present in all embodiments. Thus, respective appearances of the phrase "one embodiment of the utility model" or similar terms in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment may be combined in any suitable manner with one or more other embodiments.
While the foregoing has been with reference to the disclosure of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the utility model as defined by the appended claims. Therefore, the protection scope of the present invention should not be limited to the disclosure of the embodiments, but should include various alternatives and modifications without departing from the utility model, which are covered by the claims of the present patent application.
Claims (17)
1. An integrated circuit package compression apparatus, comprising:
a base, comprising:
a base body;
a positioning block disposed on the base body and defining a receiving space on the base body; and
a positioning mechanism disposed on the base body and in the accommodating space, the positioning mechanism including:
a positioning body; and
a first positioning pin configured to be positioned on the positioning body;
a placing plate configured to be positioned on the base and in the accommodating space; and
a cover plate disposed to be located on the placing plate.
2. The integrated circuit package body bonding apparatus of claim 1, wherein the positioning blocks are four right-angle positioning blocks respectively disposed around the base body.
3. The integrated circuit package bonding apparatus of claim 1, wherein the size of the accommodating space is larger than that of the placing plate.
4. The integrated circuit package compression device of claim 1, wherein the positioning body comprises a first positioning hole and an adjustable connection member connectable to the first positioning hole.
5. The integrated circuit package compression device of claim 1, wherein the first locator pin is conical.
6. The IC package pressing device according to claim 4, wherein the base further comprises a second positioning pin located in the accommodating space and adjacent to the positioning block.
7. The integrated circuit package compression device of claim 6, wherein the placing plate comprises: the placing plate main body comprises a pressing area and an outer area arranged on the periphery of the pressing area.
8. The integrated circuit package compression device of claim 7, wherein the compression region is a hollow grid.
9. The integrated circuit package compression device of claim 7, wherein the placing plate main body comprises:
the first positioning column is arranged in the press-fit area.
10. The integrated circuit package compression device of claim 9, wherein the placement plate main body further comprises:
the second positioning hole is arranged in the press-fit area, and the first positioning pin is arranged in the second positioning hole; and
a third positioning hole disposed in the outer region and connected to the first positioning hole via the adjustable connection member.
11. The integrated circuit package compression device of claim 10, wherein the second positioning hole and the third positioning hole are kidney-shaped holes.
12. The integrated circuit package compression device of claim 9, wherein the placement plate main body further comprises: and the second positioning pin is arranged in the fourth positioning hole.
13. The integrated circuit package compression device of claim 10, wherein the cover plate comprises:
a cover plate main body; and
and the first positioning pin is arranged in the fifth positioning hole.
14. The integrated circuit package compression device of claim 13, wherein the cover plate further comprises: and the first positioning column is arranged in the sixth positioning hole.
15. The integrated circuit package compression device of claim 14, wherein the fifth positioning hole and the sixth positioning hole are kidney-shaped holes.
16. The integrated circuit package compression device of claim 13, wherein the cover plate further comprises an opening disposed on the cover plate body.
17. The ic package pressing device as recited in claim 13, further comprising second positioning posts disposed in the second positioning holes and the fifth positioning holes when the placing plate and the cover plate are removed from the base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122162942.8U CN215600339U (en) | 2021-09-08 | 2021-09-08 | Integrated circuit packaging body pressing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122162942.8U CN215600339U (en) | 2021-09-08 | 2021-09-08 | Integrated circuit packaging body pressing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215600339U true CN215600339U (en) | 2022-01-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122162942.8U Active CN215600339U (en) | 2021-09-08 | 2021-09-08 | Integrated circuit packaging body pressing device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215600339U (en) |
-
2021
- 2021-09-08 CN CN202122162942.8U patent/CN215600339U/en active Active
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Address after: No. 188, Suhong West Road, Suzhou Industrial Park, Suzhou, Jiangsu Province Patentee after: Riyuexin semiconductor (Suzhou) Co.,Ltd. Address before: No. 188, Suhong West Road, Suzhou Industrial Park, Suzhou, Jiangsu Province Patentee before: SUZHOU ASEN SEMICONDUCTORS Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder |