CN215577631U - Cascade synchronization device for multiple LED video processors - Google Patents
Cascade synchronization device for multiple LED video processors Download PDFInfo
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- CN215577631U CN215577631U CN202122137349.8U CN202122137349U CN215577631U CN 215577631 U CN215577631 U CN 215577631U CN 202122137349 U CN202122137349 U CN 202122137349U CN 215577631 U CN215577631 U CN 215577631U
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Abstract
The utility model provides a many LED video processor cascade synchronizer, relates to the image processing system and the device technical field of LED display screen, solves the problem of current many LED video processor when cascading asynchronization, and technical scheme includes: the LED video signal processing device comprises at least two LED video processors, wherein each processor is internally provided with a synchronous card, and each synchronous card is provided with a clock synchronous chip, a communication interface component and a synchronous signal interface component. One LED video processor is a host and is connected with an upper computer through a communication interface component, and the rest are slave computers and are connected with the host through a synchronous signal input interface to form multi-computer cascade. The utility model has the beneficial effects that: the clock synchronization chip of the host outputs at least one group of homologous differential clock signals and line-field synchronization signals to the slave connected with the clock synchronization chip, so that the synchronization of the host and the slave is realized, the output image signals can be stably played on the LED display screen, and the problems of cracking and distortion of the played picture in the prior art are solved.
Description
Technical Field
The utility model relates to an image processing system and device used for an LED display screen, in particular to a cascade synchronization device for a plurality of LED video processors.
Background
In the LED video processor industry, due to the customized depth of content, sometimes a single device cannot meet complex applications, and multiple LED video processor connection schemes are needed to cope with the applications, however, electronic components of each LED video processor, such as IC chips, cannot be completely consistent due to process differences, and simultaneously, the crystal oscillator phases of each LED video processor cannot be completely the same, so that each LED video processor cannot be completely synchronized. Therefore, when a plurality of LED video processors work in a coordinated mode, errors are easily accumulated continuously due to the asynchronous problem, and the abnormal phenomena of picture splitting, distortion and the like of an LED display screen in the video picture playing process can be caused at a certain moment when the errors are accumulated to a certain degree.
The problem of unsynchronized picture splitting, distortion and the like of a plurality of LED display screens in the video output process is essentially caused by the starting time difference and the clock frequency difference of an image processing system, so how to solve the clock frequency difference of a plurality of LED video processors in the cascade coordination process and ensure that each LED video processor can stably output images in a cascade synchronization mode becomes a technical problem which is urgently needed to be solved by the industry at present.
SUMMERY OF THE UTILITY MODEL
In summary, the present invention is directed to a cascaded synchronization apparatus for multiple LED video processors, which solves the technical problem of picture splitting and distortion during playing due to non-synchronization in the process of using multiple LED video processors in a cascaded manner.
In order to solve the technical defects provided by the utility model, the technical scheme is as follows:
the utility model provides a many LED video processor cascade synchronization device, includes the LED video processor of at least two, its characterized in that: each LED video processor is internally provided with a synchronous card, each synchronous card is provided with a clock synchronization chip, a communication interface component and a synchronous signal interface component, the communication interface component and the synchronous signal interface component are connected with the clock synchronization chip, and the synchronous signal interface component comprises a synchronous signal input interface and at least one synchronous signal output interface. One of the LED video processors is a host, is connected with an upper computer through the communication interface component on the synchronous card thereof to send a system command to the device, and the other LED video processors are slaves, and are connected with one of the synchronous signal output interfaces of the host through the synchronous signal input interface on the synchronous card thereof through a cable to form multi-computer cascade. The clock synchronization chip of the host outputs at least one group of homologous differential clock signals and line-field synchronization signals, and the homologous differential clock signals and the line-field synchronization signals are respectively transmitted to the slave computers connected with the clock synchronization chip through the synchronization signal output interface on the host through the cable.
Preferably, the number of the slave devices is four or less, and the number of the synchronization signal output interfaces on the same synchronization card is four or less.
Preferably, the synchronization signal input interface and the synchronization signal output interface are both RJ45 interfaces.
Preferably, the communication interface component comprises a network interface, a USB interface and a DB9 interface.
Furthermore, the clock synchronization chip comprises a state management module and a synchronization signal transceiver module connected with the state management module, the synchronization signal transceiver module of the master outputs at least one group of the homologous differential clock signals and the line field synchronization signals through the synchronization signal output interface under the control of the state management module, and the synchronization signal transceiver module of the slave receives one group of the homologous differential clock signals and the line field synchronization signals output by the master through the synchronization signal input interface under the control of the state management module.
Further, the synchronization signal transceiver module includes a synchronization clock generator, a field synchronization/line synchronization generator, a clock buffer, and a synchronization clock receiver, the synchronization clock generator of the master generates a clock signal through a crystal oscillator under the control of the state management module and sends the clock signal to the clock buffer for replication, and the clock buffer outputs four sets of the homologous differential clock signals at most, and the field synchronization/line synchronization generator of the master generates four sets of the line field synchronization signals at most under the control of the state management module and sends the line field synchronization signals and the homologous differential clock signals to the slave in a one-to-one correspondence manner through the synchronization signal output interface of the master. And the synchronous clock receiver of the synchronous signal transceiving module of the slave receives one group of homologous differential clock signals and horizontal field synchronous signals transmitted by the master through the synchronous signal input interface of the slave.
The utility model has the beneficial effects that:
1. compared with the mode that a single LED video processor is used for processing image signals, the device enhances the image signal processing capability in the mode of cascading a plurality of LED video processors, and is more suitable for being applied to large-size stage LED display screens. The clock of the device is generated from a crystal oscillator of a synchronous card on the host computer to be a homologous clock, so that the beat synchronization of the image processing chips of the LED video processors is ensured, the pictures output by each LED video processor are delayed and synchronized during switching or between frames through line synchronization and field synchronization, the synchronous signals used by the host computer and all slave computers are ensured to be nearly consistent, and the synchronization of image processing can be ensured to the maximum extent, so that the aim of cascading synchronization of a plurality of LED video processors of the device is fulfilled, the image signals output by the device can be stably played on an LED display screen, and the problems of splitting and distortion of the played pictures in the prior art are solved.
2. The LED video processors of the device use the same clock and synchronous signals, and the device has more advantages than the pure VS frame synchronization.
3. Compared with the DDR cache synchronization product in the current market, the image processing effect of the utility model has more advantages in the aspects of transmission delay and synchronization.
4. The LED video processors in the device have the same structure, any one LED video processor can be used as a host or a slave, and all machine positions can be replaced mutually, so that multi-machine cascade combination is facilitated, the probability of connection faults is reduced to the greatest extent, and the effect of multi-machine cascade is ensured. In addition, parts of each LED video processor can be used and replaced universally, and the later use and maintenance cost of a user is greatly reduced.
Drawings
FIG. 1 is a schematic view of the overall structure of the present invention;
FIG. 2 is a first schematic block diagram of the circuit of the present invention;
FIG. 3 is a second schematic block diagram of the circuit of the present invention;
fig. 4 is a schematic block diagram of the communication interface module circuitry of the present invention.
Detailed Description
The structure of the present invention will be further described with reference to the accompanying drawings and preferred embodiments of the present invention.
Referring to fig. 1 to 3, the present invention:
a cascade synchronizer for a plurality of LED video processors comprises five LED video processors 1 with the same structure, wherein each LED video processor 1 is internally provided with a synchronous card 2, and each synchronous card 2 of each LED video processor 1 is provided with a clock synchronization chip 3, a communication interface component 4 and a synchronous signal interface component 5 which are connected with the clock synchronization chip 3.
Preferably, the sync signal interface module 5 of each sync card 2 in the present embodiment includes a sync signal input interface 51 and four sync signal output interfaces 52. During actual cascade assembly, any one of the five LED video processors 1 is used as a host 11, and the communication interface component 4 on the synchronous card 2 of the LED video processor 1 used as the host 11 is connected with the upper computer 6 through a corresponding cable, so that the host 11 of the device can perform data communication with the upper computer 6, and a system control instruction signal sent by the upper computer 6 is received. The other four LED video processors 1 are used as the slaves 12, and each slave 12 is connected to one of the synchronization signal output interfaces 52 of the synchronization card 2 of the master 11 through the synchronization signal input interface 51 on the synchronization card 2 of the slave 12 in a one-to-one correspondence manner via a cable to form a multi-machine cascade.
In practical use, the clock synchronization chip 3 on the synchronization card 2 of the LED video processor 1 serving as the master 11 outputs four sets of homologous differential clock signals and line-field synchronization signals, and the signals are respectively transmitted to the slaves 12 connected thereto through the four synchronization signal output interfaces 52 on the synchronization card 2 of the master 11 via corresponding cables in a one-to-one correspondence manner, so as to implement the synchronous operation of the master 11 and the slaves 12.
Through the technical means, the utility model has the following technical effects:
first, the present invention has five LED video processors 1 with the same structure, and any one of the LED video processors 1 can be used as a master 11, and the remaining four can be used as slaves 12. The host 11 is connected with the upper computer 6 through the communication interface component 4 on the synchronous card 2 to transmit control signals and data signals, and the four slave computers 12 are connected with one synchronous signal output interface 52 on the synchronous card 2 of the host 11 through a synchronous signal input interface 51 on the synchronous card 2 of the slave computers by cables, so that multi-computer cascade connection is realized. Compared with the method of processing image signals by using a single LED video processor 1, the method of processing the image signals by using the multi-core processing mode in the CPU of the computer is used for connecting the LED video processors 1 in a cascade mode, the cascade mode enhances the processing capacity of the method of processing multi-channel and high-definition image signals, and the method is more suitable for being applied to large-size stage LED display screens. Moreover, the clock of the device of the utility model is derived from a crystal oscillator on a synchronous card 2 of a host 11 to generate a homologous clock, thereby ensuring the beat synchronization of the image processing chips of the LED video processors 1, and the pictures output by each LED video processor 1 are delayed and synchronized during switching or between frames through line synchronization and field synchronization, thereby ensuring that the synchronous signals used by the host 11 and four slave computers 12 are nearly consistent, and ensuring the synchronization of image processing to the maximum extent, thereby realizing the purpose of cascade synchronization of a plurality of LED video processors 1 of the device of the utility model, ensuring that the image signals output by the device of the utility model can be stably played on an LED display screen, and solving the problems of splitting and twisting of the played pictures in the prior art.
Meanwhile, the LED video processors 1 of the device use the same clock and synchronous signals, and the device has more advantages than the pure use of VS frame synchronization.
Moreover, the image processing effect of the utility model has more advantages in the aspects of transmission delay and synchronization compared with the DDR cache synchronization products in the current market.
In addition, the structure of each LED video processor 1 in the device is the same, any LED video processor 1 can be used as a host 11 or a slave 12, and all machine positions can be replaced mutually, so that multi-machine cascade combination is facilitated, the probability of connection failure is reduced to the maximum extent, and the effect of multi-machine cascade is ensured. Moreover, parts of each LED video processor 1 can be used and replaced universally, and the later use and maintenance cost of a user is greatly reduced.
Preferably, the number of slave machines 12 in the apparatus of the present invention is set to four or less, and therefore the number of synchronization signal output interfaces 52 on the synchronization card 2 of each LED video processor 1 is set to four or less.
The utility model can control the number of the slave computers 12 to be less than four, can meet the use requirements of most large-size spliced LED display screens in a one-level cascade mode, and is beneficial to reducing the production and manufacturing cost of the synchronous card 2. If the number of the spliced LED display screens is too large, more than five LED video processors 1 can be cascaded in two, three or more stages through the synchronous card 2, for example, the slave 12 connected to the master 11 can be used as the next-stage sub-master 11, so that the total amount of the LED video processors 1 of the device is increased, and the playing requirement of the huge LED display screens is met.
Preferably, the synchronization signal input interface 51 and the synchronization signal output interface 52 of the synchronization signal interface module 5 of the synchronization card 2 of the present invention are both RJ45 interfaces, and a shielded ultra-five network cable is selected for connection during actual assembly connection.
The synchronous signal interface component 5 on the synchronous card 2 adopts an RJ45 interface, so that the production and manufacturing cost of the synchronous card can be reduced, the RJ45 interface has no signal attenuation, the synchronous signal connection between the host 11 and the slave 12 can be realized through a network cable, and the synchronous signal interface component is convenient for material taking and assembly. Meanwhile, the connection reliability of the network cable connected with the RJ45 interface is higher, and the network cable has certain dustproof and waterproof capabilities, so that the reliability of the network cable connector is improved, the service life of the network cable connector is prolonged, and the cost is reduced.
Preferably, referring to fig. 4, the communication interface component 4 on the synchronization card 2 of each LED video processor 1 of the present invention includes a network interface 41, a USB interface 42 and a DB9 interface 43.
The synchronous card 2 is provided with three communication interfaces with different specifications and models, so that the types of the upper computers 6 which can be connected by the host 11 are more, the problem that the host 11 cannot be connected to a certain specific upper computer 6 for use due to the limitation of the types of the communication interfaces in the actual use process is avoided, the use range of the synchronous card is favorably widened, and the synchronous card is higher in applicability.
Further, referring to fig. 1 to fig. 3, the clock synchronization chip 3 of each synchronization card 2 of each LED video processor 1 of the present invention includes a status management module 31 and a synchronization signal transceiver module 32 connected to the status management module 31.
In actual use, the synchronization signal transceiver module 32 on the synchronization card 2 of the master 11 outputs four sets of the same-source differential clock signal and the line-field synchronization signal through the synchronization signal output interface 52 on the synchronization card 2 under the control of the state management module 31, and the synchronization signal transceiver module 32 on the synchronization card 2 of each slave 12 receives one set of the same-source differential clock signal and the line-field synchronization signal output by the master 11 through the synchronization signal input interface 51 on the synchronization card 2 under the control of the state management module 31.
Further, the synchronization signal transceiver module 32 of each synchronization card 2 of the present invention includes a synchronization clock generator 321, a field sync/line sync generator 322, a clock buffer323 and a synchronization clock receiver 324, and when in actual use, the synchronization clock generator 321 of the synchronization card 2 of the host 11 generates a clock signal through a crystal oscillator under the control of its state management module 31 and sends the clock signal to its clock buffer323 for copying, and the clock buffer323 outputs four sets of homologous differential clock signals. The field sync/line sync generator 322 on the sync card 2 of the master 11 generates four sets of line field sync signals under the control of its state management module 31, and the four sets of line field sync signals and the four sets of same source differential clock signals are correspondingly sent to the four slaves 12 through the four sync signal output interfaces 52 on the sync card 2 of the master 11. The synchronizing clock receiver 324 of the synchronizing signal transceiver module 32 on the synchronizing card 2 of each slave 12 receives one set of the same-source differential clock signal and the line-field synchronizing signal transmitted by the master 11 through a synchronizing signal input interface 51 on the synchronizing card 2 of the slave 12.
The LED video processors 1 realize the synchronization of three modes of clock, line and field through the synchronous card 2, and because the synchronous signals of the clock, the line and the field of the same source are used, the difference of the whole image processing system is reduced, the error of the system is reduced, the input and output time sequence phases of data are consistent due to the clock synchronization, and the delay difference of each frame is reduced due to the same line and field scanning, thereby realizing the purpose of synchronizing the LED video processors 1 of the device.
The first one of the cascade system of the present invention is the master 11, which sends out the synchronization signals of at most four slave machines 12, and these synchronization signals include the homodyne differential clock signal and the line-field synchronization signal, so as to ensure that the synchronization signals used by the master 11 and all four slave machines 12 are nearly identical. Since all the five cascaded LED video processors 1 use the same synchronization signal sent by the host 11, the apparatus of the present invention can ensure that all the cascaded LED video processors 1 can achieve synchronization of image processing to the maximum extent.
In addition, the clock synchronization chip 3 on the synchronization card 2 of each LED video processor 1 of the device of the present invention preferably uses a master clock generation chip produced by IDT corporation, and is a differential clock with strong anti-interference capability that can support up to 5 paths, so that these differential clocks are considered as the same source clocks in the industry. Similarly, the HS/VS is generated by the CPLD and is also generated by the driving circuit as a set of five paths respectively with the clock, and is transmitted to the slave 12 end through the RJ45 interface to complete the synchronous transmission, and the slave 12 performs the image processing by using the differential clock, the line synchronization and the field synchronization, so that the device of the present invention has advantages in the aspects of transmission delay and synchronization of the processing effect compared with the DDR cache synchronization on the market.
The above examples are merely for the purpose of clarifying a specific embodiment of the present invention and are not intended to limit the scope of the present invention. For those skilled in the art, it is obvious that other adjustments or changes to the LED video processor 1, the synchronization card 2, the clock synchronization chip 3, the communication interface component 4, the synchronization signal interface component 5, etc. can be deduced and summarized according to the present invention, and they are not listed here. Any modification, replacement or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (6)
1. The utility model provides a many LED video processor cascade synchronization device, includes the LED video processor of at least two, its characterized in that: each LED video processor is internally provided with a synchronous card, each synchronous card is provided with a clock synchronization chip, a communication interface component and a synchronous signal interface component, the communication interface component and the synchronous signal interface component are connected with the clock synchronization chip, and the synchronous signal interface component comprises a synchronous signal input interface and at least one synchronous signal output interface; one of the LED video processors is a host, is connected with an upper computer through the communication interface component on the synchronous card thereof to send a system command to the device, and the other LED video processors are slaves, and are connected with one of the synchronous signal output interfaces of the host through the synchronous signal input interface on the synchronous card thereof through a cable to form multi-computer cascade; the clock synchronization chip of the host outputs at least one group of homologous differential clock signals and line-field synchronization signals, and the homologous differential clock signals and the line-field synchronization signals are respectively transmitted to the slave computers connected with the clock synchronization chip through the synchronization signal output interface on the host through the cable.
2. The cascade synchronization device of multiple LED video processors of claim 1, wherein: the number of the slave machines is less than four, and the number of the synchronous signal output interfaces on the same synchronous card is less than four.
3. The cascade synchronization device of multiple LED video processors of claim 1, wherein: the synchronous signal input interface and the synchronous signal output interface are both RJ45 interfaces.
4. The cascade synchronization device of multiple LED video processors of claim 1, wherein: the communication interface component comprises a network interface, a USB interface and a DB9 interface.
5. The cascade synchronization device of multiple LED video processors of claim 1, wherein: the clock synchronization chip comprises a state management module and a synchronization signal transceiver module connected with the state management module, the synchronization signal transceiver module of the host outputs at least one group of the homologous differential clock signals and the line field synchronization signals through the synchronization signal output interface under the control of the state management module, and the synchronization signal transceiver module of the slave receives one group of the homologous differential clock signals and the line field synchronization signals output by the host through the synchronization signal input interface under the control of the state management module.
6. The cascaded synchronization device of claim 5, wherein: the synchronous signal transceiver module comprises a synchronous clock generator, a field synchronization/line synchronization generator, a clock buffer and a synchronous clock receiver, wherein the synchronous clock generator of the master computer generates clock signals through a crystal oscillator under the control of the state management module and sends the clock signals to the clock buffer for copying, the clock buffer outputs four groups of homologous differential clock signals at most, the field synchronization/line synchronization generator of the master computer generates four groups of line field synchronization signals at most under the control of the state management module and sends the line field synchronization signals and the homologous differential clock signals to the slave computer in a one-to-one correspondence mode through the synchronous signal output interface of the master computer; and the synchronous clock receiver of the synchronous signal transceiving module of the slave receives one group of homologous differential clock signals and horizontal field synchronous signals transmitted by the master through the synchronous signal input interface of the slave.
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| CN202122137349.8U CN215577631U (en) | 2021-09-06 | 2021-09-06 | Cascade synchronization device for multiple LED video processors |
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| CN202122137349.8U CN215577631U (en) | 2021-09-06 | 2021-09-06 | Cascade synchronization device for multiple LED video processors |
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