CN215527203U

CN215527203U - Shifting register unit, grid driving circuit and display panel

Info

Publication number: CN215527203U
Application number: CN202120963742.XU
Authority: CN
Inventors: 何静; 郑浩旋
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2021-05-07
Filing date: 2021-05-07
Publication date: 2022-01-14
Anticipated expiration: 2031-05-07

Abstract

The utility model provides a shift register unit, a grid drive circuit and a display panel, wherein the shift register unit comprises: the auxiliary control subcircuit is used for providing a reference voltage for the reference node; the input sub-circuit is used for transmitting a first voltage provided by a first voltage end to a pull-up node under the control of an input voltage provided by an input end; the auxiliary control sub-circuit is also used for conducting the pull-up node and the reference node under the control of a first control voltage provided by the first control end, so that the voltage at the pull-up node is at least the first voltage; the control sub-circuit is used for transmitting a clock signal provided by a clock signal end to an output end under the control of the voltage of the pull-up node, and pulling up a first voltage at the pull-up node to an intermediate voltage together with the auxiliary control sub-circuit. The voltage at the pull-up node is further raised to the intermediate voltage from the first voltage, so that the problem that the voltage at the pull-up node is pulled down by electric leakage is avoided, and the actual charging time is prolonged.

Description

Shifting register unit, grid driving circuit and display panel

Technical Field

The utility model belongs to the technical field of display, and particularly relates to a shift register unit, a driving method, a grid driving circuit and a display panel.

Background

In the field of display technology, a pixel array such as a liquid crystal display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith. The driving of the gate line may be realized by a gate driving circuit. For example, the gate driving circuit may be implemented by a bonded integrated driving circuit.

In recent years, with the continuous improvement of the manufacturing process of the amorphous silicon thin film transistor or the oxide thin film transistor, a Gate driving circuit may be directly integrated On the Array substrate to form a Gate-driver On Array (GOA) to provide a switching voltage signal to the Gate lines, so as to control a plurality of rows of the Gate lines to be sequentially turned On according to a preset sequence, and simultaneously, a data line provides a data signal to the pixel units of the corresponding row in the pixel Array, so as to form a gray scale voltage required by each gray scale of a display image in each pixel unit, and display an image of one frame.

The present display panel increasingly uses the GOA technology to drive the gate lines.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a shift register unit, a grid drive circuit and a display panel, wherein the voltage at a pull-up node is further raised to an intermediate voltage from a first voltage, so that the problem that the voltage at the pull-up node is pulled down by leakage is avoided, and the actual charging time is prolonged.

In a first aspect, a shift register unit is provided, including: the circuit comprises an auxiliary control sub-circuit, an input sub-circuit, a control sub-circuit, an input end, an output end, a clock signal end, a first voltage end, a first control end and a pull-up node;

the auxiliary control sub-circuit comprises a reference node, and the auxiliary control sub-circuit is used for providing a reference voltage for the reference node;

the input sub-circuit is electrically connected with the input end, the first voltage end and the pull-up node, and is used for transmitting a first voltage provided by the first voltage end to the pull-up node under the control of an input voltage provided by the input end;

the auxiliary control sub-circuit is electrically connected with the first control terminal, the pull-up node and the output terminal, and is further configured to turn on the pull-up node and the reference node under control of a first control voltage provided by the first control terminal, so that a voltage at the pull-up node is at least the first voltage, and the reference voltage is greater than or equal to the first voltage;

the control sub-circuit is electrically connected with the pull-up node, the clock signal end and the output end, and the control sub-circuit is used for transmitting a clock signal provided by the clock signal end to the output end under the control of the voltage of the pull-up node and pulling up the first voltage at the pull-up node to an intermediate voltage together with the auxiliary control sub-circuit.

The embodiment of the utility model provides a shift register unit, which is characterized in that an auxiliary control sub-circuit comprising a reference node is added in the shift register unit, a reference voltage is provided for the reference node, then a pull-up node is controlled to be conducted with the reference node, the voltage at the pull-up node is at least a first voltage, and the voltage at the pull-up node is further raised to an intermediate voltage, so that the voltage at the pull-up node is prevented from being lowered by leakage of other transistors, the actual charging time is prolonged, the problem that the charging time corresponding to each row of sub-pixels P is shortened is solved, the charging rate is ensured, and the occurrence of wrong charging can be effectively prevented.

With reference to the first aspect, the shift register unit further includes a reset sub-circuit, a reset terminal, and a second voltage terminal; the reset sub-circuit is electrically connected with the reset end, the second voltage end, the pull-up node and the output end, and the reset sub-circuit is used for transmitting the second voltage provided by the second voltage end to the pull-up node and the output end under the control of the reset voltage provided by the reset end, and resetting the pull-up node and the output end.

With reference to the first aspect, the input sub-circuit includes a first transistor, a gate of the first transistor is electrically connected to the input terminal, a first electrode of the first transistor is electrically connected to the first voltage terminal, and a second electrode of the first transistor is electrically connected to the pull-up node.

With reference to the first aspect, the control sub-circuit includes a second transistor and a first capacitor; the grid electrode of the second transistor and the first electrode of the first capacitor are electrically connected with the pull-up node, the first electrode of the second transistor is electrically connected with the clock signal end, and the second electrode of the second transistor and the second electrode of the first capacitor are electrically connected with the output end.

With reference to the first aspect, the shift register further includes a second control terminal and a third control terminal; the auxiliary control sub-circuit is further electrically connected with the second control terminal and the third control terminal, and the auxiliary control sub-circuit is configured to transmit the reference voltage provided by the third control terminal to the reference node under the control of the second control voltage provided by the second control terminal.

With reference to the first aspect, the auxiliary control sub-circuit includes a third transistor, a fourth transistor, and a second capacitor; a gate of the third transistor is electrically connected to the first control terminal, a first electrode of the third transistor is electrically connected to the pull-up node, and a second electrode of the third transistor is electrically connected to the reference node; a gate of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the third control terminal, and a second electrode of the fourth transistor is electrically connected to the reference node; the first pole of the second capacitor is electrically connected to the reference node, and the second pole of the second capacitor is electrically connected to the output terminal.

With reference to the first aspect, the third control terminal is electrically connected to the first voltage terminal.

With reference to the first aspect, the reset sub-circuit includes a fifth transistor and a sixth transistor; a gate of the fifth transistor is electrically connected to the reset terminal, a first electrode of the fifth transistor is electrically connected to the pull-up node, and a second electrode of the fifth transistor is electrically connected to the second voltage terminal; the grid electrode of the sixth transistor is electrically connected with the reset end, the first electrode of the sixth transistor is electrically connected with the output end, and the second electrode of the sixth transistor is electrically connected with the second voltage end.

In a second aspect, a gate driving circuit is provided, which includes a plurality of cascaded shift register units according to any one of the implementations of the first aspect and the first aspect; the output end of the first-stage shift register unit is electrically connected with the input end of the second-stage shift register unit; the output end of the last stage of shift register unit is electrically connected with the reset end of the previous stage of shift register unit; except the first stage shift register unit and the last stage shift register unit, the output end of each shift register unit is electrically connected with the reset end of the previous stage shift register unit and the input end of the next stage shift register unit.

In a third aspect, a display panel is provided, which includes the gate driving circuit as described in the second aspect.

The embodiment of the utility model provides a shift register unit, a gate drive circuit and a display panel, wherein an auxiliary control sub-circuit comprising a reference node is added in the shift register unit, a reference voltage is provided for the reference node, then a pull-up node and the reference node are controlled to be conducted, the voltage at the pull-up node is at least a first voltage, and the voltage at the pull-up node is further raised to an intermediate voltage, so that the voltage at the pull-up node is prevented from being pulled down by leakage of other transistors, the actual charging time is prolonged, the problem that the charging time corresponding to each row of sub-pixels is shortened is solved, the charging rate is ensured, and wrong charging can be effectively prevented.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is a schematic top view of a display panel;

FIG. 2 is a schematic diagram of the gate driving circuit of FIG. 1;

FIG. 3 is a circuit diagram of a shift register unit in an exemplary technique;

FIG. 4 is an equivalent circuit diagram of the shift register unit of FIG. 3 at different stages;

FIG. 5 is a timing diagram of the shift register unit of FIG. 3;

FIG. 6 is a block diagram of a shift register unit according to the present invention;

FIG. 7 is a block diagram of another shift register unit according to the present invention;

FIG. 8 is a block diagram of a shift register unit according to another embodiment of the present invention;

FIG. 9 is a circuit diagram of a shift register unit according to the present invention;

FIG. 10 is an equivalent circuit diagram of the shift register cell of FIG. 9 at stage t 1;

FIG. 11 is an equivalent circuit diagram of the shift register cell of FIG. 9 at stage t 2;

FIG. 12 is an equivalent circuit diagram of the shift register cell of FIG. 9 at stage t 3;

FIG. 13 is an equivalent circuit diagram of the shift register cell of FIG. 9 at stage t 4;

FIG. 14 is an equivalent circuit diagram of the shift register cell of FIG. 9 at stage t 5;

fig. 15 is a timing diagram for the shift register unit of fig. 9.

Reference numerals:

1-a display panel; 2-a gate drive circuit; a P-subpixel; 3-a pixel drive circuit; d-an element to be driven; 20-a shift register unit; 200-an auxiliary control sub-circuit; 210-an input sub-circuit; 220-a control sub-circuit; 230-a reset sub-circuit; m1 — first transistor; m2 — second transistor; m3 — third transistor; m4 — fourth transistor; m5 — fifth transistor; m6 — sixth transistor; c1 — first capacitance; c2 — second capacitance; an STV-input; VDS-first voltage terminal; CLK-clock signal terminal; GOUT-output end; rst-reset terminal; VGL-a second voltage terminal; PU-pull-up node; PD-reference node; s1-a first control end; s2-a second control end; s3 — third control terminal.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.

In the description of the embodiments of the present invention, "/" indicates an OR meaning unless otherwise specified, for example, A/B may indicate A or B; "and/or" herein is merely an association describing an associated object, and means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present embodiment, "a plurality" means two or more unless otherwise specified.

The directional terms "left", "right", "upper" and "lower" are defined with respect to the orientation in which the display assembly is schematically placed in the drawings, and it is to be understood that these directional terms are relative concepts, which are used for descriptive and clarifying purposes, and may be changed accordingly according to the change of the orientation in which the array substrate or the display device is placed.

An embodiment of the present invention provides a display panel, which is suitable for a display device, and the display device may be a self-Light Emitting display device such as an Organic Light Emitting Diode (OLED) display device, a Micro Light Emitting Diode (Micro LED) display device, and a Mini Light Emitting Diode (Mini LED) display device, and has the features of small size, low power consumption, good display effect, no radiation, relatively low manufacturing cost, and the like, so that the display panel is increasingly applied to the high performance display field.

Of course, the display device may also be a liquid crystal display device. For example, the display device at least includes a display panel, and the display device may be a product or a component having any display function, such as a display, a television, a digital camera, a mobile phone, and a tablet computer. The embodiment of the present invention does not limit this.

Fig. 1 shows a schematic top view of a display panel. As shown in fig. 1, the display panel includes a plurality of subpixels P and a gate driving circuit 2.

The plurality of sub-pixels P are uniformly distributed in a matrix, and each sub-pixel P is provided with a pixel driving circuit 3 and an element D to be driven connected with the pixel driving circuit 3. The element D to be driven is a light emitting device of a current drive type. Further, the Light Emitting device may be an electric current type Light Emitting diode, such as a micro Light Emitting diode, a mini Light Emitting diode, an organic electroluminescent diode, or a Quantum Dot Light Emitting diode (QLED), and the like, which is not limited in this embodiment of the utility model.

It should be understood that, as shown in fig. 1, the plurality of sub-pixels P arranged in the x direction are referred to as a row of sub-pixels P, and the plurality of sub-pixels P arranged in the y direction are referred to as a column of sub-pixels P, in which case, the x direction is a row direction and the y direction is a column direction.

In addition, the embodiment of the present invention does not limit the specific structure of the pixel driving circuit 3.

Fig. 2 shows a schematic structural diagram of the gate driving circuit in fig. 1. As shown in fig. 1 and 2, the gate driving circuit 2 in the display panel 1 includes a plurality of cascaded shift register units 20, and each shift register unit 20 is electrically connected to all the pixel driving circuits 3 in a row of sub-pixels P.

As shown in fig. 2, when the plurality of shift register units 20 in the gate driving circuit 2 are cascaded, the cascade connection is realized through the output terminal GOUT.

Wherein, specific connection structure is: the output terminal GOUT of the first stage shift register unit 20 is electrically connected to the input terminal STV of the second stage shift register unit 20. The output terminal GOUT of the last stage shift register unit 20 is electrically connected to the reset terminal Rst of the previous stage shift register.

Except for the first stage shift register unit 20 and the last stage shift register unit 20, the output terminal GOUT of the other shift register units 20 is electrically connected to the reset terminal Rst of the previous stage shift register unit 20 and the input terminal STV of the next stage shift register unit 20.

The above cascade connection manner of the gate driving circuit 2 can provide the pixel driving circuit 3 with the gate driving signal required by it.

The structure of the gate driver circuit 2 is described in detail with reference to fig. 1 and 2, and the circuit structure of the shift register unit 20 in the gate driver circuit 2 provided in the example technology is described with reference to fig. 3.

Fig. 3 shows a circuit configuration diagram of a shift register unit in an example technique. As shown in fig. 3, in the example technology, the shift register unit 20 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a first capacitor C1.

The gate of the first transistor M1 is electrically connected to the input terminal STV, the first pole of the first transistor M1 is electrically connected to the first voltage terminal VDS, and the second pole of the first transistor M1 is electrically connected to the pull-up node PU. The gate of the second transistor M2 is electrically connected to the pull-up node PU, the first pole of the second transistor M2 is electrically connected to the clock signal terminal CLK, and the second pole of the second transistor M2 is electrically connected to the output terminal GOUT. A first pole of the first capacitor C1 is electrically connected to the pull-up node PU, and a second pole is electrically connected to the output terminal GOUT. A gate of the third transistor M3 is electrically connected to the reset terminal Rst, a first pole of the third transistor M3 is electrically connected to the pull-up node PU, and a second pole of the third transistor M3 is electrically connected to the second voltage terminal VGL. A gate of the fourth transistor M4 is electrically connected to the reset terminal Rst, a first pole of the fourth transistor is electrically connected to the output terminal GOUT, and a second pole of the fourth transistor M4 is electrically connected to the second voltage terminal VGL.

Here, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all N-type MOS transistors.

Based on the structure described in fig. 3, a driving method corresponding to the shift register unit 20 provided by the exemplary technology will be described with reference to fig. 4 and 5. Fig. 4 is an equivalent circuit diagram of the shift register unit in fig. 3 at different stages, and fig. 5 is a timing diagram of the shift register unit in fig. 3. Fig. 5 (a) shows an ideal timing chart corresponding to fig. 3, and fig. 5 (b) shows an actual timing chart corresponding to fig. 3.

As shown in fig. 4 and 5, it is assumed that the first voltage terminal VDS inputs a high level a and the second voltage terminal VGL inputs a low level.

At the stage t1, as shown in (a) of fig. 4, the inputs of the input terminal STV, the clock signal terminal CLK and the reset terminal Rst are all low, so that all transistors are turned off and do not operate.

When the input of the input terminal STV changes from low level to high level at stage t2 as shown in (b) of fig. 4, the first transistor M1 is turned on, and the high level a of the first voltage terminal VDS input is transmitted to the pull-up node PU, i.e., the pull-up node PU is set high; accordingly, the second transistor M2 will be turned on, but the input of the clock signal terminal CLK is low, so the output of the output terminal GOUT is low.

At the stage t3, as shown in (C) of fig. 4, the input of the input terminal STV changes from high level to low level, the first transistor M1 is turned off, and the input of the clock signal terminal CLK changes from low level to high level, so that the second pole of the first capacitor C1 is high level and the output of the output terminal GOUT is high level, and accordingly, the level of the first pole of the second capacitor C1 will be raised according to the capacitive coupling principle, for example, the level at the pull-up node PU is pulled up from a to b.

At the stage t4, as shown in (d) of fig. 4, the inputs of the input terminal STV and the clock signal terminal CLK are all low, the first transistor M1 and the second transistor M2 are both turned off, the reset terminal Rst is high, the third transistor M3 and the fourth transistor M4 are turned on, and at this time, the output terminal GOUT is pulled down by the low level provided by the second input terminal VGL, and the voltage at the pull-up node PU is pulled down according to the capacitive coupling principle, and because the low level provided by the second input terminal VGL is also transmitted to the pull-up node PU, the voltage at the pull-up node PU is further pulled down.

The stages t1 to t4 are driving methods of the shift register unit 20. However, in an actual product, the switching characteristics of the transistor are not perfect, there may be leakage when the transistor is turned off, and generally the wider the channel, the greater the leakage. Thus, as shown in (b) in fig. 5, when the stage t3 is entered, the first transistor M1, the third transistor M3 and the fourth transistor M4 are all turned off, and the voltage at the output terminal GOUT may be delayed by a long delay time of the rising edge due to the leakage of the fourth transistor M4; also, the voltage at the pull-up node PU may be dropped due to leakage of the third transistor M3, that is, the gate voltage of the second transistor M2 may be decreased.

The gate voltage of the second transistor M2 becomes small, which causes the voltage difference between the gate and the first pole (source) of the second transistor M2 to become small, the second transistor M2 is turned off, the voltage at the output terminal GOUT drops, and thus the falling edge delay time of the output terminal GOUT is also lengthened. Therefore, the effective time of the output terminal GOUT outputting the high level, that is, the charging time period corresponding to each row of the sub-pixels P is reduced, and at this time, a problem of insufficient charging is easily caused, and even a problem of erroneous charging may be caused.

In view of this, an embodiment of the present invention provides a shift register unit, in which an auxiliary control sub-circuit including a reference node is added to the shift register unit, a reference voltage is provided to the reference node, and then a pull-up node and the reference node are controlled to be turned on, so that a voltage at the pull-up node is at least a first voltage, and then the voltage at the pull-up node is further raised to an intermediate voltage, thereby preventing a leakage of other transistors from pulling down the voltage at the pull-up node, prolonging an actual charging time, and further solving a problem that a charging duration corresponding to each row of sub-pixels P is shortened.

The structure of the shift register unit provided by the present invention is described in detail below with reference to fig. 6 to 9, and fig. 6 is a block diagram of a circuit structure of the shift register unit provided by the present invention. Fig. 7 is a block diagram of another circuit structure of the shift register unit according to the present invention. Fig. 8 is a block diagram of a circuit structure of another shift register unit according to the present invention. Fig. 9 is a circuit structure diagram of a shift register unit according to the present invention.

An embodiment of the present invention provides a shift register unit, as shown in fig. 6, including: auxiliary control sub-circuit 200, input sub-circuit 210 and control sub-circuit 220, as well as input STV, output GOUT, clock signal terminal CLK, first voltage terminal VDS, first control terminal S1 and pull-up node PU.

As shown in fig. 6, the auxiliary control sub-circuit 200 includes a reference node PD, and the auxiliary control sub-circuit 200 is configured to provide a reference voltage to the reference node PD.

The input sub-circuit 210 is electrically connected to the input terminal STV, the first voltage terminal VDS, and the pull-up node PU, and the input sub-circuit 210 is configured to transmit the first voltage provided by the first voltage terminal VDS to the pull-up node PU under the control of the input voltage provided by the input terminal STV.

For example, the first voltage provided by the first voltage terminal VDS is a high level Ua, the input sub-circuit 210 may turn on a circuit between the first voltage VDS and the pull-up node PU under the control of the input terminal STV, so that the high level Ua provided by the first voltage terminal VDS may be transmitted to the pull-up node PU, so that the voltage at the pull-up node PU is raised, which is a process of charging the pull-up node PU.

Of course, the embodiment of the present invention is not limited thereto, for example, the input sub-circuit 210 may be connected to a voltage terminal provided additionally, and the present invention is not limited thereto.

The auxiliary control sub-circuit 200 is electrically connected to the first control terminal S1, the pull-up node PU, and the output terminal GOUT, and the auxiliary control sub-circuit 200 is further configured to turn on the pull-up node PU and the reference node PD under the control of a first control voltage provided by the first control terminal S1, so that the voltage at the pull-up node PU is at least a first voltage, and the reference voltage is greater than or equal to the first voltage.

It should be understood that when the reference voltage is equal to the first voltage, and the auxiliary control sub-circuit 200 controls the pull-up node PU and the reference node PD to be turned on, no current flows between the pull-up node PU and the reference node PD, so that the voltage at the pull-up node PU may continue to be maintained at the first voltage.

When the reference voltage is greater than the first voltage, when the auxiliary control sub-circuit 200 controls the pull-up node PU and the reference node PD to be turned on, a current from the reference node PD to the pull-up node PU may be generated, so as to charge the pull-up node PU, and thus the voltage at the pull-up node PU is increased.

Based on the above structure, even if some transistor leakage occurs in the shift register unit 20, the voltage at the pull-up node PU can be compensated by the reference voltage at the reference node PD, so as to maintain the voltage at the pull-up node PU to be at least the first voltage, ensure that the second transistor M2 can normally operate, and further ensure that the charging duration of the sub-pixel P is normal.

The control sub-circuit 220 is electrically connected to the pull-up node PU, the clock signal terminal CLK, and the output terminal GOUT, and the control sub-circuit 220 is configured to transmit the clock signal provided by the clock signal terminal CLK to the output terminal GOUT under the control of the voltage of the pull-up node PU, and pull up the first voltage at the pull-up node PU to an intermediate voltage together with the auxiliary control sub-circuit 200.

It should be understood that when the pixel driving circuit 3 in the sub-pixel includes an enable signal terminal, the output terminal GOUT of the shift register unit 20 is used for being electrically connected with the enable signal terminal of the pixel driving circuit 3 for providing an enable signal for the enable signal terminal, that is, the output signal output by the output terminal GOUT will be used as the enable signal in the pixel driving circuit, and the enable signal can also be referred to as a gate driving signal.

It should be understood that the control sub-circuit 220 and the auxiliary control sub-circuit 200 together raise the voltage at the pull-up node PU from the first voltage to the intermediate voltage, and even if the other transistors leak, it is difficult to pull the voltage at the pull-up node PU low, so that the effective time of the output terminal GOUT is prolonged.

Optionally, as a possible implementation manner, as shown in fig. 7 and fig. 8, the shift register unit provided in this embodiment of the present invention further includes a reset sub-circuit 230, a reset terminal Rst, and a second voltage terminal VGL.

The reset sub-circuit 230 is electrically connected to the reset terminal Rst, the second voltage terminal VGL, the pull-up node PU, and the output terminal GOUT, and the reset sub-circuit 230 is configured to transmit the second voltage provided by the second voltage terminal VGL to the pull-up node PU and the output terminal GOUT under the control of the reset voltage provided by the reset terminal Rst, and reset the pull-up node PU and the output terminal GOUT.

It is to be understood that the first voltage and the second voltage are different, and illustratively, the second voltage is low when the first voltage is high. When the first voltage is transmitted to the pull-up node PU, the voltage at the pull-up node PU starts to rise, and when the second voltage is transmitted to the pull-up node PU, the voltage at the pull-up node PU starts to fall.

Further, "high" and "low" merely indicate a relative magnitude relationship between the input voltages. The second voltage terminal VGL may also be grounded.

Alternatively, as a possible implementation manner, as shown in fig. 9, the input sub-circuit 210 includes a first transistor M1, a gate of the first transistor M1 is electrically connected to the input terminal STV, a first pole of the first transistor M1 is electrically connected to the first voltage terminal VDS, and a second pole of the first transistor M1 is electrically connected to the pull-up node PU.

It should be understood that the first transistor M1 is used for turning on under the control of the input voltage at the input terminal STV, and transmitting the first voltage provided by the first voltage terminal VDS to the pull-up node PU.

It should be understood that the input sub-circuit 210 may also include a plurality of switching transistors in parallel with the first transistor M1. The above is merely an illustration of the input sub-circuit 210, and other structures having the same functions as the input sub-circuit 210 are not described in detail here, but all of them should fall into the protection scope of the present invention.

Optionally, as a possible implementation, as shown in fig. 9, the control sub-circuit 220 includes a second transistor M2 and a first capacitor C1.

The gate of the second transistor M2 and the first pole of the first capacitor C1 are both electrically connected to the pull-up node PU, the first pole of the second transistor M2 is electrically connected to the clock signal terminal CLK, and the second pole of the second transistor M2 and the second pole of the first capacitor C1 are both electrically connected to the output terminal.

It should be understood that the second transistor M2 is turned on under the control of the voltage at the pull-up node PU to transmit the clock signal provided by the clock signal terminal CLK to the output terminal GOUT, i.e., the clock signal CLK is to be output as the gate driving signal. Meanwhile, since the output terminal GOUT is electrically connected to the second pole of the first capacitor C1, according to the capacitive coupling principle, the voltage of the second pole of the capacitor rises, and correspondingly, the voltage of the first pole of the capacitor also rises, i.e., the voltage at the pull-up node PU is continuously pulled up from the first voltage.

It should be appreciated that the control sub-circuit 220 may also include a plurality of switching transistors in parallel with the second transistor M2, and/or a plurality of capacitors in parallel with the first capacitor C1. The above is merely an illustration of the control sub-circuit 220, and other structures having the same functions as the control sub-circuit 220 are not described in detail herein, but all of them should fall within the scope of the present invention.

Alternatively, as a possible implementation manner, as shown in fig. 7 to 9, the shift register unit 20 further includes a second control terminal S2 and a third control terminal S3.

The auxiliary control sub-circuit 200 is further connected to the second control terminal S2 and the third control terminal S3, and the auxiliary control sub-circuit 200 is configured to transmit the reference voltage provided by the third control terminal S3 to the reference node PD under the control of the second control voltage provided by the second control terminal S2.

Of course, the embodiment of the present invention is not limited thereto, for example, the auxiliary control sub-circuit 200 may be connected to a voltage terminal additionally provided, and the present invention is not limited thereto.

Alternatively, as a possible implementation, as shown in fig. 8, the third control terminal S3 is electrically connected to the first voltage terminal STV.

It should be appreciated that since the circuit between the pull-up node PU and the reference node PD is not directly connected, the third control terminal S3 can be electrically connected with the first voltage terminal STV, saving cost. At this time, the third control terminal S3 is electrically connected to the first voltage terminal VDS, and the first voltage provided by the first voltage terminal VDS is transmitted to the pull-up node PU, and meanwhile, the first voltage can be transmitted to the reference node PD as the reference voltage provided by the third control terminal S3.

Alternatively, as a possible implementation manner, as shown in fig. 9, the auxiliary control sub-circuit 200 includes a third transistor M3, a fourth transistor M4, and a second capacitor C2.

The gate of the third transistor M3 is electrically connected to the first control terminal S1, the first pole of the third transistor M3 is electrically connected to the pull-up node PU, and the second pole of the third transistor M3 is electrically connected to the reference node PD.

The gate of the fourth transistor M4 is electrically connected to the second control terminal S2, the first pole of the fourth transistor M4 is electrically connected to the third control terminal S3, and the second pole of the fourth transistor M4 is electrically connected to the reference node PD.

A first pole of the second capacitor C2 is electrically connected to the reference node PD, and a second pole of the second capacitor C2 is electrically connected to the output terminal GOUT.

It should be understood that the fourth transistor M4 is used for turning on under the control of the second control terminal S2, and transmitting the voltage provided by the third control terminal S3 as a reference voltage to the reference node PD.

The third transistor M3 is turned on under the control of the first control terminal S1, and turns on the reference node PD and the pull-up node PU, so as to provide the reference voltage at the reference node PD to the pull-up node PU, and make the voltage at the pull-up node PU at least be the first voltage.

Since the second capacitor C2 is connected in parallel with the first capacitor C1, the voltage at the first pole of the capacitor will increase even more when pulled high according to the capacitive coupling principle.

It should be understood that the auxiliary control sub-circuit 200 may further include a plurality of switching transistors connected in parallel with the third transistor M3, and/or a plurality of switching transistors connected in parallel with the fourth transistor M4, and/or a plurality of capacitors connected in parallel with the second capacitor C2. The above is merely an illustration of the control sub-circuit 220, and other structures having the same functions as the auxiliary control sub-circuit 200 are not described in detail herein, but all of them should fall within the scope of the present invention.

Optionally, as a possible implementation, the reset sub-circuit 230 includes a fifth transistor M5 and a sixth transistor M6.

A gate of the fifth transistor M5 is electrically connected to the reset terminal Rst, a first pole of the fifth transistor M5 is electrically connected to the pull-up node PU, and a second pole of the fifth transistor M5 is electrically connected to the second voltage terminal VGL.

A gate of the sixth transistor M6 is electrically connected to the reset terminal Rst, a first pole of the sixth transistor M6 is electrically connected to the output terminal GOUT, and a second pole of the sixth transistor M6 is electrically connected to the second voltage terminal VGL.

It should be understood that the fifth transistor M5 is turned on under the control of the reset voltage provided by the reset terminal Rst, and transmits the second voltage provided by the second voltage terminal VGL to the pull-up node PU to reset the voltage at the pull-up node PU.

It should be understood that the sixth transistor M6 is configured to turn on under the control of the reset voltage provided by the reset terminal Rst, and transmit the second voltage provided by the second voltage terminal VGL to the output terminal GOUT to reset the voltage at the output terminal GOUT. That is, the voltage on the second pole of the first capacitor C1 and the second pole of the second capacitor C2 is reset.

The structure of each sub-circuit is described in detail above, and the driving method of the shift register unit according to the embodiment of the present invention is described in detail below with reference to fig. 9 to 15.

Wherein, fig. 10 is an equivalent circuit diagram of the shift register unit in fig. 9 at stage t 1; FIG. 11 is an equivalent circuit diagram of the shift register cell of FIG. 9 at stage t 2; FIG. 12 is an equivalent circuit diagram of the shift register cell of FIG. 9 at stage t 3; FIG. 13 is an equivalent circuit diagram of the shift register cell of FIG. 9 at stage t 4; FIG. 14 is an equivalent circuit diagram of the shift register cell of FIG. 9 at stage t 5; fig. 15 is a timing diagram for the shift register unit of fig. 9.

An embodiment of the present invention further provides a driving method of the shift register unit, where the driving method includes:

during the preparation phase (i.e., the t2 phase), the auxiliary control sub-circuit 200 provides the reference voltage to the reference node PD.

An input stage (i.e., stage t 3), in which the input sub-circuit 210 transmits a first voltage provided by the first voltage terminal VDS to the pull-up node PU under the control of the input voltage provided by the input terminal STV; the auxiliary control sub-circuit 200 turns on the pull-up node PU and the reference node PD under the control of the first control voltage provided by the first control terminal S1, so that the voltage at the pull-up node PU is at least the first voltage.

In the output stage (i.e. the stage t 4), the control sub-circuit 220 transmits the clock signal provided by the clock signal terminal CLK to the output terminal GOUT under the control of the first voltage of the pull-up node PU, and pulls up the first voltage of the pull-up node to the intermediate voltage together with the auxiliary control sub-circuit 200.

The driving method of the shift register unit provided by the embodiment of the utility model has the same beneficial effects as the shift register unit provided by the embodiment of the utility model, and the description is omitted.

After the output phase, the driving method may further include a reset phase (i.e., a t5 phase), in which the reset sub-circuit 230 transmits the second voltage provided by the second voltage terminal VGL to the pull-up node PU and the output terminal GOUT under the control of the reset voltage provided by the reset terminal Rst, and resets the pull-up node PU and the output terminal GOUT.

Before the preparation phase, the driving method may further include a t1 phase. At stage t1, all ports of the shift register unit 20 are input with low level, so that all ports of the shift register unit 20 can be reset once to ensure that the subsequent shift register unit 20 can work normally.

The driving process of the shift register unit 20 shown in fig. 9 will be described in detail with reference to fig. 10 to 15, taking as an example that all the transistors are N-type transistors.

At stage t1, as shown in fig. 11, the input terminal STV, the first voltage terminal VDS, the clock signal terminal CLK, the reset terminal Rst, the second voltage terminal VGL, the first control terminal S1, the second control terminal S2, and the third control terminal all provide a low level to reset the shift register unit 20 once to ensure the subsequent normal operation.

At the stage t2, as shown in fig. 12, the input terminal STV, the clock signal terminal CLK, the reset terminal Rst and the first control terminal S1 all provide a low level, the first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5 and the sixth transistor M6 are all turned off, the second control voltage provided by the second control terminal S2 is a high level, and the fourth transistor M4 is turned on, so that the reference voltage provided by the third control terminal S3 can be transmitted to the reference node PD.

At the stage t3, as shown in fig. 12, the clock signal terminal CLK and the reset terminal Rst continue to provide a low level, the input terminal STV provides a high level, the first transistor M1 is turned on, the first voltage (e.g., the high level Ua) input by the first voltage terminal VDS can be input to the pull-up node PU, then the first control terminal S1 provides a high level, the second control terminal S2 provides a low level, the third transistor M3 is turned on, the fourth transistor is turned off, and thus the pull-up node PU and the reference node PD are turned on. When the reference voltage at the reference node is equal to the first voltage at the pull-up node PU, no current flows, and the pull-up node PU maintains the first voltage. When the reference voltage at the reference node is greater than the first voltage at the pull-up node PU, the current flows, the pull-up node PU may continue to rise, and the voltage of the reference node PD may supplement the voltage of the pull-up node PU.

At the stage t4, as shown in fig. 13, the input terminal STV, the reset terminal Rst, the first control terminal S1 and the second control terminal S2 provide a low level, and the voltage at the pull-up node PU is pulled up to a high level Ua at the stage t3, at this time, the second transistor M2 is turned on, the clock signal provided by the clock signal terminal CLK is transmitted to the output terminal GOUT for output, and meanwhile, the voltage at the second pole rises due to the transmission of the clock signal to the second pole of the first capacitor C1, and the voltage at the first pole of the first capacitor C1 continues to rise according to the capacitive coupling principle. Since the first control terminal S1 still provides the high level, the third transistor M3 is turned on, and the clock signal is also transmitted to the second pole of the second capacitor C2, the first capacitor C1 is connected in parallel with the second capacitor C2, and the capacitance is larger, so that the first capacitor C1 and the second capacitor C2 can cooperate to boost the voltages at the pull-up node PU and the reference node PD to the intermediate voltage (e.g., the high level Ub, Ub > Ua) according to the capacitive coupling principle.

In addition, it should be understood that the third control terminal S3 may continuously provide the reference voltage during the t3 and t4 stages in order to prevent the leakage of the third transistor M3 and the fourth transistor M4 from affecting the voltage at the pull-up node PU.

Based on this, the voltage at the pull-up node PD is raised to the intermediate voltage, the voltage at the pull-up node PU is hard to be pulled down again even if the fifth transistor leaks electricity, and the effective duration of the output terminal GOUT outputting the high level becomes long.

At the stage t5, as shown in fig. 14, the input terminal STV, the first control terminal S1, the second control terminal S2 and the third control terminal S3 provide a low level, the reset terminal Rst provides a high level, the fifth transistor M5 is turned on, the second voltage (low level) transmitted by the second voltage terminal VGL can be transmitted to the pull-up node PU to reset the pull-up node PU, meanwhile, the sixth transistor M6 is turned on, the second voltage (low level) transmitted by the second voltage terminal VGL can be transmitted to the output GOUT to reset the output GOUT.

The embodiment of the present invention further provides a gate driving circuit, as shown in fig. 2, including a plurality of cascaded shift register units 20 according to the embodiment of the present invention.

The output terminal GOUT of the first stage shift register unit 20 is electrically connected to the input terminal STV of the second stage shift register unit 20.

The output terminal of the last stage shift register unit 20 is electrically connected to the reset terminal Rst of the previous stage shift register unit 20.

Except for the first stage shift register unit 20 and the last stage shift register unit 20, the output terminal GOUT of each of the other shift register units 20 is electrically connected to the reset terminal Rst of the previous stage shift register unit 20 and the input terminal STV of the next stage shift register unit 20.

The gate driving circuit provided by the embodiment of the utility model has the same beneficial effects as the shift register unit provided by the embodiment of the utility model, and the details are not repeated herein.

The embodiment of the utility model also provides a display panel, which comprises the gate driving circuit.

The display panel provided by the embodiment of the utility model has the same beneficial effects as the shift register unit provided by the embodiment of the utility model, and the description is omitted.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. A shift register cell, comprising: the circuit comprises an auxiliary control sub-circuit, an input sub-circuit, a control sub-circuit, an input end, an output end, a clock signal end, a first voltage end, a first control end and a pull-up node;

2. The shift register cell of claim 1, further comprising a reset subcircuit, a reset terminal, and a second voltage terminal;

the reset sub-circuit is electrically connected with the reset end, the second voltage end, the pull-up node and the output end, and the reset sub-circuit is used for transmitting the second voltage provided by the second voltage end to the pull-up node and the output end under the control of the reset voltage provided by the reset end, and resetting the pull-up node and the output end.

3. The shift register cell of claim 1, wherein the input sub-circuit comprises a first transistor, a gate of the first transistor is electrically connected to the input terminal, a first electrode of the first transistor is electrically connected to the first voltage terminal, and a second electrode of the first transistor is electrically connected to the pull-up node.

4. The shift register cell of claim 1, wherein the control subcircuit includes a second transistor and a first capacitance;

the grid electrode of the second transistor and the first electrode of the first capacitor are electrically connected with the pull-up node, the first electrode of the second transistor is electrically connected with the clock signal end, and the second electrode of the second transistor and the second electrode of the first capacitor are electrically connected with the output end.

5. The shift register cell of claim 1, further comprising a second control terminal and a third control terminal;

the auxiliary control sub-circuit is further electrically connected with the second control terminal and the third control terminal, and the auxiliary control sub-circuit is configured to transmit the reference voltage provided by the third control terminal to the reference node under the control of the second control voltage provided by the second control terminal.

6. The shift register cell of claim 5, wherein the auxiliary control subcircuit includes a third transistor, a fourth transistor, and a second capacitor;

a gate of the third transistor is electrically connected to the first control terminal, a first electrode of the third transistor is electrically connected to the pull-up node, and a second electrode of the third transistor is electrically connected to the reference node;

a gate of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the third control terminal, and a second electrode of the fourth transistor is electrically connected to the reference node;

the first pole of the second capacitor is electrically connected to the reference node, and the second pole of the second capacitor is electrically connected to the output terminal.

7. The shift register cell of claim 5 or 6, wherein the third control terminal is electrically connected to the first voltage terminal.

8. The shift register cell of claim 2, wherein the reset subcircuit includes a fifth transistor and a sixth transistor;

a gate of the fifth transistor is electrically connected to the reset terminal, a first electrode of the fifth transistor is electrically connected to the pull-up node, and a second electrode of the fifth transistor is electrically connected to the second voltage terminal;

the grid electrode of the sixth transistor is electrically connected with the reset end, the first electrode of the sixth transistor is electrically connected with the output end, and the second electrode of the sixth transistor is electrically connected with the second voltage end.

9. A gate drive circuit comprising a plurality of cascaded shift register cells according to any one of claims 1 to 8;

the output end of the first-stage shift register unit is electrically connected with the input end of the second-stage shift register unit;

the output end of the last stage of shift register unit is electrically connected with the reset end of the previous stage of shift register unit;

except the first stage shift register unit and the last stage shift register unit, the output end of each shift register unit is electrically connected with the reset end of the previous stage shift register unit and the input end of the next stage shift register unit.

10. A display panel comprising the gate driver circuit as claimed in claim 9.