CN215526658U

CN215526658U - Circuit for switching debugging port and operation and maintenance serial port of device

Info

Publication number: CN215526658U
Application number: CN202120530883.2U
Authority: CN
Inventors: 王润路; 高超; 庄凯凯; 蔡菠; 孙颂林; 李响
Original assignee: NR Electric Co Ltd; NR Engineering Co Ltd
Current assignee: NR Electric Co Ltd; NR Engineering Co Ltd
Priority date: 2021-03-12
Filing date: 2021-03-12
Publication date: 2022-01-14
Anticipated expiration: 2031-03-12

Abstract

The utility model discloses a circuit for switching a debugging port and an operation and maintenance serial port of a device, which comprises a hardware circuit of the debugging port and the operation and maintenance serial port and a hardware circuit for controlling the switching function of the port; by concentrating the debugging port and the operation and maintenance serial port on the same physical port of the device panel, the device can be debugged by using the debugging port, and the operation and maintenance serial port and the device can be used for communication. The utility model can save the panel space of the device, efficiently utilize port resources and consider the normal use of the device by a user and the debugging device of maintenance personnel.

Description

Circuit for switching debugging port and operation and maintenance serial port of device

Technical Field

The utility model belongs to the field of communication, and particularly relates to a circuit for switching a device debugging port and an operation and maintenance serial port.

Background

The communication device supports the access of an operation and maintenance serial port of a user, is usually in an RJ45 port form, different manufacturers have different definitions of an RJ45 port PIN foot, and meanwhile, the device needs to be provided with a debugging port, is usually in an RJ45 port form, comprises a hundred-megabyte network port and a debugging serial port, and is used for debugging and using when the device is abnormal.

The common practice is to design two RJ45 ports, one is an operation and maintenance serial port, and the other is a debugging port. This takes up a large amount of the device panel space, especially when the device is small in size. Considering that the debugging port is not used in most cases when the device is working normally, the design is a waste of hardware resources to a certain extent.

SUMMERY OF THE UTILITY MODEL

Utility model purpose: the utility model aims to provide a circuit for switching a device debugging port and an operation and maintenance serial port, which integrates the debugging port and the operation and maintenance serial port into the same maintenance port and can save panel space.

The technical scheme is as follows: the utility model includes debugging port and operation serial port hardware circuit, port switching function control hardware circuit; the debugging port and operation and maintenance serial port hardware circuit comprises a first integrated device U1 and two bus channels of a first integrated device U1, wherein a first channel L1 and a second channel L1 are respectively connected with a first contact K1 and a second contact K2 of a fourth discrete device F4, and the fourth discrete device F4 is connected with a third discrete device F3 through a third channel L3; the port switching function control hardware circuit comprises a first integrated device U1, wherein one output pin of the first integrated device U1 is connected with the base electrode of a fifth discrete device F5, and the collector electrode of the fifth discrete device F5 is respectively connected with one end of a sixth discrete device F6 and the gate electrode of a seventh discrete device F7; the other end of the sixth discrete device F6 and the source of the seventh discrete device F7 are both connected to the positive electrode of a first voltage V1; the drain electrode of the seventh discrete device F7 is respectively connected with the anode electrode of the fourth discrete device F4 and the input end of the second integrated device U2; the negative electrode of the first voltage V1 is connected with the positive electrode of the fourth discrete device F4.

The port switching function control hardware circuit further comprises a first discrete device F1, one end of the first discrete device F1 is connected with a common input pin of the first integrated device U1 and one end of an eighth discrete device F8, and the other end of the eighth discrete device F8 is connected with a fifth voltage V5.

The first discrete device F1 adopts a press non-self-locking microswitch to switch ports.

The output end of the second integrated device U2 is respectively connected with one input pin of the first integrated device U1 and the anode of the second discrete device F2.

The second discrete device F2 adopts an indicator light, and can reflect the functional status of the port.

The fourth discrete device F4 is a relay, and the relay adopts a single-pole double-throw contact and a plurality of groups of contacts which act simultaneously.

The fifth discrete device F5 is an NPN triode.

Has the advantages that: compared with the prior art, the utility model has the beneficial effects that: the debugging port and the operation and maintenance serial port are integrated into one physical port, and one port realizes two functions, so that the panel interface resource of the device is saved, the size of the device is reduced, and the appearance design of the device is simplified.

Drawings

Fig. 1 is a circuit diagram of the present invention.

Detailed Description

The utility model is described in further detail below with reference to specific embodiments and the attached drawings.

As shown in fig. 1, the present invention includes two parts, namely a debugging port, an operation and maintenance serial port hardware circuit, and a port switching function control hardware circuit. The debugging port and the operation and maintenance serial port hardware circuit comprise a first integrated device U1, a first channel L1, a second channel L2, a third channel L3, a third discrete device F3 and a fourth discrete device F4. Two bus channels, a first channel L1 and a second channel L2, of the first integrated device U1 are connected to a first contact K1 and a second contact K2 of a fourth discrete device F4, respectively, and the fourth discrete device F4 is connected to the third discrete device F3 through a third channel L3. Specifically, the first integrated device U1 employs a central processing unit CPU; the third discrete device F3 is an RJ45 maintenance port; the fourth discrete device F4 is a relay; in this embodiment, the relay employs a single-pole double-throw, multi-group of contacts that operate simultaneously. The first channel L1 is a debugging network port and a serial port; the second channel L2 is an operation and maintenance serial port; the third channel L3 maintains port signals for RJ 45.

The port switching function control hardware circuit comprises a first integrated device U1, a second integrated device U2, a first discrete device F1, a second discrete device F2, a fifth discrete device F5, a sixth discrete device F6, a seventh discrete device F7, an eighth discrete device F8, a first voltage V1, a second voltage V2, a third voltage V3, a fourth voltage V4, a fifth voltage V5 and a sixth voltage V6. Specifically, the second integrated device U2 employs an inverter; the first discrete device F1 is a key, and in this embodiment, a non-self-locking microswitch is pressed; the second discrete device F2 adopts an indicator light; the fifth discrete device F5 adopts an NPN triode; the sixth discrete device F6 is a resistor; the seventh discrete device F7 employs a PMOS transistor; the eighth discrete device F8 is a resistor. One end of the first discrete device F1 is connected to a common input pin of the first integrated device U1 and one end of the eighth discrete device F8, respectively, and the other end of the eighth discrete device F8 is connected to the fifth voltage V5. An output pin of the first integrated device U1 is connected to the base of the fifth discrete device F5, the emitter is grounded, and the collector of the fifth discrete device F5 is connected to one end of the sixth discrete device F6 and the gate of the seventh discrete device F7. The other end of the sixth discrete device F6 and the source of the seventh discrete device F7 are both connected to the positive electrode of the first voltage V1; the drain of the seventh discrete device F7 is connected to the anode of the fourth discrete device F4 and the input of the second integrated device U2, respectively. The negative pole of the first voltage V1 is connected with the positive pole of the fourth discrete device F4. The output end of the second integrated device U2 is respectively connected with one input pin of the first integrated device U1 and the anode of the second discrete device F2, and the cathode of the second discrete device F2 is grounded.

The debugging network port, the debugging serial port and the operation and maintenance serial port are all led out from the CPU, the debugging network port of the first channel L1 is a hundred million network port, and the total number of the debugging network port is 4 signal lines; the debugging serial port consists of TX, RX and GND (two), and the total number of the debugging serial port is 4 signal lines; the operation and maintenance serial port of the second channel L2 consists of TX, RX, and GND (two), for a total of 4 signal lines. The first channel L1 is connected to a first contact K1 of the relay, the second channel L2 is connected to a second contact K2 of the relay, the default relay power supply is not electrified, the first contact K1 is closed, namely the RJ45 maintenance port is a debugging port function by default, and after the CPU controls the relay power supply to be electrified, the second contact K2 is closed, namely the RJ45 maintenance port is an operation and maintenance serial port function. The relay is a single-pole double-throw contact, and 8 groups of contacts with the same action are needed for simultaneous switching because the debugging port has 8 signal lines.

One end of the key is grounded, the other end of the key is pulled up to a fifth voltage V5 through the resistor, and a negative pulse is generated when the key is pressed because the key is a non-self-locking microswitch, and the negative pulse is sent to the CPU. The CPU receives a pulse to change the high and low levels of the sixth voltage V6 on the relay control pin once.

When the sixth voltage V6 is at low level, the NPN transistor is turned off, and the second voltage V2 is pulled up through the resistor to the second voltage V2 and remains at high level. The grid electrode and the source electrode of the PMOS transistor are both first voltage V1, Vgs is 0, the PMOS transistor is cut off, third voltage V3 is low level, the relay is not powered, and the relay is closed to the first contact point K1. The third voltage V3 is low, the output of the inverter is high, the fourth voltage V4 is high, the indicator lights, and the CPU reads the high signal of the fourth voltage V4. Therefore, when the RJ45 maintenance port is in the debugging port state, the indicator light is lightened, and the CPU reads back to the high level state.

When the sixth voltage V6 is at a high level, the NPN transistor is turned on, and the second voltage V2 is at a low level. And the voltage difference | Vgs | > | Vgs (th) | of the grid electrode and the source electrode of the PMOS transistor, the PMOS transistor is conducted, the third voltage V3 is high level, the power supply of the relay is normal, and the relay is closed to the second contact point K2. The third voltage V3 is high, the output of the inverter is fourth voltage V4 is low, the indicator light is off, and the CPU reads the low signal of the fourth voltage V4. Therefore, when the maintenance port of the RJ45 is in the serial port maintenance state, the indicator light is turned off, and the CPU reads back to the low level state.

The whole work flow of switching between the device debugging port and the operation and maintenance serial port is triggered by key pulse, the CPU controls the relay to switch and close the first contact K1 and the second contact K2, so that the RJ45 communicates on the corresponding functional port, the indicator light represents the functional state of the port, and the CPU reads back the corresponding level state.

The utility model can debug the equipment by using the debugging port on the same physical port of the device panel, and can also communicate with the equipment by using the operation and maintenance serial port, wherein the debugging port consists of a hundred million network port and a debugging serial port. The switching between the two functional ports is controlled by an entity key, and the indicator light of the panel can reflect whether the port is in a debugging port state or an operation and maintenance serial port state.

Claims

1. The utility model provides a circuit that device debugging mouth and operation and maintenance serial ports switch which characterized in that: the debugging port and the operation and maintenance serial port hardware circuit and the port switching function control hardware circuit are included;

the debugging port and operation and maintenance serial port hardware circuit comprises a first integrated device U1 and two bus channels of a first integrated device U1, wherein a first channel L1 and a second channel L1 are respectively connected with a first contact K1 and a second contact K2 of a fourth discrete device F4, and the fourth discrete device F4 is connected with a third discrete device F3 through a third channel L3;

the port switching function control hardware circuit comprises a first integrated device U1, wherein one output pin of the first integrated device U1 is connected with the base electrode of a fifth discrete device F5, and the collector electrode of the fifth discrete device F5 is respectively connected with one end of a sixth discrete device F6 and the gate electrode of a seventh discrete device F7; the other end of the sixth discrete device F6 and the source of the seventh discrete device F7 are both connected to the positive electrode of a first voltage V1; the drain electrode of the seventh discrete device F7 is respectively connected with the anode electrode of the fourth discrete device F4 and the input end of the second integrated device U2; the negative electrode of the first voltage V1 is connected with the positive electrode of the fourth discrete device F4.

2. The device of claim 1, wherein the device comprises a debugging port and an operation and maintenance serial port, and the device comprises: the port switching function control hardware circuit further comprises a first discrete device F1, one end of the first discrete device F1 is connected with a common input pin of the first integrated device U1 and one end of an eighth discrete device F8, and the other end of the eighth discrete device F8 is connected with a fifth voltage V5.

3. The device of claim 2, wherein the device comprises a debugging port and an operation and maintenance serial port, and the device comprises: the first discrete device F1 employs a push-on non-self-locking microswitch.

4. The device of claim 1, wherein the device comprises a debugging port and an operation and maintenance serial port, and the device comprises: the output end of the second integrated device U2 is respectively connected with one input pin of the first integrated device U1 and the anode of the second discrete device F2.

5. The device of claim 4, wherein the device comprises a debugging port and an operation and maintenance serial port, and the device comprises: the second discrete device F2 employs an indicator light.

6. The device of claim 1, wherein the device comprises a debugging port and an operation and maintenance serial port, and the device comprises: the fourth discrete device F4 is a relay, and the relay adopts a single-pole double-throw contact and a plurality of groups of contacts which act simultaneously.

7. The device of claim 1, wherein the device comprises a debugging port and an operation and maintenance serial port, and the device comprises: the fifth discrete device F5 is an NPN triode.

8. The device of claim 1, wherein the device comprises a debugging port and an operation and maintenance serial port, and the device comprises: the seventh discrete device F7 employs PMOS transistors.