CN215499299U

CN215499299U - System for image processing enhancement

Info

Publication number: CN215499299U
Application number: CN202121336636.5U
Authority: CN
Inventors: 禹春来; 李小亮; 李文方; 张具琴; 栗红霞; 王新月
Original assignee: Huanghe Science and Technology College
Current assignee: Huanghe Science and Technology College
Priority date: 2021-06-16
Filing date: 2021-06-16
Publication date: 2022-01-11
Anticipated expiration: 2031-06-16

Abstract

The utility model is used for the system that the image processing enhances, the image de-noising circuit uses the high resistance to receive the image signal that the image acquisition circuit detects, one end of the image signal is outputted after the primary amplification, frequency selection circuit frequency selection, another end of the image signal is after detecting the static electricity, buffering, one is discharged through the resistance R15, another is added to the base of the triode Q2, when the static electricity is high, one end of the image signal is outputted after frequency selection + noise discharge, thus realize the noise reduction processing, then enter the image enhancement circuit, use the differential amplifier to amplify, balance the amplitude modulation, enter DSP after the smooth filtering, and connect the grid of the field effect tube T2 through the resistance R14, the double diode VD1, change the input resistance of the operational amplifier AR2, namely realize the effect of feedback amplitude modulation, in order to meet the requirement of DSP input voltage range, so as to enhance the processing, relatively conventional processing, help to guarantee the integrality of the signal, the problem of losing image signals is avoided.

Description

System for image processing enhancement

Technical Field

The utility model belongs to the technical field of image processing, and particularly relates to a system for enhancing image processing.

Background

The prior art is as follows: the system for image processing enhancement with the patent application number of 201620033717.0 collects images through an image collecting circuit and enters a DSP (digital signal processor), and the DSP adopts an embedded processor to carry out image enhancement, noise elimination, edge enhancement and other processing, so that the image processing efficiency and effect are effectively improved.

However, in the process of outputting the image signal to the DSP by the image acquisition circuit, the image signal may be attenuated, and meanwhile, the image signal may be polluted by noise in the presence of various interference factors, and if the image signal is small, the image signal may be submerged.

Disclosure of Invention

Aiming at the situation and overcoming the defects of the prior art, the utility model provides a system for image processing enhancement, which adopts high-impedance receiving, primary amplification, frequency selection or noise release, amplification by a differential amplifier, balanced amplitude modulation, further feedback amplitude modulation and then enters a DSP processor to enhance and eliminate the noise of the image.

The image denoising circuit adopts a high-resistance receiving image signal detected by an image acquisition circuit and outputs the image signal after primary amplification, frequency selection or noise release, and the image enhancement circuit receives an output signal of the image denoising circuit, adopts a differential amplifier for amplification and balanced amplitude modulation, and further feeds back the amplitude modulation to enter a DSP (digital signal processor).

Furthermore, the image enhancement circuit comprises an operational amplifier AR2, the inverting input terminal of the operational amplifier AR2 is respectively connected with one end of a resistor R11 and one end of a resistor R12, the other end of the resistor R11 is connected with the output signal of the image denoising circuit, the non-inverting input terminal of the operational amplifier AR2 is respectively connected with one end of a resistor R6, one end of a capacitor C7 and the cathode of a diode D2 through a resistor R13, the other end of the capacitor C7 and the anode of a diode D2 are respectively connected with one end of the capacitor C8 and one end of an inductor L5, the output terminal of the operational amplifier AR2 is respectively connected with the other end of a resistor R12, one end of a capacitor C9 and the anode of a diode D1, the other end of a capacitor C9 and the cathode of a diode D1 are respectively connected with the other end of a capacitor C8, one end of an inductor L4 and one end of a resistor R14, the other end of an inductor L4 and the other end of an inductor L5 output signal are respectively output to the DSP processor, and the other end of the diode R14 is connected with the right end of a bidirectional diode VD1, the left end of the bidirectional diode VD1 is connected with the grid of a field effect transistor T1, the source of the field effect transistor T1 is connected with the anode of the diode D3, and the drain of the field effect transistor T1 and the cathode of the diode D3 are connected with the inverting input end of the operational amplifier AR 2.

The utility model has the beneficial effects that: the high resistance is adopted to receive an image signal detected by an image acquisition circuit, one end of the image signal is output after primary amplification and frequency selection by a frequency selection circuit, the other end of the image signal is output after static electricity detection and buffering, one path of the image signal is discharged through a resistor R15, the other path of the image signal is added to a base electrode of a triode Q2, when the static electricity is high, the triode Q2 is conducted, one end of the image signal is output after frequency selection and noise leakage, noise reduction processing is realized, then the image signal enters a DSP after amplification by a differential amplifier, balanced amplitude modulation and smooth filtering by a balancing circuit, the DSP is connected through a resistor R14 and a double diode VD1 to a grid electrode of a field effect tube T2, the input resistance of an operational amplifier AR2 is changed, the effect of feedback amplitude modulation is also realized, the requirement of the DSP input voltage range is met, and the enhancement processing is relatively convenient to ensure the integrity of the signal and avoid the problem of image signal loss.

Drawings

Fig. 1 is a schematic diagram of the circuit of the present invention.

Detailed Description

The technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.

The following description will explain embodiments of the present invention in further detail with reference to fig. 1 of the specification.

The system for image processing enhancement comprises an image denoising circuit and an image enhancement circuit, wherein the image denoising circuit adopts a high resistance to receive an image signal detected by an image acquisition circuit, one end (positive pole) of the image signal is subjected to primary amplification, one end of the image signal is subjected to frequency selection and output through a frequency selection circuit consisting of a capacitor C5, a resistor R9, a capacitor C6 and a resistor R10, the other end (negative pole) of the image signal is subjected to static electricity detection through a resistor R6 and a capacitor C4 which are connected in parallel, one path of the image signal is discharged through a resistor R15 after being buffered by an operational amplifier AR1, the other path of the image signal is added to a base electrode of a triode Q2, when the static electricity is high, the triode Q2 is conducted, one end of the image signal is subjected to frequency selection and noise discharge and output, so that the noise reduction is realized, then the image enhancement circuit enters the image enhancement circuit, the differential amplifier AR2 and the differential amplifier consisting of the resistor R11-resistor R13 are adopted for amplification, a diode D1 and a capacitor C9, a resistor R13 are connected in parallel, A balancing circuit composed of a diode D2 and a capacitor C7 balances amplitude modulation, the capacitor C8, the inductor L4 and the inductor L5 enter the DSP after smooth filtering, and are further fed back to a double diode VD1 through a resistor R14, the double diode VD1 is connected with the grid of a field effect tube T2, the drain electrode of the field effect tube T2 is connected with the inverting input end of an operational amplifier AR2, the input resistance of the operational amplifier AR2 is changed, namely, the effect of feedback amplitude modulation is realized, so that the requirement of the DSP input voltage range is met, and therefore, the enhancement processing is realized.

In the above technical solution, the image denoising circuit receives an image signal detected by an image acquisition circuit by using a high resistance receiving circuit composed of a fet T1, a resistor R1-a resistor R3, a capacitor C1, a capacitor C2, and a capacitor C9, one end (positive electrode) of the image signal is then applied to an amplifying circuit composed of a transistor Q1, a resistor R4, a resistor R5, and a resistor R7 through a capacitor C1 for primary amplification, frequency-selected by a frequency-selecting circuit composed of a capacitor C5, a resistor R9, a capacitor C6, and a resistor R10 and then output, the other end (negative electrode) of the image signal is detected by a resistor R6 and a capacitor C4 connected in parallel, one path is discharged after buffering by an operational amplifier AR1, the other path is applied to a base of a transistor Q2, when the static electricity is high, the transistor Q2 is turned on, the frequency-selected + the discharged noise is output, thereby realizing noise reduction processing, including a capacitor C1, a capacitor C9, one end of the capacitor C1, and one end of the image signal connected to the image detection circuit of the capacitor C9, the other end of the capacitor C1 is connected to one end of a resistor R1 and the gate of a field effect transistor T1, the drain of the field effect transistor T1 is connected to one end of a grounded capacitor C2 and one end of a resistor R3, the other end of the resistor R3 is connected to +5V, the source of the field effect transistor T1 is connected to one end of a resistor R2 and one end of a capacitor C3, the other end of the resistor R2 is connected to the other end of a capacitor C9, the other end of the resistor R1, one end of a resistor R6 and one end of a capacitor C4, the other end of the resistor R6 and the other end of the capacitor C4 are connected to the non-inverting input end of an operational amplifier AR1, the inverting input end and the output end of an operational amplifier AR1 are connected to one end of a resistor R8, the other end of the resistor R8 is connected to the base of a transistor Q2 and one end of a resistor R15, the emitter of the transistor Q2 and the other end of the resistor R15 are connected to ground, the other end of the capacitor C3 is connected to one end of a resistor R4 and one end of a resistor R5, The image denoising circuit comprises a base electrode of a triode Q1, an emitter electrode of a triode Q1 is respectively connected with one end of a grounding resistor R7 and one end of a capacitor C5, the other end of a resistor R4 and a collector electrode of a triode Q1 are connected with +5V of a power supply, the other end of a capacitor C5 is connected with one end of a resistor R9, the other end of a resistor R9 is respectively connected with a collector electrode of a triode Q2, one end of the grounding resistor R10 and one end of a grounding capacitor C6, and a collector electrode of the triode Q2 is used as an image denoising circuit output signal.

In the above technical solution, the image enhancement circuit receives the output signal of the image denoising circuit, and adopts a differential amplifier composed of an operational amplifier AR2, a resistor R11-a resistor R13 to amplify, a balanced circuit composed of a diode D1, a capacitor C9, a diode D2 and a capacitor C7 connected in parallel to balance amplitude modulation, a capacitor C8, an inductor L4 and an inductor L5 to smooth and filter, and further feed back to a double diode VD1 through a resistor R14, the double diode VD1 is connected to the gate of a field effect transistor T2, the drain of the field effect transistor T2 is connected to the inverting input terminal of the operational amplifier AR2 to change the input resistance of the operational amplifier AR2, that is, to realize the feedback amplitude modulation effect, so as to meet the requirement of the DSP input voltage range (for example, the core voltage of the DSP28377D chip is 1.2V, the I/O port is 3.3V, the allowed voltage is-3.3V-3.6V), the problem of losing image signals is avoided, comprising an operational amplifier AR2, the inverting input end of the operational amplifier AR2 is respectively connected with one end of a resistor R11 and one end of a resistor R12, the other end of a resistor R11 is connected with an image denoising circuit output signal, the non-inverting input end of the operational amplifier AR2 is respectively connected with one end of a resistor R6, one end of a capacitor C7 and the cathode of a diode D2 through a resistor R13, the other end of a capacitor C7 and the anode of a diode D2 are respectively connected with one end of a capacitor C8 and one end of an inductor L5, the output end of the operational amplifier AR2 is respectively connected with the other end of a resistor R12, one end of a capacitor C9 and the anode of a diode D1, the other end of a capacitor C9 and the cathode of a diode D1 are respectively connected with the other end of a capacitor C8, one end of an inductor L4 and one end of a resistor R14, the other end of an inductor L4 and the other end of an inductor L5 output signal is connected to a DSP processor, the other end of the capacitor R14 is connected with the right end of a bidirectional VD1, the left end of the bidirectional diode VD1 is connected with the grid of a field effect transistor T2, the source of the field effect transistor T2 is connected with the anode of the diode D3, and the drain of the field effect transistor T2 and the cathode of the diode D3 are connected with the inverting input end of the operational amplifier AR 2.

When the utility model is used in concrete, the image de-noising circuit adopts high resistance to receive the image signal detected by the image acquisition circuit, one end (positive pole) of the image signal is output after being subjected to primary amplification and frequency selection by the frequency selection circuit, the other end (negative pole) of the image signal is subjected to static electricity detection, one path of the image signal is discharged through the resistor R15 after being buffered by the operational amplifier AR1, the other path of the image signal is added to the base electrode of the triode Q2, when the static electricity is high, the triode Q2 is conducted, one end of the image signal is output after frequency selection and noise discharge, so that noise reduction is realized, then the image signal enters the image enhancement circuit, differential amplifier amplification and balance circuit are adopted to balance amplitude modulation, the capacitor C8, the inductor L4 and the inductor L5 are smoothly filtered and then enter the DSP, the VD is connected with the grid of the field effect transistor T2 through the resistor R14 and the double diode 1, the drain of the field effect transistor T2 is connected with the inverting input end of the operational amplifier AR2, so as to change the input resistance of the operational amplifier AR2, the feedback amplitude modulation effect is realized to meet the requirement of the DSP input voltage range, so that the processing is enhanced, the integrity of signals can be ensured compared with the conventional clamping processing, and the problem of image signal loss is avoided.

Claims

1. The system for image processing enhancement comprises an image denoising circuit and an image enhancement circuit, and is characterized in that the image denoising circuit receives an image signal detected by an image acquisition circuit by adopting a high resistance and outputs the image signal after primary amplification, frequency selection or noise release, the image enhancement circuit receives an output signal of the image denoising circuit, amplifies the signal by adopting a differential amplifier, balances amplitude modulation, and further feeds back the amplitude modulation before entering a DSP (digital signal processor).

2. The system according to claim 1, wherein the image de-noising circuit comprises a capacitor C1 and a capacitor C9, one end of the capacitor C1 and one end of the capacitor C9 are connected to the image signal detected by the image acquisition circuit, the other end of the capacitor C1 is connected to one end of a resistor R1 and the gate of a FET T1, the drain of the FET T1 is connected to one end of a grounded capacitor C2 and one end of a resistor R3, the other end of the resistor R3 is connected to +5V, the source of the FET T1 is connected to one end of a resistor R2 and one end of a capacitor C3, the other end of the resistor R2 is connected to the other end of a capacitor C9, the other end of a resistor R1, one end of a resistor R6 and one end of a capacitor C4, the other end of a resistor R6 AR and the other end of a capacitor C4 are connected to the non-inverting input terminal of an operational amplifier AR1, the input terminal and the output terminal of the inverting input terminal of the operational amplifier 1 are connected to one end of the resistor R8, the other end of the resistor R8 is connected with the base of the triode Q2 and one end of the resistor R15, the emitter of the triode Q2 and the other end of the resistor R15 are connected with the ground, the other end of the capacitor C3 is respectively connected with one end of the resistor R4, one end of the ground resistor R5 and the base of the triode Q1, the emitter of the triode Q1 is respectively connected with one end of the ground resistor R7 and one end of the capacitor C5, the other end of the resistor R4 and the collector of the triode Q1 are connected with +5V, the other end of the capacitor C5 is connected with one end of the resistor R9, the other end of the resistor R9 is respectively connected with the collector of the triode Q2, one end of the ground resistor R10 and one end of the ground capacitor C6, and the collector of the triode Q2 is used as an image denoising circuit output signal.

3. The system of claim 1, wherein the image enhancement circuit comprises an operational amplifier AR2, the inverting input terminal of the operational amplifier AR2 is connected to one terminal of a resistor R11 and one terminal of a resistor R12 respectively, the other terminal of the resistor R11 is connected to the output signal of the image de-noising circuit, the non-inverting input terminal of the operational amplifier AR2 is connected to one terminal of a resistor R6, one terminal of a capacitor C7 and the cathode of a diode D2 respectively through a resistor R13, the other terminal of the capacitor C7 and the anode of a diode D2 are connected to one terminal of a capacitor C8 and one terminal of an inductor L5 respectively, the output terminal of the operational amplifier AR2 is connected to the other terminal of a resistor R12, one terminal of a capacitor C9 and the anode of a diode D1 respectively, the other terminal of a capacitor C9 and the cathode of a diode D1 are connected to the other terminal of a capacitor C8, one terminal of an inductor L4 and one terminal of a resistor R14, the other terminal of an L4 and the other terminal of the inductor L5 output signal to the DSP, the other end of the capacitor R14 is connected with the right end of a bidirectional diode VD1, the left end of the bidirectional diode VD1 is connected with the grid of a field effect tube T1, the source of the field effect tube T1 is connected with the anode of a diode D3, and the drain of the field effect tube T1 and the cathode of the diode D3 are connected with the inverting input end of the operational amplifier AR 2.