CN215498275U - Chip structure and KNX bus power supply circuit - Google Patents

Abstract

The embodiment of the utility model discloses a chip and a KNX bus power supply circuit. The chip comprises a circuit board, a choke coil and a switch circuit, wherein the circuit board comprises a first face and a second face which are opposite, the choke coil is arranged on the first face, the choke coil is provided with an input end and an output end, the input end is used for being electrically connected with a power supply, the output end is used for outputting current, the switch circuit is arranged on the second face, and the switch circuit is electrically connected between the input end and the power supply. The choke coil is arranged on the circuit board, so that the direct current output by the KNX bus power circuit is ensured, meanwhile, the choke coil is used for blocking a communication signal from entering a power supply, and the power supply is prevented from generating interference on the communication signal. The choke coil and the switch circuit are respectively arranged on the first surface and the second surface of the circuit board, so that the whole structure of the chip is more compact, and the miniaturization design of the chip can be realized.

Description

Chip structure and KNX bus power supply circuit

Technical Field

The utility model relates to the technical field of integrated circuits, in particular to a chip and a KNX bus power supply circuit.

Background

KNX (Konnex) is an open international standard in the field of home and building control and developed by the combination of European three bus protocols EIB, BatiBus and EHS. By means of the KNX system, lighting, shading/blinds, security systems, energy management, heating, ventilation, air conditioning systems, signal and monitoring systems, service interfaces and building control systems, remote control, metering, video/audio control, large appliances, etc. of homes and buildings can be controlled.

In a KNX system, an electrical connection between a power supply and each device is usually realized through a KNX bus, so as to realize communication signal transmission between each device and enable the power supply to supply power to each device. In the related art, a filter capacitor is often disposed at an output terminal of a power supply to reduce an ac ripple coefficient, thereby smoothing an output dc current and achieving better power supply. However, when each device transmits a communication signal, the communication signal is transmitted to the filter capacitor through the KNX bus, and the communication signal is changed due to interference of the filter capacitor. The changed communication signals can be transmitted to each device through the KNX bus, so that the communication accuracy between the devices is influenced, and the use is influenced.

In order to solve the above problem, a choke circuit is generally provided between the filter capacitor and the device. However, since the choke coil circuit in the related art is complex and includes many electronic components, the choke coil circuit is usually configured by using a circuit board with a large area for layout design, which results in a large overall volume of the KNX system.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model discloses a chip and a KNX bus power supply circuit, wherein the chip can adopt a circuit board with a smaller area, and the layout of electronic components on the circuit board is more compact, so that the overall size of the chip is smaller.

In order to achieve the above object, in a first aspect, the present invention discloses a chip applied to a KNX bus power supply circuit having a power supply, the chip including:

the circuit board comprises a first surface and a second surface which are opposite;

a choke disposed on the first face, the choke having an input end for electrical connection with the power source and an output end for outputting a current; and the number of the first and second groups,

the switch circuit is arranged on the second surface and is electrically connected between the input end and the power supply, and the switch circuit is used for controlling the on-off of a circuit between the input end and the power supply.

As an optional implementation manner, in an embodiment of the first aspect of the present invention, the chip further includes a signal optimization circuit, the signal optimization circuit is disposed on the circuit board, one end of the signal optimization circuit is electrically connected to the input end, the other end of the signal optimization circuit is electrically connected to the output end, and the signal optimization circuit is configured to adjust a limit of an amplitude of the communication signal flowing through the output end.

As an optional implementation manner, in an embodiment of the first aspect of the present invention, the input terminal includes a first input terminal and a second input terminal, the first input terminal is configured to be electrically connected to a positive pole of the power supply, and the second input terminal is configured to be electrically connected to a negative pole of the power supply;

the output end comprises a first output end and a second output end, the first output end is used for outputting positive voltage current, and the second output end is used for outputting negative voltage current;

the first input end is electrically connected with the first output end, the second input end is electrically connected with the second output end, the switch circuit is electrically connected between the second input end and the negative electrode of the power supply, and the switch circuit is used for controlling the circuit between the second input end and the negative electrode of the power supply to be switched on or switched off.

As an optional implementation manner, in an embodiment of the first aspect of the present invention, the chip further includes a signal optimization circuit, where the signal optimization circuit includes a first optimization circuit and a second optimization circuit, the first optimization circuit is electrically connected between the first input terminal and the first output terminal, the first optimization circuit is configured to adjust an upper limit of an amplitude of the communication signal flowing through the first output terminal, the second optimization circuit is electrically connected between the second input terminal and the second output terminal, and the second optimization circuit is configured to adjust a lower limit of an amplitude of the communication signal flowing through the second output terminal.

As an optional implementation manner, in an embodiment of the first aspect of the present invention, the first optimization circuit includes a first triode and a first zener diode, an emitter of the first triode is electrically connected to the first output terminal, a base of the first triode is electrically connected to the first input terminal, the first zener diode is electrically connected between a collector of the first triode and the first output terminal, the first triode is configured to be turned on when a voltage at the first output terminal is greater than a voltage at the first input terminal, and a voltage difference between the first output terminal and the first input terminal reaches a certain value, so as to control the first zener diode to be turned on, so as to reduce the voltage at the first output terminal;

the second optimization circuit comprises a second triode and a second voltage-stabilizing diode which are electrically connected, wherein an emitting electrode of the second triode is electrically connected with the second input end, a base electrode of the second triode is between the second output end, the second voltage-stabilizing diode is electrically connected between a collector electrode of the second triode and the second output end, the second triode is used for controlling the second voltage-stabilizing diode to be conducted when the voltage at the second output end is smaller than the voltage at the second input end, and the voltage difference between the second output end and the second input end reaches a certain value, so that the second voltage-stabilizing diode is controlled to be conducted, and the voltage output at the second output end is improved.

As an alternative implementation, in an embodiment of the first aspect of the present invention, the signal optimization circuit is at least partially disposed on the second side.

As an optional implementation manner, in an embodiment of the first aspect of the present invention, the switch circuit includes a third transistor and a field effect transistor, which are electrically connected to each other, the field effect transistor is electrically connected between the power supply and the input terminal, and the third transistor is configured to control the field effect transistor to switch between on and off, so as to turn on or off a circuit between the power supply and the input terminal.

As an optional implementation manner, in an embodiment of the first aspect of the present invention, the chip further includes a monitoring circuit, the monitoring circuit is disposed on the circuit board, and the monitoring circuit is configured to monitor circuit data between the power supply and the input terminal.

As an alternative implementation manner, in an embodiment of the first aspect of the present invention, the monitoring circuit includes a first resistor and a current detection amplifier, the first resistor is electrically connected between the power supply and the input terminal, the current detection amplifier is arranged in parallel with the first resistor, and the current detection amplifier is configured to detect a current flowing through the first resistor.

As an alternative implementation, in an embodiment of the first aspect of the present invention, the monitoring circuit is disposed on the second side.

In a second aspect, the utility model discloses a KNX bus power supply circuit, which comprises a power supply and the chip as described in the first aspect.

Compared with the prior art, the utility model has the beneficial effects that:

according to the chip and the KNX bus power supply circuit provided by the embodiment of the utility model, the circuit board is provided with the choke coil which is electrically connected between the output end of the KNX bus power supply circuit and the power supply, so that the KNX bus power supply circuit can output current at the output end and prevent a communication signal at the output end of the KNX bus power supply circuit from entering the power supply, the power supply is prevented from interfering the communication signal, the communication accuracy among equipment is improved, and the use experience of a user is improved. Meanwhile, the choke coil and the switch circuit are respectively arranged on the first surface and the second surface of the circuit board, so that the distribution of each electronic component included by the chip on the circuit board is more compact, and the miniaturization design of the chip can be realized.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a chip according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another angle structure of a chip according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a disclosed chip according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a second surface of the circuit board according to an embodiment of the disclosure.

Icon: 1. a chip; 10. a circuit board; 100. a first side; 101. a second face; 101a, a first region; 101b, a second region; 101c, a third area; 101d, a fourth region; 11. a choke coil; 110. an input end; 110a, a first input end; 110b, a second input terminal; 111. an output end; 111a, a first output end; 111b and a second output end; 12. a signal optimization circuit; 120. a first optimization circuit; q1, the first triode; d1, a first zener diode; 121. a second optimization circuit; q2, the second triode; d1, a second zener diode; 13. a switching circuit; q3, third triode; q4, field effect transistor; r12, pull-down resistor; 14. a monitoring circuit; r1, a first resistor; u1, a current sense amplifier; IC. A micro control unit; 2. a KNX bus power supply circuit; 20. a power source.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the present invention, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "center", "vertical", "horizontal", "lateral", "longitudinal", and the like indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These terms are used primarily to better describe the utility model and its embodiments and are not intended to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation.

Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meanings of these terms in the present invention can be understood by those skilled in the art as appropriate.

Furthermore, the terms "mounted," "disposed," "provided," "connected," and "connected" are to be construed broadly. For example, it may be a fixed connection, a removable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. The specific meanings of the above terms in the present invention can be understood by those of ordinary skill in the art according to specific situations.

Furthermore, the terms "first," "second," and the like, are used primarily to distinguish one device, element, or component from another (the specific nature and configuration may be the same or different), and are not used to indicate or imply the relative importance or number of the indicated devices, elements, or components. "plurality" means two or more unless otherwise specified.

The technical solution of the present invention will be further described with reference to the following embodiments and the accompanying drawings.

Example one

Referring to fig. 1 to 3, fig. 1 is a schematic view of a chip according to an embodiment of the present invention, fig. 2 is a schematic view of a chip according to another embodiment of the present invention, and fig. 1 is a circuit diagram of a chip according to an embodiment of the present invention. The embodiment one of the utility model discloses a chip, the chip 1 can be applied to a KNX bus power circuit 2, the KNX bus power circuit 2 is provided with a power supply 20, and when the KNX bus power circuit 2 is used for supplying power to a KNX system, the chip 1 can prevent a communication signal of equipment in the KNX system from entering the power supply 20 when the signal is transmitted. The chip 1 may include a circuit board 10, a choke 11 and a switch circuit 13, the circuit board 10 includes a first side 100 and a second side 101 opposite to each other, the choke 11 is disposed on the first side 100, the choke 11 has an input terminal 110 and an output terminal 111, the input terminal 110 is used for being electrically connected to a power supply 20, the output terminal 111 is used for being electrically connected to a device in the KNX system to output current to the device, so that the output terminal may be used for supplying power to the device in the KNX system, the switch circuit 13 is disposed on the second side 101, the switch circuit 13 is electrically connected between the input terminal 110 and the power supply 20, and the switch circuit 13 is used for controlling the circuit of the input terminal 110 and the power supply 20 to be turned on or off.

The chip 1 disclosed in this embodiment is provided with the choke 11 on the circuit board 10, and the power supply 20 outputs current through the choke 11, so that by using the characteristics of "direct current and alternating current resistance" of the choke 11, the direct current output by the power supply can be ensured to be normally output to supply power to the KNX system, and meanwhile, the communication signal of the device in the KNX system during signal transmission can be prevented from entering the power supply 20 through the output end, thereby avoiding the interference of the power supply 20 on the communication signal, and improving the accuracy of communication between the devices. Further, by providing the choke coil 11 and the switch circuit 13 on the first surface 100 and the second surface 101 of the circuit board 10, respectively, to utilize the space on the different surfaces of the circuit board 10, the circuit board 10 having a small area can be used, and the overall structure of the chip 1 is more compact, so that the chip 1 can be designed in a compact size.

Alternatively, the input terminal 110 and the output terminal 111 may both extend from the first side 100 through the circuit board 10 to at least partially be located on the second side 101, so as to be electrically connected to the switch circuit 13 located on the second side 101.

Referring to fig. 1 and fig. 2, in some embodiments, the input end 110 includes a first input end 110a and a second input end 110b, the output end 111 includes a first output end 111a and a second output end 111b, the first input end 110a is electrically connected to the positive pole of the power source 20, the first input end 110a is electrically connected to the first output end 111a, so that the first output end 111a can output a positive voltage current, the second input end 110b is electrically connected to the negative pole of the power source 20, the second output end 111b is used for outputting a negative voltage current, and the second input end 110b is electrically connected to the second output end 111b, so as to output a negative voltage current through the negative pole of the power source 20. Where GND in fig. 1 represents the negative pole of the power supply 20, and "output GND" represents the output of negative voltage current.

It can be understood that when the communication signal of the KNX system device is transmitted to the first output terminal 110a, the communication signal is blocked by the choke coil 11 and is not transmitted to the first input terminal 111a, so that the communication signal of the KNX system device cannot be transmitted to the power supply 20, and the power supply 20 can be prevented from interfering with the communication signal.

Specifically, the choke coil 11 may include a first coil, a second coil and a toroidal core (none of which is shown), the first coil is insulated from the second coil, the first coil and the second coil may have the same size and may be symmetrically wound on the same toroidal core with the same number of turns, an input end of the first coil forms a first input end 110a, an output end of the first coil forms a first output end 111a, an input end of the second coil forms a second input end 110b, and an output end of the second coil forms a second output end 111 b.

In some embodiments, the chip 1 may further include a signal optimization circuit 12, the signal optimization circuit 12 is disposed on the circuit board 10, one end of the signal optimization circuit 12 is electrically connected to the input end 110, the other end of the signal optimization circuit 12 is electrically connected to the output end 111, and the signal optimization circuit 12 is configured to adjust a limit of an amplitude of the communication signal flowing through the output end 111, so as to remove an interference signal carried by the communication signal and having an amplitude that is too high or too low, thereby improving the correctness of the communication signal.

Specifically, the signal optimization circuit 12 may include a first optimization circuit 120 and a second optimization circuit 121, the first optimization circuit 120 is electrically connected between the first input terminal 110a and the first output terminal 111a, the first optimization circuit 120 is configured to adjust an upper limit of an amplitude of the communication signal flowing through the first output terminal 111a to remove the interference signal carried by the communication signal with an excessively high amplitude, the second optimization circuit 121 is electrically connected between the second input terminal 110b and the second output terminal 111b, and the second optimization circuit 121 is configured to adjust a lower limit of an amplitude of the communication signal flowing through the second output terminal 111b to remove the interference signal carried by the communication signal with an excessively low amplitude. It is to be understood that, for the convenience of viewing, the first optimization circuit 120 is not shown in a wired manner in fig. 1 to be electrically connected to the first output end 111a, but one end of the first optimization circuit 120 for electrical connection to the first output end 111a is labeled as an output.

It is understood that the communication signal may be a voltage signal or a current signal to achieve the effect of transmitting information through the circuit, and the communication signal is taken as the voltage signal in the embodiment as an example for description. It will be appreciated that as a voltage signal is passed through a circuit, the magnitude of the voltage in the circuit fluctuates with the voltage signal. During the transmission of the voltage signal, the voltage signal is affected by the interference signal, and an abnormal voltage which causes the voltage amplitude in the circuit to be too high or too low is generated. Therefore, by providing the first optimization circuit 120 for adjusting the upper limit of the amplitude of the communication signal flowing through the first output terminal 111a and the second optimization circuit 121 for adjusting the lower limit of the amplitude of the communication signal flowing through the second output terminal 111b, it is possible to remove the abnormal voltage signal in the circuit, thereby achieving the effect of improving the information transfer accuracy of the voltage signal in the circuit.

Optionally, the first optimization circuit 120 includes a first transistor Q1 and a first zener diode D1, a collector of the first transistor Q1 is electrically connected to a cathode of the first zener diode D1, a base of the first transistor Q1 is electrically connected to the first input terminal 110a, an emitter of the first transistor Q1 is electrically connected to the first output terminal 111a, the first transistor Q1 is configured to conduct when the voltage at the first output terminal 111a is greater than the voltage at the first input terminal 110a, and a voltage difference between the first output terminal 111a and the first input terminal 110a reaches a certain value, so as to conduct the current at the first output terminal 111a to the cathode of the first zener diode D1, so that the current flows to the inside of the first zener diode D1. The positive electrode of the first zener diode D1 is electrically connected to the first output end 111a, and the first zener diode D1 is configured to reduce the voltage of the current flowing through the inside of the first zener diode D1, and output the reduced current to the first output end 111a, so that the first triode Q1 is matched with the first zener diode D1, and a function of removing an interference signal with an excessively high voltage amplitude carried by a voltage signal is achieved.

Optionally, the second optimization circuit 121 includes a second transistor Q2 and a second zener diode D2, a collector of the second transistor Q2 is electrically connected to a cathode of the second zener diode D2, a base of the second transistor Q2 is electrically connected to the second output end 111b, an emitter of the second transistor Q2 is electrically connected to the second input end 110b, the second transistor Q2 is configured to conduct when the voltage at the second output end 111b is lower than the voltage at the second input end 110b, and a voltage difference between the second output end 111b and the second input end 110b reaches a certain value, so as to conduct the current at the second output end 111b to the cathode of the second zener diode D2, so that the current flows to the inside of the second zener diode D2. The anode of the second zener diode D2 is electrically connected to the second output terminal 111b, and the second zener diode D2 is configured to boost the voltage of the current flowing through the inside of the second zener diode D2, and output the boosted current to the second output terminal 111b, so that the second triode Q2 is matched with the second zener diode D2, and a function of removing an interference signal with an excessively low voltage amplitude carried by the voltage signal is achieved.

Optionally, the signal optimization circuit 12 may also include a plurality of other components for performing various functions. In the first example, the signal optimization circuit 12 may further include a resistor R3 electrically connected between the emitter of the first transistor Q1 and the first output terminal 111a, and a resistor R7 electrically connected between the emitter of the second transistor Q2 and the second input terminal 110b, for shunting current to adjust the current. In a second example, the signal optimization circuit 12 may further include a resistor R4 electrically connected between the anode of the first zener diode D1 and the first output terminal 111a for shunting current to protect the first zener diode D1, and a resistor R6 electrically connected between the anode of the second zener diode D2 and the second input terminal 110b for shunting current to protect the second zener diode D2. In the third example, the signal optimization circuit 12 may further include a resistor R5 electrically connected between the base of the first transistor Q1 and the first input terminal 110a, and a resistor R8 electrically connected between the base of the second transistor Q2 and the second output terminal 111b, so as to limit the current and prevent the current in the switch circuit 13 from being too large and damaging the electronic components in the switch circuit 13. In a fourth example, the signal optimization circuit 12 may further include a capacitor C1 electrically connected between the collector of the first transistor Q1 and the first output terminal 111a, and a capacitor C2 electrically connected between the collector of the second transistor Q2 and the second input terminal 110b, for isolating direct current from alternating current.

As shown in fig. 3, in some embodiments, the signal optimization circuit 12 may be at least partially disposed on the second surface 101, that is, the signal optimization circuit 12 may be at least partially disposed on a different surface of the circuit board 10 from the choke coil 11, so that the overall structure of the chip 1 is more compact, and the chip 1 can be miniaturized.

Alternatively, in order to meet the actual layout requirement, the signal optimization circuit 12 may be disposed on the second surface 101 as a whole, or the first optimization circuit 120 may be disposed on the second surface 101 and the second optimization circuit 121 may be disposed on the first surface 100, or the first optimization circuit 120 may be disposed on the first surface 100 and the second optimization circuit 121 may be disposed on the second surface 101 according to the actual situation.

Referring to fig. 1 again, in some embodiments, the switching circuit 13 includes a third transistor Q3 and a field effect transistor Q4 electrically connected to each other, the field effect transistor Q4 is electrically connected between the power source 20 and the input terminal 110, and the third transistor Q3 is used for controlling the field effect transistor Q4 to switch between on and off, so as to turn on or off the circuit between the power source 20 and the input terminal 110, so as to implement the switching function of the power source 20 of the switching circuit 13.

It is understood that the switch circuit 13 can be electrically connected between the second input terminal 110b and the negative pole of the power supply 20, or between the first input terminal 110a and the positive pole of the power supply 20. Taking the example that the switch circuit 13 is electrically connected between the second input terminal 110b and the negative electrode of the power supply 20, specifically, the source of the fet Q4 is electrically connected to the negative electrode of the power supply 20, the drain of the fet Q4 is electrically connected to the second input terminal 110b, when the fet Q4 is turned on, the negative electrode of the power supply 20 is turned on with the second input terminal 110b, so that the circuit formed by the chip 1 and the power supply 20 forms a closed loop, the power supply 20 can output current through the chip 1, when the fet Q4 is turned off, the circuit formed by the chip 1 and the power supply 20 is turned off at the fet Q4, and cannot form a closed loop, so that the power supply 20 cannot output current through the chip 1.

Further, in order to realize the automatic control of the switch circuit 13, the chip 1 may further include a micro control unit IC and a pull-down resistor R12, the micro control unit IC is electrically connected to the base of the third transistor Q3, the micro control unit IC is configured to output a high level to the base of the third transistor Q3, the pull-down resistor R12 is electrically connected between the negative electrode of the power supply 20 and the base of the third transistor Q3, the pull-down resistor R12 is configured to output a low level to the base of the third transistor Q3, the emitter of the third transistor Q3 is electrically connected to the source of the fet Q4, and the collector of the third transistor Q3 is electrically connected to the gate of the fet Q4 and the negative electrode of the power supply.

Specifically, when the base of the third transistor Q3 receives the high level output by the mcu IC, a voltage difference is generated between the base and the collector of the third transistor Q3, the third transistor Q3 is turned on under the action of the voltage difference, and the emitter of the third transistor Q3 outputs a low level to the source of the fet Q4, so that the drain and the source of the fet Q4 are turned on under the action of the voltage difference, and the second input terminal 110b is connected to the second output terminal 111b, and the power supply 20 is turned on. When the mcu IC stops outputting the high level to the base of the third transistor Q3, the base of the third transistor Q3 receives the low level from the pull-down resistor R12, and there is no voltage difference between the base and the collector of the third transistor Q3 to turn on the third transistor Q3, so the third transistor Q3 is turned off, and accordingly, the drain and the source of the fet Q4 are also turned off, the second input terminal 110b is turned off from the second output terminal 111b, and the circuit included in the chip 1 cannot form a loop, thereby turning off the power supply 20.

Further, the switch circuit 13 may further include a resistor 10 electrically connected between the collector of the third transistor Q3 and the gate of the fet Q4 for limiting the current and preventing the current in the switch circuit 13 from being too large to damage the electronic components in the switch circuit 13. More specifically, the switch circuit 13 may further include a resistor 11 electrically connected between the power supply 20 and the collector of the third transistor Q3, and a resistor 13 electrically connected between the negative electrode of the power supply 20 and the collector of the third transistor Q3, for dividing the current to avoid the voltage in the switch circuit 13 from being too high and damaging the electronic components in the switch circuit 13.

Referring to fig. 1 again, in some embodiments, the chip 1 further includes a monitoring circuit 14, the monitoring circuit 14 is disposed on the circuit board 10, the monitoring circuit 14 is configured to monitor circuit data between the power supply 20 and the input terminal 110, specifically, the monitoring circuit 14 is electrically connected between the positive electrode of the power supply 20 and the first input terminal 110a, so as to monitor an output current of the positive electrode of the power supply 20, so that a user can monitor a working state of the power supply 20, and the user can obtain information in time when an output state of the power supply 20 is abnormal, so as to perform maintenance.

Specifically, the monitoring circuit 14 may include a first resistor R1 and a current sense amplifier U1, the first resistor R1 is electrically connected between the positive electrode of the power supply 20 and the first input terminal 110a, the current sense amplifier U1 is disposed in parallel with the first resistor R1, and the current sense amplifier U1 is configured to detect a current flowing through the first resistor R1, so as to monitor the operating state of the power supply 20 by monitoring the magnitude of the current output by the positive electrode of the power supply 20. It is understood that in other embodiments, the monitoring circuit 14 may also monitor the operating state of the power supply 20 by monitoring the voltage level between the negative pole of the power supply 20 and the second input terminal 110 b.

Optionally, a current sense amplifier U1 may be used to electrically connect to the mcu IC to transmit current data of the power supply 20 to the mcu IC so that the mcu IC can be used to process the current data measured by the monitoring circuit 14. Further, the signal optimization circuit 12 may further include a resistor R2 electrically connected between the current detection amplifier U1 and the mcu IC for limiting the current flowing to the mcu IC, so as to prevent the mcu IC from being damaged due to excessive current flowing into the mcu IC.

As shown in fig. 3, in some embodiments, the monitoring circuit 14 is disposed on the second surface 101, that is, the monitoring circuit 14 and the choke 11 may be disposed on different surfaces of the circuit board 10, so that the overall structure of the chip 1 is more compact, and the chip 1 can be designed in a smaller size.

It is understood that at least one of the first optimization circuit 120, the second optimization circuit 121 and the monitoring circuit 14 may be located on the second side 101, or the first optimization circuit 120, the second optimization circuit 121 and the monitoring circuit 14 may be located on the first side 100, in order to meet the actual layout requirements.

Preferably, since the volume of the choke 11 is much larger than the volume of each component included in the signal optimization circuit 12 and the detection circuit in a normal situation, in order to achieve the miniaturized design of the chip 1 to the maximum extent, the signal optimization circuit 12 and the monitoring circuit 14 are both located on the second surface 101, as shown in fig. 3 and fig. 4, fig. 4 is a schematic structural diagram of the second surface 101 of the circuit board 10 disclosed in the first embodiment of the present invention, wherein arrows in fig. 4 show four directions, namely, up, down, left, and right.

Specifically, the second face 101 may include a first region 101a, a second region 101b, a third region 101c, and a fourth region 101d connected as shown in fig. 4, and the dotted lines in fig. 4 show the boundary lines of the four regions. The second area 101b, the third area 101c, and the fourth area 101d are all located on the right side of the first area 101a, and are arranged in sequence from bottom to top, that is, the second area 101b, the third area 101c, and the fourth area 101d are arranged in sequence from bottom to top. The first input end 110a, the first output end 111a, the second input end 110b and the second output end 111b extend from the first surface 100 to the second surface 101 through the circuit board 10, the first input end 110a and the second output end 111b are located on the left side of the first region 101a, the first input end 110a is located above the second output end 111b, the first output end 111a and the second input end 110b are located on the right side of the third region 101c, and the first output end 111a is located above the second input end 110 b. The switch circuit 13 is disposed in the first region 101a, the second optimization circuit 121 is disposed in the second region 101b, the first optimization circuit 120 is disposed in the third region 101c, and the monitor circuit 14 is disposed in the fourth region 101 d. Thereby on the one hand can clearly locate second face 101 with each circuit function division that chip 1 includes, make the overall arrangement regular, on the other hand can make the overall arrangement of each circuit more reasonable, promptly, makes between each circuit to and each circuit and input 110 or output 111 between be connected the line simply, thereby simplify circuit board 10's the line design of walking.

According to the chip 1 disclosed by the first embodiment of the utility model, the choke coil 11 is arranged on the circuit board 10, and the choke coil 11 is electrically connected between the output end 111 of the KNX bus power circuit 2 and the power supply 20, so that the characteristics of direct current and alternating current resistance of the choke coil 11 are utilized, the direct current output by the KNX bus power circuit 2 is ensured to be normally output, the communication signal at the output end 111 of the KNX bus power circuit 2 is prevented from entering the power supply 20, and the power supply 20 is prevented from generating interference on the communication signal, so that the communication accuracy between the devices is improved. More specifically, by providing the first optimization circuit 120 for removing the interference signal with the excessively high voltage amplitude carried by the communication signal and the second optimization circuit 121 for removing the interference signal with the excessively low voltage amplitude carried by the communication signal on the circuit board 10, the optimization function of the communication signal can be realized, so that the accuracy of the communication signal is further improved.

Meanwhile, the choke coil 11 is arranged on the first surface 100 of the circuit board 10, and the switch circuit 13, the signal optimization circuit 12 and the monitoring circuit 14 are arranged on the second surface 101, so that the whole structure of the chip 1 is more compact, and the miniaturization design of the chip 1 can be realized.

Example two

Referring to fig. 1 again, fig. 1 is a circuit diagram of a KNX bus power circuit 2 disclosed in a second embodiment of the present invention, and the second embodiment of the present invention discloses a KNX bus power circuit, where the KNX bus power circuit 2 includes a power supply 20 and a chip 1 according to the first embodiment of the present invention, and the KNX bus power circuit 2 is electrically connected to a KNX bus to supply power to the KNX bus. The disclosed KNX bus power supply circuit 2 of this embodiment is used for the electricity to connect in the chip 1 of KNX bus through the setting to make power 20 electrically connect in chip 1, so that power 20 can connect in the KNX bus through chip 1 electricity, in order to realize carrying out the function of supplying power to the KNX bus, simultaneously, utilize chip 1 to realize blockking the effect that communication signal in the KNX bus got into power 20, in order to avoid power 20 to produce the interference to the communication signal in the KNX bus.

The chip and the KNX bus power supply circuit disclosed by the embodiment of the utility model are described in detail, a specific example is applied in the description to explain the principle and the implementation mode of the utility model, and the description of the embodiment is only used for helping to understand the chip, the KNX bus power supply circuit and the core idea of the chip and the KNX bus power supply circuit; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (10)

1. A chip for application to a KNX bus power supply circuit, the KNX bus power supply circuit having a power supply, the chip comprising:

the circuit board comprises a first surface and a second surface which are opposite;

a choke disposed on the first face, the choke having an input end for electrical connection with the power source and an output end for outputting a current; and the number of the first and second groups,

the switch circuit is arranged on the second surface and is electrically connected between the input end and the power supply, and the switch circuit is used for controlling the on-off of a circuit between the input end and the power supply.

2. The chip of claim 1, further comprising a signal optimization circuit disposed on the circuit board, one end of the signal optimization circuit being electrically connected to the input terminal, the other end of the signal optimization circuit being electrically connected to the output terminal, the signal optimization circuit being configured to adjust a limit of an amplitude of a communication signal flowing through the output terminal.

3. The chip of claim 1, wherein the input terminals comprise a first input terminal and a second input terminal, the first input terminal is configured to be electrically connected to a positive pole of the power supply, and the second input terminal is configured to be electrically connected to a negative pole of the power supply;

the output end comprises a first output end and a second output end, the first output end is used for outputting positive voltage current, and the second output end is used for outputting negative voltage current;

the first input end is electrically connected with the first output end, the second input end is electrically connected with the second output end, the switch circuit is electrically connected between the second input end and the negative electrode of the power supply, and the switch circuit is used for controlling the circuit between the second input end and the negative electrode of the power supply to be switched on or switched off.

4. The chip of claim 3, further comprising a signal optimization circuit, wherein the signal optimization circuit comprises a first optimization circuit electrically connected between the first input terminal and the first output terminal, the first optimization circuit configured to adjust an upper limit of an amplitude of the communication signal flowing through the first output terminal, and a second optimization circuit electrically connected between the second input terminal and the second output terminal, the second optimization circuit configured to adjust a lower limit of an amplitude of the communication signal flowing through the second output terminal.

5. The chip according to claim 4, wherein the first optimization circuit includes a first transistor and a first zener diode, an emitter of the first transistor is electrically connected to the first output terminal, a base of the first transistor is electrically connected to the first input terminal, the first zener diode is electrically connected between a collector of the first transistor and the first output terminal, the first transistor is configured to be turned on when a voltage at the first output terminal is greater than a voltage at the first input terminal, and a voltage difference between the first output terminal and the first input terminal reaches a certain value, so as to control the first zener diode to be turned on, thereby reducing the voltage at the first output terminal;

the second optimization circuit comprises a second triode and a second voltage stabilizing diode, wherein an emitting electrode of the second triode is electrically connected with the second input end, a base electrode of the second triode is arranged between the second output end, the second voltage stabilizing diode is electrically connected between a collector electrode of the second triode and the second output end, the second triode is used for controlling the conduction of the second voltage stabilizing diode when the voltage at the second output end is smaller than the voltage at the second input end, and the voltage difference between the second output end and the second input end reaches a certain value, so that the conduction of the second voltage stabilizing diode is controlled, and the voltage output at the second output end is improved.

6. The chip of claim 2, 4 or 5, wherein the signal optimization circuit is at least partially disposed on the second side.

7. The chip of claim 1 or 3, wherein the switch circuit comprises a third transistor and a field effect transistor electrically connected, the field effect transistor is electrically connected between the power supply and the input terminal, and the third transistor is configured to control the field effect transistor to switch between on and off to turn on or off the circuit between the power supply and the input terminal.

8. The chip of claim 1, further comprising a monitoring circuit disposed on the circuit board, the monitoring circuit configured to monitor circuit data between the power source and the input terminal, the monitoring circuit disposed on the second side.

9. The chip of claim 8, wherein the monitoring circuit comprises a first resistor and a current sense amplifier, the first resistor is electrically connected between the power supply and the input terminal, the current sense amplifier is connected in parallel with the first resistor, and the current sense amplifier is configured to sense a current flowing through the first resistor.

10. A KNX bus power supply circuit comprising a power supply and a chip as claimed in any one of claims 1 to 9.

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