CN215494755U - Wave-by-wave current limiting circuit and power utilization system - Google Patents
Wave-by-wave current limiting circuit and power utilization system Download PDFInfo
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- CN215494755U CN215494755U CN202120531309.9U CN202120531309U CN215494755U CN 215494755 U CN215494755 U CN 215494755U CN 202120531309 U CN202120531309 U CN 202120531309U CN 215494755 U CN215494755 U CN 215494755U
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Abstract
The embodiment of the utility model relates to the technical field of electronics, in particular to a wave-by-wave current limiting circuit and an electric system. The utility model provides a wave-by-wave current limiting circuit, which comprises a power frequency current limiting circuit, a high-frequency current limiting circuit and a combined current limiting circuit. The input ends of the power frequency current limiting circuit and the high-frequency current limiting circuit are connected with the bus sampling resistor, the output ends of the power frequency current limiting circuit and the high-frequency current limiting circuit are connected with the driving circuit, the input end of the combined current limiting circuit is connected with the output end of the power frequency current limiting circuit, and the output end of the combined current limiting circuit is connected with the output end of the high-frequency current limiting circuit. The present invention also provides an electricity utilization system, including: the current sampling circuit collects the current of the negative terminal of the bus of the full-bridge inverter circuit and sends the current to the wave-chasing current-limiting circuit, and the current sampling circuit is used for amplifying the current of the negative terminal of the bus. The utility model can protect the power tube, improve the stability of the circuit, select the power tube with smaller power and reduce the cost.
Description
Technical Field
The embodiment of the utility model relates to the technical field of electronics, in particular to a wave-by-wave current limiting circuit and an electric system.
Background
The inverter output needs to be compatible with various loads and has pure resistive loads, such as a black-wire bulb, a hot water kettle and the like; there are inductive loads with relatively large impact, such as cutting machines, air conditioners, etc.
In circuitries, a large current, namely an instantaneous impact current, is usually generated at the moment of electrifying a load, and when the load is a load with a large instantaneous impact current, if the load is not protected in time, a power tube in an inverter circuit is easily damaged, so that the stability of the circuit is affected. Therefore, the bus current in the inverter circuit needs to be detected in real time, and when the bus current is larger than the preset instantaneous impact current, the power tube is turned off in time, so that the power tube is prevented from being damaged.
The existing wave-by-wave current limiting method mostly adopts a method of sealing waves of all power tubes when an inverter circuit is sealed, and the method has the problems that all power tubes are easily and frequently triggered to be cut off and limited in current, so that the service life of the power tubes is shortened, and in addition, in order to effectively prevent the damage of the power tubes, the power tubes with larger power are generally selected, so that the cost is higher.
Disclosure of Invention
The embodiment of the utility model aims to provide a wave-by-wave current limiting circuit and an electric system, so that a power tube can limit current in time, protect the power tube and improve the stability of the circuit; the full-bridge inverter circuit is controlled more accurately, the high-frequency tube can select a power tube with smaller power, and the cost is reduced; the turn-off frequency of the power frequency pipe is reduced, and the service life of the power frequency pipe is prolonged.
In order to solve the above technical problem, one technical solution adopted by the embodiments of the present invention is: providing a wave-by-wave current limiting circuit, wherein the wave-by-wave current limiting circuit comprises a power frequency tube current limiting circuit, a high frequency tube current limiting circuit and a combined current limiting circuit; the input end of the power frequency tube current limiting circuit is connected with the output end of the current sampling circuit, the current sampling circuit is used for sampling the current of the negative terminal of the bus, the output end of the power frequency tube current limiting circuit is connected with the driving circuit, the power frequency tube current limiting circuit is used for detecting whether the output current of the current sampling circuit is larger than a first preset current or not, and if the output current of the current sampling circuit is larger than the first preset current, a first overcurrent signal is sent to the driving circuit, so that the power frequency tube of the full-bridge inverter circuit is controlled to be turned off; the input end of the high-frequency tube current limiting circuit is connected with the output end of the current sampling circuit, the output end of the high-frequency tube current limiting circuit is connected with the driving circuit, the high-frequency tube current limiting circuit is used for detecting whether the output current of the current sampling circuit is larger than a second preset current, and if the output current of the current sampling circuit is larger than the second preset current, a second overcurrent signal is sent to the driving circuit, so that the high-frequency tube of the full-bridge inverter circuit is controlled to be turned off; the input end of the combined current limiting circuit is connected with the output end of the power frequency tube current limiting circuit, the output end of the combined current limiting circuit is connected with the output end of the high-frequency tube current limiting circuit, and when the combined current limiting circuit receives the first overcurrent signal, the combined current limiting circuit sends a third overcurrent signal to the driving circuit to control the high-frequency tube of the full-bridge inverter circuit to be switched off.
In some embodiments, the power frequency tube current limiting circuit comprises: a first voltage comparison circuit and a first reference voltage supply circuit. The first input end of the first voltage comparison circuit is connected with the output end of the current sampling circuit, the second input end of the first voltage comparison circuit is connected with the output end of the first reference voltage providing circuit, and the output end of the first voltage comparison circuit is connected with the input end of the driving circuit.
In some embodiments, the high frequency tube current limiting circuit includes: a second voltage comparison circuit and a second reference voltage supply circuit. The first input end of the second voltage comparison circuit is connected with the output end of the current sampling circuit, the second input end of the second voltage comparison circuit is connected with the output end of the second reference voltage providing circuit, and the output end of the second voltage comparison circuit is connected with the input end of the driving circuit.
In some embodiments, the joint current limiting circuit comprises: the input end of the triode switch switching circuit is connected with the output end of the power frequency tube current limiting circuit, the output end of the triode switch switching circuit is connected with one end of the time delay circuit, and the other end of the time delay circuit is connected with the output end of the high-frequency tube current limiting circuit.
In some embodiments, the first voltage comparison circuit comprises: a fourth resistor and a first voltage comparator; the positive phase input end of the first voltage comparator is connected with the output end of the current sampling circuit, the negative phase input end of the first voltage comparator is connected with the output end of the first reference voltage providing circuit, the output end of the first voltage comparator is connected with the input end of the driving circuit, the first end of the fourth resistor is connected with the output end of the first voltage comparator, and the second end of the fourth resistor is connected with the second power supply.
In some embodiments, the first reference voltage providing circuit includes: a second resistor and a third resistor; the first end of the second resistor is connected with the first end of the third resistor, the second end of the second resistor is connected with the first power supply, and the second end of the third resistor is grounded.
In some embodiments, the second voltage comparison circuit comprises: a seventh resistor and a second voltage comparator; the positive phase input end of the second voltage comparator is connected with the output end of the current sampling circuit, the negative phase input end of the second voltage comparator is connected with the output end of the second reference voltage providing circuit, the output end of the second voltage comparator is connected with the input end of the driving circuit, the first end of the seventh resistor is connected with the output end of the second voltage comparator, and the second end of the seventh resistor is connected with the fourth power supply.
In some embodiments, the second reference voltage providing circuit includes: a fifth resistor and a sixth resistor; the first end of the fifth resistor is connected with the first end of the sixth resistor, the second end of the fifth resistor is connected with a third power supply, and the second end of the sixth resistor is grounded.
In some embodiments, the triode switch switching circuit comprises: the first PNP triode and the second NPN triode are connected with the first resistor and the second resistor respectively; the first end of the eighth resistor is connected with the base of the first NPN transistor, the second end of the eighth resistor is grounded, the emitter of the first NPN transistor is grounded, the collector of the first NPN transistor is connected with the first end of the ninth resistor, and the second end of the ninth resistor is connected with the first end of the tenth resistor and the base of the first PNP transistor respectively. The second end of the tenth resistor is connected with a fifth power supply, the emitter of the first PNP tube is connected with the fifth power supply, the collector of the first PNP tube is respectively connected with the first end of the delay circuit and the driving circuit, and the second end of the delay circuit is grounded.
In some embodiments, the delay circuit comprises: an eleventh resistor, a first capacitor, a first diode; the first end of the eleventh resistor is connected with the output end of the triode switch conversion circuit and the first end of the first capacitor respectively, the second end of the eleventh resistor is grounded, the second end of the first capacitor is grounded, the anode of the first diode is connected with the output end of the triode switch conversion circuit, the first end of the eleventh resistor and the first end of the first capacitor respectively, and the cathode of the first diode is connected with the driving circuit.
In some embodiments, there is also provided a power utilization system comprising a wave-by-wave current limiting circuit and a current sampling circuit, wherein the current sampling circuit comprises: a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor and a first operational amplifier; the first end of the twelfth resistor is connected with the first end of the bus negative terminal of the full-bridge inverter circuit, the second end of the twelfth resistor is connected with the first end of the thirteenth resistor and the inverting input end of the first operational amplifier respectively, the second end of the thirteenth resistor is connected with the output end of the first operational amplifier, the first end of the fourteenth resistor is connected with the second end of the bus negative terminal of the full-bridge inverter circuit, the second end of the fourteenth resistor is connected with the first end of the fifteenth resistor and the positive phase input end of the first operational amplifier respectively, the second end of the fifteenth resistor is grounded, and the output end of the first operational amplifier is further connected with the input end of the wave-chasing current-limiting circuit.
The beneficial effects of the embodiment of the utility model are as follows: the utility model provides a wave-by-wave current limiting circuit which is different from the prior art, and is provided with a power frequency tube current limiting circuit, a high-frequency tube current limiting circuit and a combined current limiting circuit, the current of the negative terminal of a bus in a full-bridge inverter circuit is detected, and the turn-off of a power tube in the full-bridge inverter circuit is controlled according to the current condition, so that the power tube can limit the current in time, protect the power tube and improve the stability of the circuit; the secondary protection is designed, so that the full-bridge inverter circuit is controlled more accurately, the high-frequency tube can select a power tube with smaller power, and the cost is reduced; the turn-off frequency of the power frequency pipe is reduced, and the service life of the power frequency pipe is prolonged.
Drawings
One or more embodiments are illustrated by the accompanying figures in the drawings that correspond thereto and are not to be construed as limiting the embodiments, wherein elements/modules and steps having the same reference numerals are represented by like elements/modules and steps, unless otherwise specified, and the drawings are not to scale.
Fig. 1 is a schematic structural diagram of a wave-by-wave current limiting circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a wave-by-wave current limiting circuit according to an embodiment of the present invention;
fig. 3 is a circuit diagram of a wave-by-wave current limiting circuit according to an embodiment of the utility model;
fig. 4 is a schematic structural diagram of an electric system according to an embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of another power utilization system according to an embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of another power utilization system according to an embodiment of the present invention;
fig. 7 is a schematic circuit structure diagram of another power utilization system according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the utility model, but are not intended to limit the utility model in any way. It should be noted that variations and modifications can be made by persons skilled in the art without departing from the spirit of the utility model. All falling within the scope of the present invention.
In order to facilitate an understanding of the present application, the present application is described in more detail below with reference to the accompanying drawings and specific embodiments. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It should be noted that, if not conflicted, the various features of the embodiments of the utility model may be combined with each other within the scope of protection of the present application. In addition, although the functional blocks are divided in the device diagram, in some cases, the blocks may be divided differently from those in the device. Further, the terms "first," "second," and the like, as used herein, do not limit the data and the execution order, but merely distinguish the same items or similar items having substantially the same functions and actions.
Referring to fig. 1, fig. 1 is a schematic structural block diagram of a wave-by-wave current limiting circuit according to an embodiment of the present invention, where the wave-by-wave current limiting circuit 100 includes a power frequency tube current limiting circuit 10, a high frequency tube current limiting circuit 11, and a combined current limiting circuit 12.
The input end of the current sampling circuit is connected with the negative end of the bus of the full-bridge inverter circuit, the output end of the current sampling circuit is respectively connected with the input ends of the power frequency tube current limiting circuit 10 and the high-frequency tube current limiting circuit 11, and the current sampling circuit is used for collecting the current of the negative end of the bus of the full-bridge inverter circuit and sending current signals to the power frequency tube current limiting circuit 10 and the high-frequency tube current limiting circuit 11;
the output end of the power frequency tube current limiting circuit 10 is connected with the first end of the driving circuit, and the power frequency tube current limiting circuit 10 is used for detecting whether the current of the negative bus end of the full-bridge inverter circuit is larger than the current limiting threshold value of the power frequency tube or not and sending an overcurrent signal of the power frequency tube to the driving circuit;
the output end of the high-frequency tube current limiting circuit 11 is connected with the second end of the driving circuit, and the high-frequency tube current limiting circuit 11 is used for detecting whether the current of the negative terminal of the bus of the full-bridge inverter circuit is larger than a high-frequency tube current limiting threshold value or not and sending a high-frequency tube overcurrent signal to the driving circuit;
the input end of the combined current limiting circuit 12 is connected with the output end of the power frequency tube current limiting circuit 10, the output end of the combined current limiting circuit 12 is connected with the output end of the high-frequency tube current limiting circuit 11, and when the power frequency tube current limiting circuit 10 outputs a high-level signal, the high-frequency tube current limiting circuit also outputs the high-level signal.
The utility model provides a wave-by-wave current limiting circuit, which is provided with a power frequency tube current limiting circuit, a high-frequency tube current limiting circuit and a combined current limiting circuit, detects the current of the negative terminal of a bus in a full-bridge inverter circuit, and controls the turn-off of a power tube in the full-bridge inverter circuit according to the current condition, so that the power tube can limit the current in time, protect the power tube and improve the stability of the circuit; the secondary protection is designed, so that the full-bridge inverter circuit is controlled more accurately, the high-frequency tube can select a power tube with smaller power, and the cost is reduced; the turn-off frequency of the power frequency pipe is reduced, and the service life of the power frequency pipe is prolonged.
In some embodiments, referring to fig. 2, the power frequency tube current limiting circuit 10 includes a first reference voltage providing circuit 101 and a first voltage comparing circuit 102. The first reference voltage providing circuit 101 provides a first reference voltage for the first voltage comparing circuit 102, the first voltage comparing circuit 102 is used for comparing the negative terminal voltage of the bus with the first reference voltage, when the negative terminal voltage of the bus is greater than or equal to the first reference voltage, the output end SDL of the first voltage comparing circuit 102 outputs a high level signal, the signal is connected to the driving circuit, and the driving circuit closes the power frequency tube of the full-bridge driving circuit, so that the power frequency tube is protected.
The high-frequency tube current limiting circuit 11 includes a second reference voltage supply circuit 111 and a second voltage comparison circuit 112. The second reference voltage providing circuit 111 provides a second reference voltage for the second voltage comparing circuit 112, the second voltage comparing circuit 112 is used for comparing the negative terminal voltage of the bus with the second reference voltage, when the negative terminal voltage of the bus is greater than or equal to the second reference voltage, the output end SDH of the second voltage comparing circuit 112 outputs a high level signal, the signal is connected to the driving circuit, and the driving circuit closes the high frequency tube of the full bridge inverter circuit, thereby protecting the high frequency tube.
The combined current limiting circuit 12 includes a triode switch switching circuit 121 and a delay circuit 122. Triode switch converting circuit 121 is used for when triggering the power frequency pipe current-limiting, trigger the high frequency pipe current-limiting through triode switch converting circuit simultaneously, because when triggering the power frequency pipe current-limiting, if trigger the high frequency pipe current-limiting not simultaneously, the high frequency pipe will continue the periodic opening and shutting, when the high frequency pipe switches on, constitute the return circuit by the high frequency pipe, inductive load, power frequency top tube, the energy of inductive load storage is released, and this return circuit current does not pass through the sampling resistance of bus negative terminal, lead to the electric current not to receive the restriction, cause the power frequency top tube to exceed the avalanche energy damage easily. The delay circuit 122 is used for determining the time length for triggering the high-frequency tube to limit the current when triggering the power frequency tube to limit the current.
In some embodiments, referring to fig. 3, the ripple current limiting circuit 100 includes a first resistor R1, a power frequency tube current limiting circuit 10, a high frequency tube current limiting circuit 11, and a combined current limiting circuit 12. The power frequency tube current limiting circuit 10 comprises a first reference voltage providing circuit and a first voltage comparison circuit, wherein the first reference voltage providing circuit comprises a second resistor R2 and a third resistor R3, and the first voltage comparison circuit comprises a fourth resistor R4 and a first voltage comparator U1; the first end of the first resistor R1 is connected with the output end of the current sampling circuit, the second end of the first resistor R1 is connected with the non-inverting input end of the first voltage comparator U1, the first end of the second resistor R2 is respectively connected with the first end of the third resistor R3 and the inverting input end of the first voltage comparator U1, the second end of the second resistor R2 is connected with the first power supply, the second end of the third resistor is grounded, the first end of the fourth resistor R4 is connected with the output end of the first voltage comparator U1, the second end of the fourth resistor R4 is connected with the second power supply, and the output end of the first voltage comparator U1 is connected with the driving circuit.
The first resistor R1 is used for collecting an output current FIB of the current sampling circuit 200, the second resistor R2 and the third resistor R3 form a voltage division circuit used for adjusting the size of the first reference voltage, and the fourth resistor R4 is a pull-up resistor, so that the first voltage comparator U1 can output a high level. When the voltage of the positive phase input end of the first voltage comparator U1 is greater than or equal to the voltage of the negative phase input end, namely the current of the negative end of the bus is greater than or equal to the current limiting threshold value of the power frequency tube, the output end SDL of the first voltage comparator U1 outputs a high level signal, the signal is connected to a driving circuit, and the driving circuit enables the power frequency tube of the full-bridge inverter circuit to be closed, so that the power frequency tube is protected.
The high-frequency tube current limiting circuit 11 comprises a second reference voltage providing circuit and a second voltage comparison circuit, wherein the second reference voltage providing circuit comprises a fifth resistor R5 and a sixth resistor R6, and the second voltage comparison circuit comprises a seventh resistor R7 and a second voltage comparator U2; the first end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the inverting input end of the second voltage comparator U2, the second end of the fifth resistor R5 is connected to the third power supply, the second end of the sixth resistor R6 is grounded, the non-inverting input end of the second voltage comparator U2 is connected to the second end of the first resistor R1, the first end of the seventh resistor R7 is connected to the output end of the second voltage comparator U2, the second end of the seventh resistor R7 is connected to the fourth power supply, and the output end of the second voltage comparator U2 is connected to the driving circuit.
The fifth resistor R5 and the sixth resistor R6 form a voltage divider circuit for adjusting the magnitude of the second reference voltage, and the seventh resistor R7 is a pull-up resistor, so that the second voltage comparator U2 can output a high level. When the voltage of the positive phase input end of the second voltage comparator U2 is greater than or equal to the voltage of the negative phase input end, that is, the current of the negative end of the bus is greater than or equal to the current limiting threshold value of the high-frequency tube, the output end SDH of the voltage comparator outputs a high-level signal, the signal is connected to a driving circuit, and the driving circuit closes the power frequency tube of the full-bridge inverter circuit, so that the power frequency tube is protected.
The combined current limiting circuit 12 comprises a triode switch conversion circuit, and the triode switch conversion circuit comprises an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a first NPN triode Q1 and a first PNP triode Q2; a first end of the eighth resistor is connected to the base of the first NPN transistor Q1, a second end of the eighth resistor is grounded, an emitter of the first NPN transistor Q1 is grounded, a collector of the first NPN transistor Q1 is connected to a first end of the ninth resistor R9, and a second end of the ninth resistor R9 is connected to a first end of the tenth resistor R10 and a base of the first PNP transistor Q2, respectively. The second end of the tenth resistor R10 is connected to a fifth power supply, the emitter of the first PNP transistor Q2 is connected to the fifth power supply, and the collector of the first PNP transistor Q2 is grounded.
When the power frequency current limiting is triggered, the SDL signal is in a high level, the first NPN triode Q1 is turned on, the base electrode of the first PNP triode Q2 is pulled down, and the first PNP triode Q2 is turned on. The power supply 5V _ INV is passed to the output terminal of the high frequency transistor current limiting circuit 12, so that the SDH signal also becomes high level. The purpose is when triggering the power frequency, pin high frequency pipe signal simultaneously.
In order to control the time for the high frequency tube to perform current limiting when the power frequency tube is triggered to perform current limiting, in other embodiments, referring to fig. 2 and fig. 3 together, the combined current limiting circuit 12 further includes a delay circuit 122, and the delay circuit 122 includes an eleventh resistor R11, a first capacitor C1, and a first diode D1. A first end of the eleventh resistor R11 is connected to the output end of the triode switch switching circuit, the first end of the first capacitor C1, and the anode of the first diode D1, respectively, a second end of the eleventh resistor R11 is grounded, a second end of the first capacitor C1 is grounded, and a cathode of the first diode D1 is connected to the driving circuit.
When the power frequency current limiting is triggered, the SDL signal is in a high level, the first NPN triode Q1 is turned on, the base electrode of the first PNP triode Q2 is pulled down, and the first PNP triode Q2 is turned on. The power supply 5V _ INV charges the first capacitor C1, and when the first capacitor C1 is fully charged, the first diode D1 discharges to the output end SDH of the high frequency transistor current limiting circuit 12, so that the output signal also becomes high level, the time for maintaining the high level is determined by the eleventh resistor R11 and the first capacitor C1, the energy stored in the first capacitor C1 is discharged by the eleventh resistor R11, and the eleventh resistor R11 is a discharging resistor.
Referring to fig. 4, an electrical system 1000 includes a ripple-by-ripple current limiting circuit 100 and a current sampling circuit 200, and referring to fig. 5, the current sampling circuit 200 includes a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, and a first operational amplifier U3.
The first end of a twelfth resistor R12 is connected with the first end of the bus negative terminal of the full-bridge inverter circuit, the second end of the twelfth resistor R12 is respectively connected with the first end of a thirteenth resistor R13 and the inverting input end of a first operational amplifier U3, the second end of the thirteenth resistor R13 is connected with the output end of a first operational amplifier U3, the first end of a fourteenth resistor R14 is connected with the second end of the bus negative terminal of the full-bridge inverter circuit, the second end of the fourteenth resistor R14 is respectively connected with the first end of a fifteenth resistor R15 and the non-inverting input end of a first operational amplifier U3, the second end of the fifteenth resistor R15 is grounded, and the output end of the first operational amplifier U3 is further connected with the input ends of the power frequency tube current limiting circuit 11 and the high frequency tube current limiting circuit 12.
The current sampling circuit 200 is actually an operational amplifier circuit, and samples and amplifies the current at the negative terminal of the bus, and sends the current to the input terminals of the power frequency tube current limiting circuit 11 and the high frequency tube current limiting circuit 12, and the amplification factor is determined by a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14 and a fifteenth resistor R15.
In some embodiments, referring to fig. 4 again, the power utilization system 1000 further includes a driving circuit 300, the driving circuit is connected to the full-bridge inverter circuit, and the driving circuit 300 is configured to drive the power transistor of the full-bridge inverter circuit to operate and receive the overcurrent signals from the power frequency transistor current limiting circuit 10, the high frequency transistor current limiting circuit 11, and the combined current limiting circuit 12. Referring to fig. 6, the driving circuit 300 may be formed by two half-bridge driving chips with the same model, the model of the driving chip may be SLM2110, EG2113D, IR2110S, etc., and the driving chip may provide driving waveforms for the power frequency tube and the high frequency tube to control the on and off of the power frequency tube and the high frequency tube.
In some embodiments, referring again to fig. 4, the power system 1000 further includes a control module 400, the control module 400 is connected to the driving circuit, and the control module 400 may employ an STM8 series, an STM32 series, or other micro-control processor capable of outputting a sine wave pulse width modulated (SPWM) driving waveform to provide the driving circuit with the sine wave pulse width modulated (SPWM) driving waveform.
In some embodiments, referring to fig. 4 again, the power consumption system 1000 further includes a full-bridge inverter circuit 500, referring to fig. 7, the full-bridge inverter circuit 500 includes a first high-frequency tube Q3, a second high-frequency tube Q4, a first power frequency tube Q5, a second power frequency tube Q6, a first inductor L1, a second capacitor C2, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, and a twenty-fourth resistor R24;
the source of the first high-frequency tube Q3 is connected with the drain of the second high-frequency tube Q4 and the first end of the first inductance L1, the drain of the first high-frequency tube Q3 is connected with the drain of the first power frequency tube Q5, the source of the first power frequency tube Q5 is connected with the drain of the second power frequency tube Q6, the source of the second high-frequency tube Q4 is connected with the source of the second power frequency tube Q6, the second end of the first inductance L1 is connected with the first end of the second capacitance C2 and the positive pole of the load, the second end of the second capacitance C2 is connected with the source of the first power frequency tube Q5 and the negative pole of the load, the first end of the sixteenth resistance R16 is connected with the sources of the second high-frequency tube Q4 and the second power frequency tube Q6, the second end is grounded, the first end of the seventeenth resistance R17 is connected with the pin 1 of the first half-bridge driving chip, the second end HO is connected with the eighteen R18 and the gate of the eighteen resistance R3, and the eighteen resistance R18, the first end of a nineteenth resistor R19 is connected with the LO1 pin of the first half-bridge driver chip, the second end of the nineteenth resistor R19 is connected with the first end of a twentieth resistor R20 and the gate of the second high-frequency tube Q4 respectively, the second end of the twentieth resistor R20 is grounded, the first end of a twenty-first resistor R21 is connected with the HO2 pin of the second half-bridge driver chip, the second end of the twenty-second resistor R22 is connected with the first end of the first power frequency tube Q5 respectively, the second end of a twenty-second resistor R22 is grounded, the first end of a twenty-third resistor R23 is connected with the LO2 pin of the second half-bridge driver chip, the second end of the twenty-fourth resistor R24 is connected with the first end of the second power frequency tube Q6 respectively, and the second end of the twenty-fourth resistor R24 is grounded.
One end of the full-bridge inverter circuit 500 is connected to a load, converts the dc voltage into an ac voltage, and supplies power to the load. The secondary protection is designed in the full-bridge inverter circuit, namely primary high-frequency tube current limiting and secondary power frequency tube current limiting, the high-frequency tube limits a small current signal in a sine wave half cycle, the power frequency tube limits a current signal in the upper half cycle or the lower half cycle of the sine wave, general overcurrent only needs to start the high-frequency tube for current limiting, and when the high-frequency tube is not limited, the power frequency tube is started for current limiting. The two-stage design of the power frequency pipe and the high-frequency pipe ensures that the current limiting is more accurate, the turn-off frequency of the power frequency pipe is reduced, the service life of the power frequency pipe is prolonged, the high-frequency pipe can select a model with smaller power, and the cost is saved.
The complete working process is as follows: the current sampling circuit 200 collects bus current in the full-bridge inverter circuit 500 in real time and sends the bus current to the power frequency tube current limiting circuit 10 and the high-frequency tube current limiting circuit 11, when the fact that instantaneous current is larger than the threshold value of the high-frequency tube current limiting circuit 11 is detected, the high-frequency tube current limiting circuit 11 sends a high-frequency tube overcurrent signal to the driving circuit 300, the driving circuit 300 stops sending a high-frequency tube driving waveform to the full-bridge inverter circuit 500 after receiving the high-frequency tube overcurrent signal, so that a high-frequency tube is closed, the high-frequency tube is protected, and after a high-frequency period (such as 50 microseconds) is cut off, the high-frequency tube driving signal is restarted; when the high-frequency tube is turned off, the bus current is continuously detected, when the instantaneous current is still larger than the power frequency tube current-limiting threshold value, the power frequency tube current-limiting circuit 10 sends a power frequency tube overcurrent signal to the driving module, and after the driving circuit 300 receives the power frequency tube overcurrent signal, the driving circuit stops sending a power frequency tube driving waveform to the full-bridge inverter circuit 500, so that the power frequency tube is closed, the power frequency tube is protected, and after the power frequency tube is turned off in a power frequency period (such as 20 milliseconds), the power frequency tube driving signal is restarted; when the instantaneous current is detected to be larger than the current-limiting threshold value of the power frequency tube, the current limiting of the power frequency tube is started, meanwhile, the overcurrent signal of the power frequency tube passes through the combined current-limiting circuit 12, the high-frequency tube current limiting is started (the time for limiting the current of the high-frequency tube can be set manually), because when the current limiting of the power frequency tube is triggered, if the driving signal of the high-frequency tube is not locked, the high-frequency tube is continuously opened and closed periodically, when the high-frequency tube is switched on, a loop is formed by the high-frequency tube, the inductive load and the power frequency upper tube, the energy stored by the inductive load is released, and the current of the loop does not pass through the sampling resistor at the negative end of the bus, so that the current is not limited, and the damage of the power frequency upper tube exceeding avalanche energy is easily caused.
The current-limiting threshold of the power frequency tube is generally set to be a little larger than that of the high-frequency tube, so that the load carrying capacity of inversion can be improved, and when general capacitive or inductive loads are carried, overcurrent chopping can be triggered in time to protect the power tube. The combined current limiting circuit 12 improves the capacity with inductive loads.
It should be noted that the above-described embodiments are merely illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the utility model, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the utility model as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (11)
1. A wave-by-wave current limiting circuit is characterized by comprising a power frequency tube current limiting circuit, a high-frequency tube current limiting circuit and a combined current limiting circuit;
the input end of the power frequency tube current limiting circuit is connected with the output end of the current sampling circuit, the current sampling circuit is used for sampling the current of the negative terminal of the bus, the output end of the power frequency tube current limiting circuit is connected with the driving circuit, the power frequency tube current limiting circuit is used for detecting whether the output current of the current sampling circuit is larger than a first preset current or not, and if the output current of the current sampling circuit is larger than the first preset current, a first overcurrent signal is sent to the driving circuit, so that the power frequency tube of the full-bridge inverter circuit is controlled to be turned off;
the input end of the high-frequency tube current limiting circuit is connected with the output end of the current sampling circuit, the output end of the high-frequency tube current limiting circuit is connected with the driving circuit, the high-frequency tube current limiting circuit is used for detecting whether the output current of the current sampling circuit is larger than a second preset current, and if the output current of the current sampling circuit is larger than the second preset current, a second overcurrent signal is sent to the driving circuit, so that the high-frequency tube of the full-bridge inverter circuit is controlled to be turned off;
the input end of the combined current limiting circuit is connected with the output end of the power frequency tube current limiting circuit, the output end of the combined current limiting circuit is connected with the output end of the high-frequency tube current limiting circuit, and when the combined current limiting circuit receives the first overcurrent signal, the combined current limiting circuit sends a third overcurrent signal to the driving circuit to control the high-frequency tube of the full-bridge inverter circuit to be switched off.
2. The current-limiting circuit according to claim 1, wherein the current-limiting circuit comprises: a first voltage comparison circuit and a first reference voltage supply circuit; the first input end of the first voltage comparison circuit is connected with the output end of the current sampling circuit, the second input end of the first voltage comparison circuit is connected with the output end of the first reference voltage providing circuit, and the output end of the first voltage comparison circuit is connected with the input end of the driving circuit.
3. The current-limiting circuit according to claim 1, wherein the high-frequency tube current-limiting circuit comprises: a second voltage comparison circuit and a second reference voltage supply circuit; the first input end of the second voltage comparison circuit is connected with the output end of the current sampling circuit, the second input end of the second voltage comparison circuit is connected with the output end of the second reference voltage providing circuit, and the output end of the second voltage comparison circuit is connected with the input end of the driving circuit.
4. The ripple-by-ripple current limit circuit of claim 1, wherein the joint current limit circuit comprises: the input end of the triode switch switching circuit is connected with the output end of the power frequency tube current limiting circuit, the output end of the triode switch switching circuit is connected with one end of the time delay circuit, and the other end of the time delay circuit is connected with the output end of the high-frequency tube current limiting circuit.
5. The ripple-through current limiting circuit of claim 2, wherein the first voltage comparison circuit comprises:
a fourth resistor and a first voltage comparator; the positive phase input end of the first voltage comparator is connected with the output end of the current sampling circuit, the negative phase input end of the first voltage comparator is connected with the output end of the first reference voltage providing circuit, the output end of the first voltage comparator is connected with the input end of the driving circuit, the first end of the fourth resistor is connected with the output end of the first voltage comparator, and the second end of the fourth resistor is connected with the second power supply.
6. The ripple-through current limiting circuit of claim 2, wherein the first reference voltage providing circuit comprises: a second resistor and a third resistor;
the first end of the second resistor is connected with the first end of the third resistor, the second end of the second resistor is connected with the first power supply, and the second end of the third resistor is grounded.
7. The ripple-through current limiting circuit of claim 3, wherein the second voltage comparison circuit comprises: a seventh resistor and a second voltage comparator;
the positive phase input end of the second voltage comparator is connected with the output end of the current sampling circuit, the negative phase input end of the second voltage comparator is connected with the output end of the second reference voltage providing circuit, the output end of the second voltage comparator is connected with the input end of the driving circuit, the first end of the seventh resistor is connected with the output end of the second voltage comparator, and the second end of the seventh resistor is connected with the fourth power supply.
8. The ripple-through current limiting circuit of claim 3, wherein the second reference voltage providing circuit comprises: a fifth resistor and a sixth resistor;
the first end of the fifth resistor is connected with the first end of the sixth resistor, the second end of the fifth resistor is connected with a third power supply, and the second end of the sixth resistor is grounded.
9. The ripple-through current limit circuit of claim 4, wherein the triode switch switching circuit comprises: the first PNP triode and the second NPN triode are connected with the first resistor and the second resistor respectively;
a first end of the eighth resistor is connected with the base of the first NPN transistor, a second end of the eighth resistor is grounded, an emitter of the first NPN transistor is grounded, a collector of the first NPN transistor is connected with a first end of the ninth resistor, and a second end of the ninth resistor is connected with a first end of the tenth resistor and the base of the first PNP transistor respectively; the second end of the tenth resistor is connected with a fifth power supply, the emitter of the first PNP tube is connected with the fifth power supply, the collector of the first PNP tube is respectively connected with the first end of the delay circuit and the driving circuit, and the second end of the delay circuit is grounded.
10. The ripple-through current limit circuit of claim 4, wherein the delay circuit comprises: an eleventh resistor, a first capacitor, a first diode;
the first end of the eleventh resistor is connected with the output end of the triode switch conversion circuit, the first end of the first capacitor and the anode of the first diode respectively, the second end of the eleventh resistor is grounded, the second end of the first capacitor is grounded, and the cathode of the first diode is connected with the driving circuit.
11. An electrical system comprising the ripple-by-ripple current limit circuit of any one of claims 1-10 and a current sampling circuit, wherein the current sampling circuit comprises: a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor and a first operational amplifier;
the first end of the twelfth resistor is connected with the first end of the bus negative terminal of the full-bridge inverter circuit, the second end of the twelfth resistor is connected with the first end of the thirteenth resistor and the inverting input end of the first operational amplifier respectively, the second end of the thirteenth resistor is connected with the output end of the first operational amplifier, the first end of the fourteenth resistor is connected with the second end of the bus negative terminal of the full-bridge inverter circuit, the second end of the fourteenth resistor is connected with the first end of the fifteenth resistor and the positive phase input end of the first operational amplifier respectively, the second end of the fifteenth resistor is grounded, and the output end of the first operational amplifier is further connected with the input end of the wave-chasing current-limiting circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120531309.9U CN215494755U (en) | 2021-03-12 | 2021-03-12 | Wave-by-wave current limiting circuit and power utilization system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120531309.9U CN215494755U (en) | 2021-03-12 | 2021-03-12 | Wave-by-wave current limiting circuit and power utilization system |
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| CN215494755U true CN215494755U (en) | 2022-01-11 |
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