CN215453114U - Video transmission board card and video transmission system - Google Patents
Video transmission board card and video transmission system Download PDFInfo
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- CN215453114U CN215453114U CN202121316039.6U CN202121316039U CN215453114U CN 215453114 U CN215453114 U CN 215453114U CN 202121316039 U CN202121316039 U CN 202121316039U CN 215453114 U CN215453114 U CN 215453114U
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Abstract
The utility model discloses a video transmission board card and a video transmission system. Wherein, the video transmission integrated circuit board includes: the device comprises a board card main body, wherein at least two target interfaces are arranged on the board card main body, each target interface comprises a plurality of pins, and each pin comprises at least one multiplexing pin; the video source processing chip is arranged on the board card main body, video transmission channels are arranged between the at least two target interfaces and the video source processing chip respectively, and the video transmission channels are used for transmitting video signals with preset resolution. The utility model solves the technical problem of poor mainboard reusability caused by non-uniform interface types of the 8K high-resolution video source in the related technology.
Description
Technical Field
The utility model relates to the technical field of display, in particular to a video transmission board card and a video transmission system.
Background
For the LED display industry, video input sources are continuously developing towards higher resolutions, and video input sources with high resolutions (for example, 8K or higher resolutions) gradually become the mainstream in the market, however, the types of decoding chips or loop-out chips of the video input sources with high resolutions are more, because the video decoding chips with high resolutions have different models and interfaces for different signal output forms, in order to adapt to different video decoding chips, the motherboard needs to be provided with interfaces of different types, different video decoding chips cannot multiplex the same motherboard, the flexibility of the motherboard is poor, and the motherboard needs to be redesigned for different video decoding chips, resulting in high development cost.
In view of the above problems, no effective solution has been proposed.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a video transmission board card and a video transmission system, which at least solve the technical problem of poor mainboard reusability caused by non-uniform interface types of 8K high-resolution video sources in the related technology.
According to an aspect of the embodiments of the present invention, there is provided a video transmission board, including: the device comprises a board card main body, wherein at least two target interfaces are arranged on the board card main body, each target interface comprises a plurality of pins, and each pin comprises at least one multiplexing pin; the video source processing chip is arranged on the board card main body, video transmission channels are arranged between the at least two target interfaces and the video source processing chip respectively, and the video transmission channels are used for transmitting video signals with preset resolution.
Furthermore, the preset resolution is greater than or equal to 8K resolution, and at least two target interfaces are connected with the same video source processing chip.
Further, the physical structure of the target interface is consistent with that of the m.2 interface, and the physical structure of the m.2 interface includes multiplexing pins.
Further, the multiplexing pins include at least 4 sets of differential signal transmission pins for minimum transmission.
Further, the differential signal transmission pin for minimum transmission includes a data signal pin for minimum transmission of a differential signal and a clock signal pin for minimum transmission of a differential signal.
Further, the multiplexing pin further comprises a control pin matched with the HDMI protocol, and the control pin comprises any one or more of a reset pin, a power supply pin, a configuration clock signal pin, a configuration data signal pin, a hot plug monitoring pin and a consumer electronics control pin.
Furthermore, the video transmission board card comprises a plurality of video source processing chips, the video source processing chips correspond to the target interfaces one by one, and each video source processing chip transmits video signals through the corresponding target interface.
Further, at least two target interfaces are sequentially arranged on the same side face of the board card main body.
According to another aspect of the embodiments of the present invention, there is also provided a video transmission system, including: the video transmission board card; the control mainboard is provided with a female seat matched with the target interface, and the female seat is internally provided with an electric connection contact point which is used for forming a transmission channel of a video signal with the target interface.
Furthermore, the target interface is a golden finger structure which is integrated with the board card main body and is provided with double-sided metal contacts, the female base further comprises a slot, the electric connection contacts are arranged in the slot, and when the video transmission board card is inserted into the slot through the golden finger structure, a transmission channel of video signals is formed between the main control chip and the video source processing chip.
In the embodiment of the utility model, at least two target interfaces are arranged on the board card main body, each target interface comprises at least one multiplexing pin, video transmission channels are respectively arranged between the at least two target interfaces and the video source processing chip, the video transmission channels are used for transmitting video signals with preset resolution, different transmission protocols can be customized for the multiplexing pins according to different video signals, the transmission of different types of video signals by using the same interface is realized, the problem that the mainboard needs to be redesigned by using different video source processing chips is avoided, on the other hand, the bandwidth of the interface is increased by expanding and using a plurality of target interfaces with multiplexing pins, the board card can be suitable for video signals with ultrahigh resolution of 8K and above, and further, the problem that the types of the interfaces of the 8K high-resolution video sources in the related technology are not uniform is solved, leading to the technical problem of poor reusability of the mainboard.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the utility model and together with the description serve to explain the utility model without limiting the utility model. In the drawings:
fig. 1 is a schematic diagram of a video transmission board according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an alternative target interface pin definition according to an embodiment of the utility model;
FIG. 3 is a schematic diagram of an alternative target interface pin definition according to an embodiment of the utility model;
fig. 4 is a schematic diagram of an alternative video transmission board according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an alternative video transmission system according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the utility model described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
According to an embodiment of the present invention, an embodiment of a video transmission board card is provided, and fig. 1 is a video transmission board card according to an embodiment of the present invention, as shown in fig. 1, the video transmission board card includes:
the integrated circuit board comprises a board card main body 100, wherein at least two target interfaces are arranged on the board card main body 100, each target interface comprises a plurality of pins 1011, and each pin comprises at least one multiplexing pin; the video source processing chip 102 is disposed on the board card main body 100, and video transmission channels are disposed between the at least two target interfaces and the video source processing chip 102, respectively, and the video transmission channels are used for transmitting video signals with preset resolution.
Fig. 1 illustrates a video transmission board by taking two target interfaces as an example, as shown in fig. 1, the two target interfaces are a first target interface 101a and a second target interface 101b, a first video transmission channel 103a is disposed between the first target interface 101a and the video source processing chip 102, and a second video transmission channel 103b is disposed between the second target interface 101b and the video source processing chip 102, so that video signals output by the video source processing chip 102 can be transmitted through the first target interface 101a and the second target interface 101b simultaneously.
The multiplexing pin supports transmission of video signals of different transmission protocols, specifically, hardware of the multiplexing pin can support transmission of video signals output by different video source processing chips, and transmission of any video signal can be realized by customizing a protocol or specification used for video signal transmission to the multiplexing pin. For example, for an 8K resolution video source with ultrahigh resolution, different manufacturers or different types of video source processing chips may support different transmission protocols for the 8K resolution video signals output by the video source processing chips, and the multiplexing pins may be customized to support an HDMI (High Definition Multimedia Interface) transmission protocol or a dp (display port) transmission protocol, so that the 8K resolution video signals output by the different types of video source processing chips may all be transmitted through the same Interface.
The number of the multiplexing pins is determined by a self-defined transmission protocol, and the number of the multiplexing pins required by different transmission protocols is different, for example, the plurality of pins may include 75 pins, and when the transmission protocol supported by the video source processing chip is the HDMI protocol, any 19 pins may be selected from the 75 pins as the multiplexing pins, and the multiplexing pins are self-defined according to the HDMI protocol; when the transmission protocol supported by the video source processing chip is the DP protocol, 20 arbitrary pins can be selected from 75 pins as multiplexing pins, and the multiplexing pins are customized according to the DP protocol.
The video source processing chip can be a video source decoding chip or a video source loop-out chip. The video transmission board card can be a daughter card with a video source decoding chip or a video source loop-out chip.
The at least two target interfaces may be interfaces with the same physical structure (e.g., with the same number of pins) or interfaces with different physical structures. It should be noted that at least two target interfaces are arranged on the board card main body, and the video source processing chip and the at least two target interfaces are connected through the plurality of video transmission channels, so that the target interfaces are expanded, and further, the bandwidth of the interfaces can be increased, so that the video transmission board card can realize the transmission of video signals with any resolution. Under the condition that at least two target interfaces adopt the same physical structure, the types of electronic components in the video transmission board card (for example, the types of the used interfaces) can be reduced, and the cost of the video transmission board card can be further reduced.
In addition, when at least two target interfaces adopt the same physical structure, different protocol definitions may be performed on the pins of each target interface, that is, the number of multiplexing pins actually used by different target interfaces may be different, for example, the plurality of pins may include 75 pins, one target interface may select any 19 pins from the 75 pins as the multiplexing pins, and the other target interface may select any 29 pins from the 75 pins as the multiplexing pins.
The preset resolution may be any resolution, for example, any one of a 2K resolution, a 4K resolution, and an 8K resolution, and the at least two target interfaces may be respectively and independently used for transmitting the video signal with any resolution, or may be used in combination to transmit the sub-signal obtained by splitting the video signal.
In an optional embodiment, the preset resolution is greater than or equal to 8K resolution, and at least two target interfaces are connected to the same video source processing chip.
The 8K resolution is a resolution of 7680 × 4320 pixels, and the preset resolution may be any ultrahigh resolution greater than 8K resolution, for example, 12K resolution or 16K resolution. Since the bandwidth required by the video signal with the resolution of 8K or more is relatively large, and the requirement on the interface bandwidth is relatively high, in order to improve the versatility and compatibility of the target interface in this embodiment, the target interface with the same hardware structure (for example, with the same number of pins) may be used, and it is difficult to ensure that the bandwidth of a single target interface meets the requirements of the video signal with all resolutions. Therefore, the interface bandwidth of the video transmission board card can be increased by expanding the number of the target interfaces so as to adapt to application with higher resolution.
Specifically, the video source processing chip can output video signals with resolutions of 8K and above, at least two target interfaces are connected with the same video source processing chip, and video transmission channels are respectively arranged between the video source processing chip and each target interface, and each target interface is respectively used for transmitting sub-signals obtained by splitting the video signals with resolutions of 8K and above, for example, as shown in fig. 1, the video source processing chip 102 can be 1 video source decoding chip with resolutions of 8K and can output video signals with resolutions of 8K, because the video signals with resolutions of 8K need larger bandwidth, the video source decoding chip can split the video signals with resolutions of 8K into two sub-signals, specifically, the two sub-signals are respectively transmitted through the first target interface 101a via the video transmission channel 103a and through the second target interface 101b via the video transmission channel 103b, after the control main board receives the two paths of sub signals, the two paths of sub signals can be merged and restored to be original video signals.
It should be noted that each of the split sub-signals may have equal data size or unequal data size, that is, the actually used bandwidths of different target interfaces corresponding to each of the sub-signals may be unequal, which is specifically determined according to the pin customization condition of each target interface by the user.
In an alternative embodiment, the at least two target interfaces are sequentially arranged on the same side surface of the board main body. As shown in fig. 1, the first target interface 101a and the second target interface 101b are arranged on the same side surface of the board main body, so that the video transmission board can use the side surface as a connection surface with the control main board, which is convenient for connecting a plurality of target interfaces with the control main board at the same time.
In this embodiment, at least two target interfaces are arranged on the board card main body, the target interfaces include at least one multiplexing pin, and a plurality of video transmission channels are arranged between the video source processing chip and at least two target interfaces, the video transmission channels are used for transmitting video signals with preset resolution, and according to different video signals, different transmission protocols are defined by the multiplexing pins, so that different types of video signals are transmitted by using the same interface, the problem that a mainboard needs to be redesigned by using different video source processing chips is avoided, on the other hand, by expanding and using a plurality of target interfaces with multiplexing pins, the bandwidth of the interfaces is increased, the method can be suitable for video signals with ultrahigh resolution of 8K and above, and the technical problem of poor mainboard reusability caused by non-uniform interface types of the 8K high-resolution video source in the related technology is solved.
As an alternative embodiment, the target interface is consistent with the physical structure of the m.2 interface, which includes multiplexing pins.
The physical structure comprises hardware structures such as pin positions, the number and the size of the M.2 interface, the number and the position of gaps, and the like, a target interface of the video transmission board card is consistent with the physical structure of the M.2 interface, but the definition of each pin is different from that of the M.2 interface so as to support a data protocol type different from that of the M.2 interface.
The m.2 interface (original NGFF interface) is a new interface specification replacing the mSATA interface, has strong transmission performance, is mainly used as a transmission interface of a super local solid state disk at present, and can support multiple transmission protocols, such as SATA, PCLe, USB, HSIC, and the like. However, the protocol type supported by the m.2 interface does not include a transmission protocol (e.g., HDMI transmission protocol) required by the video decoding chip, and the m.2 interface cannot be directly applied to an interface in the field of video source processing, in the present application, a plurality of target interfaces consistent with the physical structure of the m.2 interface are used to perform a custom protocol on each pin of the target interface, so as to implement transmission of an ultra-high resolution video signal, and the m.2 interface is a host interface in the field of computers, and has a lower cost when purchasing in a large batch.
Specifically, in the hardware structure of the m.2 interface, a gap is formed by missing a pin at a designated position, and the missing pin is defined as a key position, which is used for identifying the data protocol type supported by the m.2 interface. The target interface in the present application is consistent with the hardware structure of the m.2 interface, that is, a key structure consistent with the m.2 interface may be adopted, as shown in fig. 1, a pin at a designated position in the target interface is missing to form a notch 1012, and the pin constituting the notch 1012 may be any one or more pins of a plurality of pins. The at least two target interfaces may use the same key, that is, the pins in the same position are missing, for example, the first target interface 101a lacks the 8 th pin to the 15 th pin, and the second target interface 101b also lacks the 8 th pin to the 15 th pin.
The hardware structure of the m.2 interface can be divided into 12 types according to the difference of key positions, the missing pins in this embodiment can be consistent with the key positions of the m.2 interface, specifically, the multiple pins of the video transmission board card include 75 pins, wherein the pin at the designated position is any one of the following pins: 8 th pin to 15 th pin; and 12 th to 19 th pins; and 16 th to 23 th pins; and 20 th pin to 27 th pin; and 24 th to 31 th pins; and 28 th pin to 35 th pin; and 39 th through 46 th pins; and 43 rd to 50 th pins; and 47 th to 54 th pins; and 51 st pin to 58 th pin; and 55 th to 62 th pins; and 59 th to 66 th pins. In an alternative embodiment, the pins at the designated location include at least one set of a predetermined number of consecutive pins to form at least one corresponding notch at the designated location. For example, for a target interface of a video transmission board card with 75 pins, the pins at the designated positions may be from 8 th pin to 15 th pin, so that the interface of the video transmission board card lacks from 8 th pin to 15 th pin, and a notch 1012 as shown in fig. 1 is formed at the position from 8 th pin to 15 th pin. The pins at the designated positions may also include two groups of consecutive pins with a preset number, for example, the pins at the designated positions may be the 8 th pin to the 15 th pin, and the 59 th pin to the 66 th pin, so that the interface of the video transmission board card lacks the 8 th pin to the 15 th pin, and the 59 th pin to the 66 th pin, and two notches are formed at corresponding positions.
It should be noted that the number of pins actually used for video signal transmission in the video transmission board card should be the number of pins minus the pin data corresponding to the notch, and the pin at the designated position is missing, and only plays a role of identification, and does not actually participate in the transmission of the video signal. For example, for a target interface of a video transmission board card with 75 pins, the pins in the designated positions may be from 8 th pin to 15 th pin, and the number of the pins actually used for video signal transmission is 67 pins. The multiplexing pins may be disposed on any side of the notch or distributed on two sides of the notch, for example, the pins at the designated positions are the 8 th pin to the 15 th pin, and the multiplexing pins may be the 17 th to 40 th pins, or the 1 st to 7 th and the 16 th to 33 th pins, and the positions of the multiplexing pins may be customized, which is not limited herein.
For example, when a video source processing chip of the video transmission board outputs a video signal of 8K @30 (i.e. 8K resolution \30fps), a bandwidth supported by a physical structure of 1 m.2 interface cannot meet the requirement of transmission of the 8K video signal, two target interfaces consistent with the physical structure of the m.2 interface may be sequentially arranged on the video transmission board, the two target interfaces are a first target interface U26 and a second target interface U27, and the first target interface and the second target interface are respectively used for transmitting two sub-signals obtained by splitting the 8K @30 video signal, so as to meet the requirement of the 8K @30 video signal on the transmission bandwidth. Specifically, the pins of the target interface may be defined according to an HDMI transmission protocol, and fig. 2 is a schematic diagram of an optional pin definition of the target interface according to an embodiment of the present invention, as shown in fig. 2, the first target interface U26 may adopt the definitions of the pins in fig. 2, so as to implement transmission of the first sub-signal (represented by an HDMI1 signal) obtained by splitting the 8K @30 video signal. The physical structure of the first target interface U26 is consistent with that of the m.2 interface, and each of the first target interface U26 has 75 pins, and the 8 th pin to the 15 th pin are missing to form key positions consistent with that of the m.2 interface, table 1 is a pin definition of an optional first target interface according to the embodiment of the present application, and the definition of 75 pins may be as shown in table 1, corresponding to 8K video signals:
TABLE 1
Fig. 3 is a schematic diagram of pin definitions of an optional target interface according to an embodiment of the present invention, as shown in fig. 3, a second target interface U27 may adopt the definitions of pins in fig. 3 to implement transmission of a second sub-signal obtained by splitting an 8K @30 video signal (represented by an HDMI2 signal), the second target interface U27 is consistent with the physical structure of an m.2 interface and is consistent with the physical structure of a first target interface U26, that is, has 75 pins, an 8 th pin to a 15 th pin are missing to form a key bit consistent with an m.2 interface, table 2 is a pin definition of an optional second target interface according to an embodiment of the present application, corresponding to an 8K video signal, and the definition of 75 pins of the second target interface is shown in table 2:
TABLE 2
As shown in table 1 and table 2, the first target interface U26 and the second target interface U27 have the same number of pins and the same notch position, but the definition of each pin may be different, the first target interface U26 actually defines 28 pins to support the HDMI transport protocol, and the second target interface U27 actually defines 19 pins to support the HDMI transport protocol.
In an alternative embodiment, the multiplexing pins include at least 4 sets of differential signal transmission pins for minimum transmission.
The Differential signal transmission pins for minimum transmission are tmds (transition Minimized Differential signal) signal transmission pins. The target interface may include 4 sets of differential signal transmission pins for minimum transmission according to the HDMI transmission protocol definition, as shown in fig. 2 and table 1, and the pins 31, 33, 39, 41, 47, 49, 55, and 57 of the first target interface U26 are the above-mentioned differential signal transmission pins for minimum transmission. As shown in fig. 3 and table 2, the pins 31, 33, 39, 41, 47, 49, 55 and 57 of the second target interface U27 are the above-mentioned transition minimized differential signaling pins for transmitting TMDS signals.
In an alternative embodiment, the differential signal transmission pins for minimum transmission include a data signal pin for minimum transmission of differential signals and a clock signal pin for minimum transmission of differential signals.
Specifically, as shown in fig. 2 and table 1, the pins 31, 33, 39, 41, 47, and 49 of the first target interface U26 are defined as HDMI1_ TXn _ P and HDMI1_ TXn _ N (where N takes any one of values 0, 1, and 2), and represent a pair of minimum transmission differential signals for transmitting the video data (i.e., the actual video data signal) of the split first sub-signal HDMI1, and the pins 55 and 57 are defined as HDMI1_ TXC _ P and HDMI1_ TXC _ N, and represent the clock signals corresponding to the minimum transmission differential signals; as shown in fig. 3 and table 2, the pins 31, 33, 39, 41, 47, and 49 of the second target interface U27 are defined as HDMI2_ TXn _ P and HDMI2_ TXn _ N (where N takes any one of values 0, 1, and 2) and represent a pair of minimum transmission differential signals for transmitting the video data of the split second sub-signal HDMI2, and the pins 55 and 57 are defined as HDMI2_ TXC _ P and HDMI2_ TXC _ N and represent clock signals corresponding to the minimum transmission differential signals.
As an optional embodiment, the multiplexing pin further includes a control pin matching with the HDMI protocol, and the control pin includes any one or more of a reset pin, a power supply pin, a configuration clock signal pin, a configuration data signal pin, a hot plug monitoring pin, and a consumer electronics control pin.
Each pin of the target interface further comprises a control pin matched with the HDMI protocol, so that the target interface supports the HDMI transmission protocol, and TMDS signals are transmitted. The same control pins of the first destination interface U26 and the second destination interface U27 are defined by the same reference numerals and have the same meaning, and only the control pin of the first destination interface U26 will be described below as an example.
As shown in fig. 2 and table 1, pin 1 of the first target interface U26 is a reset pin (HDMI _ CON _ SYSRSTn) for resetting the first target interface U26 of the video transmission board; pins 2, 4 and 6 are all power supply pins (VCC5.0), and VCC5.0 is used for providing a 5V power supply; pins 71 and 50 are hot plug monitor pins for monitoring whether TMDS signals are transmitted, where the pin 71(HDMI1_ FPGA _ CON _ HPD) is a hot plug monitor pin corresponding to a main control chip (such as FPGA) of the control motherboard, and the pin 50(HDMI1_ MCU _ CON _ HPD) is a hot plug monitor pin corresponding to a video source decoding chip; the pins 63 and 46 are both configuration clock signal pins, where the pin 63(HDMI1_ FPGA _ DDC _ SCL) is a configuration clock signal pin corresponding to a main control chip (such as FPGA) of the control motherboard, and the pin 46(HDMI1_ MCU _ DDC _ SCL) is a configuration clock signal corresponding to a video source decoding chip; the pins 64 and 48 are both configuration data signal pins, where the pin 64(HDMI1_ FPGA _ DDC _ SDA) is a configuration data signal pin corresponding to a main control chip (such as FPGA) controlling the motherboard, and the pin 48(HDMI1_ MCU _ DDC _ SDA) is a configuration data signal pin corresponding to a video source decoding chip; pin 38 is the digital audio output pin (7672_ a0_ SPDIF); pin 40 is a consumer electronics control pin (HDMI _ CEC); pin 38(7672_ a0_ SPDIF) is a digital audio output pin.
In addition to the definition of the control pin matched with the HDMI protocol, the control pin may further include a plurality of pins of a custom protocol according to different transmission protocols, for assisting transmission of video signals. Specifically, as shown in fig. 2 and table 1, the control pins may further include pins 3, 5, 7, 56, and 58, where pin 3(Board _ ID) is used to transmit identification signals of different video transmission boards, pin 5(MCU _ INT1n) and pin 7(MCU _ INT2n) are used to transmit interrupt signals of the video source processing chip, pin 56(UART1_ TX) is an asynchronous serial transmission control pin, and pin 58(UART1_ RX) is an asynchronous serial reception control pin.
It should be noted that the control pin may be defined as any pin of a plurality of pins, and different definition rules may be provided according to different video signals or different transmission protocols, which is not limited herein.
As an optional embodiment, the video transmission board card includes a plurality of video source processing chips, the video source processing chips correspond to the target interfaces one to one, and each video source processing chip transmits a video signal through the corresponding target interface.
The at least two target interfaces can be used for transmitting video signals output by the same video source processing chip and can also be used for independently transmitting video signals output by different video source processing chips. Fig. 4 is a schematic diagram of an optional video transmission board according to an embodiment of the present invention, as shown in fig. 4, the video transmission board includes a video source processing chip 401 and a video source processing chip 402, the two video source processing chips are responsible for outputting respective video signals, for example, both the video source processing chip 401 and the video source processing chip 402 can output video signals with a resolution of 4K, target interfaces are a first target interface 403a and a second target interface 403b, the video source processing chip 401 corresponds to the first target interface 403a, the video signal output by the video source processing chip 401 is transmitted through a video transmission channel 404a, the video source processing chip 402 corresponds to the second target interface 403b, and the video signal output by the video source processing chip 402 is transmitted through a video transmission channel 404 b.
Through with a plurality of target interfaces and a plurality of video source processing chip one-to-one for the video transmission integrated circuit board that has a plurality of video source processing chips can use and unify the transmission that carries out video signal between standardized target interface and the mainboard, avoids different frequency source processing chips to need to use different interfaces, leads to the problem that the interface on the mainboard can not multiplex.
Example 2
According to another aspect of the embodiments of the present invention, there is also provided a video transmission system, and fig. 5 is a video transmission system according to an embodiment of the present invention, and as shown in fig. 5, the video transmission system includes: the video transmission board 501; the control main board 502 with the main control chip 5021 is provided with a female socket matched with a target interface on the control main board 502, and the female socket is internally provided with an electric connection contact point which is used for forming a transmission channel of a video signal with the target interface.
The target interfaces are matched with the female socket, specifically, the number of the target interfaces is matched with the number of the female socket, and the number and definition of pins of the target interfaces are matched with the number and definition of the electric connection contact points in the female socket, so that the female socket and the target interfaces support the same transmission protocol. For example, as shown in fig. 5, the target interfaces are a first target interface 5012a and a second target interface 5012b, the control motherboard 502 has a female socket 5022 matched with the first target interface 5012a and a female socket 5023 matched with the second target interface 5012b, so that the video transmission board 501 is plugged into the control motherboard 502 through the 2 target interfaces to realize the transmission of video signals.
The main control chip can be an FPGA chip for video signal processing, the video transmission board card can be a daughter card with a video source decoding chip or a video source loop-out chip, the daughter card is electrically connected with a slot on the control mainboard through an interface formed by a plurality of pins, and transmission of video signals between the FPGA chip and the daughter card chip 5011 (for example, the video source decoding chip or the video source loop-out chip) is achieved.
As an optional embodiment, the target interface is a gold finger structure integrated with the board card main body and having a double-sided metal contact, the female base further includes a slot, the electrical connection contact is disposed in the slot, and when the video transmission board card is inserted into the slot through the gold finger structure, a transmission channel of the video signal is formed between the main control chip and the video source processing chip.
The plurality of pins in the target interface are gold finger structures, as shown in fig. 1, pads of the gold finger structures and the board card main body 100 are integrated, and the pads of the gold finger structures may be disposed on two sides of the board card main body 100 under the condition that the number of the pins is large.
The target interface and the board main body are of an integrated structure, and the target interface can adopt a physical structure of an M.2 interface, so that a video transmission board as a daughter card has a uniform interface, when a video source processing chip is changed, only the transmission protocol of the target interface needs to be customized again, the physical structure does not need to be changed, the interface structure on the control mainboard does not need to be redesigned, and the multiplexing of the interface on the control mainboard is realized. When the video source processing chip outputs video signals with the resolution of 8K or above, the transmission of the video signals with the ultrahigh resolution is realized by expanding the number of the target interfaces.
In an alternative embodiment, the target interface adopts a physical structure of an m.2 interface, the pin missing at the designated position of the target interface forms a notch, and the slot of the female socket has a transition structure matched with the notch of the target interface, and the transition structure is used for forming a plug-in space matched with the notch between adjacent electrical connection contact points. Because the notch of the video transmission board card is formed by the missing pins, the transition structure in the female seat does not have an electric connection contact point so as to correspond to the missing pins, and the transition structure can also be used for indicating the transmission protocol type of the video signal. Specifically, the transition structure may further be a protruding structure matched with the notch, so that after the video transmission board card is inserted into the slot of the control main board, the protruding structure is matched with the space in the notch, and when the transmission protocol supported by the interface of the video transmission board card is inconsistent with the transmission protocol supported by the interface of the control main board, the notch and the protruding structure cannot be inserted, thereby avoiding misoperation.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A video transmission board card, comprising:
the device comprises a board card main body, wherein at least two target interfaces are arranged on the board card main body, each target interface comprises a plurality of pins, and each pin comprises at least one multiplexing pin;
the video source processing chip is arranged on the board card main body, video transmission channels are arranged between the at least two target interfaces and the video source processing chip respectively, and the video transmission channels are used for transmitting video signals with preset resolution.
2. The video transmission board card of claim 1, wherein the preset resolution is greater than or equal to 8K resolution, and the at least two target interfaces are connected to a same video source processing chip.
3. The video transmission board of claim 1, wherein the destination interface is consistent with a physical structure of an m.2 interface, the physical structure of the m.2 interface including the multiplexing pin.
4. The video transmission board of claim 3, wherein the multiplexing pins comprise at least 4 sets of differential signal transmission pins for minimized transmission.
5. The video transmission board card of claim 4, wherein the differential signal transmission minimization pins comprise a data signal minimization pin and a clock signal minimization pin for differential signal transmission.
6. The video transmission board of claim 4, wherein the multiplexing pin further comprises a control pin matching an HDMI protocol, and the control pin comprises any one or more of a reset pin, a power pin, a configuration clock signal pin, a configuration data signal pin, a hot plug monitor pin, and a consumer electronics control pin.
7. The video transmission board card of claim 1, wherein the video transmission board card comprises a plurality of video source processing chips, the video source processing chips are in one-to-one correspondence with the target interfaces, and each video source processing chip transmits video signals through the corresponding target interface.
8. The video transmission board of claim 1, wherein the at least two target interfaces are sequentially arranged on a same side of the board body.
9. A video transmission system, comprising:
the video transmission board of any one of claims 1-8;
the control mainboard is provided with a master control chip, the control mainboard is provided with a female seat matched with the target interface, an electric connection contact point is arranged in the female seat, and the electric connection contact point is used for forming a transmission channel of the video signal with the target interface.
10. The video transmission system according to claim 9,
the target interface be with integrated into one piece of integrated circuit board main part and have the golden finger structure of two-sided metal contact, female seat still includes the slot, the electric connection contact point set up in the slot, work as the video transmission integrated circuit board passes through the golden finger structure inserts during the slot main control chip with form between the video source processing chip video signal's transmission path.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121316039.6U CN215453114U (en) | 2021-06-11 | 2021-06-11 | Video transmission board card and video transmission system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121316039.6U CN215453114U (en) | 2021-06-11 | 2021-06-11 | Video transmission board card and video transmission system |
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| CN215453114U true CN215453114U (en) | 2022-01-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114666415A (en) * | 2022-05-16 | 2022-06-24 | 宏晶微电子科技股份有限公司 | Data transmission method, display device and control device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114666415A (en) * | 2022-05-16 | 2022-06-24 | 宏晶微电子科技股份有限公司 | Data transmission method, display device and control device |
| CN114666415B (en) * | 2022-05-16 | 2022-09-09 | 宏晶微电子科技股份有限公司 | Data transmission method, display device and control device |
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