CN215451386U - Semiconductor package - Google Patents

Abstract

The present invention relates to a semiconductor package. According to an embodiment of the present invention, a semiconductor package includes: a substrate having a first surface; a semiconductor die coupled to the first surface of the substrate; a first insulating material covering the semiconductor die and at least a portion of the first surface of the substrate, wherein the first insulating material includes a first recess located over the semiconductor die; and a second insulating material located in the first groove, wherein an elastic modulus of the second insulating material is lower than an elastic modulus of the first insulating material.

Description

Semiconductor package

Technical Field

The present invention relates generally to semiconductor packaging technology, and more particularly to semiconductor packages including hybrid modulus blocks.

Background

In the prior art, semiconductor packages are typically subjected to various tests to verify that the design and manufacturing requirements are met prior to assembly to a PCB board, including package strain testing. As package sizes continue to decrease, package strain tests for small size packages become more stringent. For example, in some types of semiconductor packages, it is generally desirable in the art for the top mold clearance (top mold clearance) to be less than 130 μm on the die. However, a smaller thickness of the molding compound on the die means a smaller Minimum Strain (Minimum Strain) allowed, and thus a greater difficulty in passing the package Strain test. Thus, none of the existing single component molded packages can meet the stringent minimum strain requirements (e.g., minimum strain values of no less than 7000 μ ε) when an over-die molding compound thickness of less than 130 μm is required.

In view of the strong correlation between package strain and elastic modulus (hereinafter referred to as "modulus") and fracture toughness of molding compounds, some prior arts propose technical solutions for improving package strain (for example, decreasing modulus and increasing fracture toughness) by adjusting modulus and fracture toughness of molding compounds. However, adjusting the modulus and fracture toughness of the molding compound may indirectly result in the package not meeting other product requirements, such as substrate warpage, manufacturability, and Board Level Reliability (BLR). In other words, the semiconductor package using a single molding compound cannot satisfy all the requirements at the same time, and is often lost.

In view of the above, there is a strong need in the art to provide improved solutions to the above-mentioned problems.

SUMMERY OF THE UTILITY MODEL

The present disclosure provides a semiconductor package structure including a high modulus block and a low modulus block.

According to an embodiment of the present invention, there is provided a semiconductor package, including: a substrate having a first surface; a semiconductor die coupled to the first surface of the substrate; a first insulating material covering the semiconductor die and at least a portion of the first surface of the substrate, wherein the first insulating material includes a first recess located over the semiconductor die; and a second insulating material located in the first groove, wherein an elastic modulus of the second insulating material is lower than an elastic modulus of the first insulating material.

According to another embodiment of the present invention, the second insulating material in the semiconductor package is centered on top of the first insulating material.

According to another embodiment of the present invention, a top surface of the first insulating material in a semiconductor package is coplanar with a top surface of the second insulating material.

According to another embodiment of the present invention, the first recess in the semiconductor package has one or more rounded corners.

According to another embodiment of the present invention, the first insulating material in the semiconductor package includes a second recess located above the semiconductor die and separated from the first recess.

According to another embodiment of the present invention, the first insulating material in the semiconductor package includes a third recess located over the semiconductor die and separated from the first recess and the second recess, wherein the second recess and the third recess are located on both sides of the first recess, respectively.

According to another embodiment of the present invention, the second groove and the third groove in the semiconductor package are symmetrical with respect to the first groove.

According to another embodiment of the present invention, each of the first insulating material and the second insulating material in a semiconductor package includes a resin, a hardener, and a filler.

According to another embodiment of the present invention, the first insulating material and the second insulating material in the semiconductor package include the same resin and the same hardener.

According to another embodiment of the present invention, the filler content of the first insulating material in the semiconductor package is higher than the filler content of the second insulating material.

Additional aspects and advantages of embodiments of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of the utility model.

Drawings

Fig. 1 shows a schematic diagram of a semiconductor package in the prior art.

Fig. 2 is a diagram illustrating a prior art package strain test performed on a semiconductor package.

Fig. 3 is a schematic diagram of a semiconductor package according to an embodiment of the utility model.

Fig. 4A shows a top view of the semiconductor package structure shown in fig. 3.

Fig. 4B shows a top view of a semiconductor package structure similar to fig. 4A.

Fig. 5 is a schematic diagram of a semiconductor package according to another embodiment of the utility model.

Fig. 6A shows a top view of the semiconductor package structure shown in fig. 5.

Fig. 6B shows a top view of a semiconductor package structure similar to fig. 6A.

Fig. 7 shows a detailed structural diagram of a semiconductor package according to an embodiment of the utility model.

Fig. 8 is a schematic structural diagram of a semiconductor package according to another embodiment of the present invention.

Fig. 9A to 9D illustrate method steps for forming the semiconductor package structure shown in fig. 3 according to an embodiment of the present invention.

Detailed Description

In order that the spirit of the utility model may be better understood, some preferred embodiments of the utility model are described below.

The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the utility model be constructed or operated in a particular orientation.

Various embodiments of the utility model are discussed in detail below. While specific implementations are discussed, it should be understood that these implementations are for illustrative purposes only. A person skilled in the relevant art will recognize that other components and configurations may be used without parting from the spirit and scope of the utility model.

Fig. 1 shows a schematic diagram of a semiconductor package in the prior art. As shown in fig. 1, in a semiconductor package (10), a semiconductor die (101) is formed over a substrate (100) and coupled to an upper surface of the substrate (100). It should be understood that semiconductor die (101) may include a stack of dies and may be wire bonded to an upper surface (not shown) of substrate (100) via a number of wires. A molding material (102) is positioned over the substrate (100) encapsulating the semiconductor die (101) and the conductive lines (not shown) and covering a portion of the upper surface of the substrate (100). As an embodiment, a plurality of conductive solder balls (103) may be further formed on the lower surface of the substrate (100) to electrically connect the semiconductor package (10) with an external device. The molding material (102) shown in fig. 1 has a single composition, and when the thickness of the molding material over the semiconductor die (101) is reduced, no matter how its composition is adjusted, it cannot simultaneously satisfy various requirements such as package strain, substrate warpage, manufacturability, and board level reliability.

Fig. 2 is a diagram illustrating a prior art package strain test performed on a semiconductor package. As shown in fig. 2, the semiconductor package (200) is mounted upside down on the test stand (201) after the package is completed, so that the stress gauge (203) performs a package strain test against the surface of the semiconductor package (200). In the package strain test process, the probe (202) gradually applies pressure to the semiconductor package (200) from top to bottom, the stress meter (203) acquires strain values from the surface of the semiconductor package (200) in real time to acquire the minimum strain of the semiconductor package (200), and then whether the semiconductor package (200) can meet the minimum strain requirement is judged (for example, the minimum strain value is not less than 7000 mu epsilon). It should be understood that the semiconductor package under test 200 may include internal structures similar to the semiconductor package 10 shown in fig. 1, and thus, will not be described in detail herein.

In the package strain test shown in fig. 2, it is difficult for the prior art single component molded packages to meet the minimum strain requirement, and particularly, none of the prior art packages can meet the severe minimum strain requirement (e.g., the minimum strain value is not less than 7000 μ s) when the thickness of the plastic on the die of the single component molded package is less than 130 μm.

Fig. 3 is a schematic diagram of a semiconductor package according to an embodiment of the utility model. As shown in fig. 3, in a semiconductor package (30), a semiconductor die (301) is formed over a substrate (300) and coupled to a first surface of the substrate (300). It should be understood that the semiconductor die (301) may include a stack of dies and may be wire bonded to an upper surface (not shown) of the substrate (300) via a number of wires. A first insulating molding material (302) is located over the substrate (300) encapsulating the semiconductor die (301) and the conductive lines (not shown) and covering a portion of the upper surface of the substrate (300). It should still be understood that a number of conductive solder balls (not shown) may be further formed on the lower surface of the substrate (300) to enable electrical connection of the semiconductor package (30) with external devices.

Still referring to fig. 3, in the semiconductor package (30), the first insulating molding material (302) further includes a groove (302'), and the second insulating molding material (303) is formed in the groove (302'). Wherein the molding compound used to form the first insulating molding material (302) has a higher modulus, and the molding compound used to form the second insulating molding material (303) has a lower modulus relative to the molding compound of the first insulating molding material (302). In other words, the second insulating molding material (303) having a lower modulus is embedded in the top groove of the first insulating molding material (302) having a higher modulus. The first insulating molding material (302) may be referred to as a high modulus block and the second insulating molding material (303) may be referred to as a low modulus block.

When subjected to a strain test such as that shown in fig. 2, the semiconductor package (30) is mounted upside down on a test stand (201) and a strain gauge (203) in a form similar to that of the semiconductor package (200) of fig. 2. At this time, it is the second insulating molding material (303) that comes into direct contact with the strain gauge (203) instead of the first insulating molding material (302). Therefore, the second insulating molding material (303) having a low modulus can effectively absorb stress applied to the semiconductor package (30) by the probe (202), thereby enhancing package strain of the semiconductor package.

In one embodiment, the top surface of the first insulating molding material (302) is coplanar with the top surface of the second insulating molding material (303) to make the top surface of the semiconductor package (30) flat and aesthetically pleasing. However, depending on the actual process or other factors, it may also be permissible for the top surface of the first insulating molding material (302) to be offset from the top surface of the second insulating molding material (303) rather than coplanar, which does not affect the package strain of the semiconductor package (30) to be enhanced. In another embodiment, the bottom surface of the second insulating molding material (303) may further include rounded corners instead of the sharp corners as shown in fig. 3, so that the second insulating molding material (303) sufficiently and smoothly fills the groove (302').

The material components of the first insulating molding material (302) and the second insulating molding material (303) each contain, for example, a resin, a hardener, and a filler. To achieve a lower modulus, one can simply reduce the filler content without changing the resin and hardener content. That is, the first insulating molding material (302) and the second insulating molding material (303) differ only in material composition in that the second insulating molding material (303) contains relatively less filler, and the resin and hardener contents of the two can be identical, which not only simplifies the process and reduces the cost, but also can avoid a series of problems of CTE mismatch, adhesion, and delamination that may occur during thermal testing. It should be understood that the particular molding compound components required may be co-developed with the molding compound supplier, or the Design and adjustment of the molding compound components may be conveniently made by Design of experiment (DOE) according to the supplier's recipe, provided that it is ensured that the modulus of the second insulating molding material (303) is sufficiently low to meet the minimum strain requirement.

Fig. 4A shows a top view of the semiconductor package structure shown in fig. 3. As shown in fig. 4A, a first insulating molding material (402) having a higher modulus has a second insulating molding material (403) having a lower modulus embedded therein. It can be seen that the second insulating molding material (403) is embedded in the first insulating molding material (402) in a single body and is located substantially in the middle of the top surface of the first insulating molding material (402). As an example, the second insulating molding material (403) may be centrally located on top of the first insulating molding material (402) so as to be in direct contact with a strain gauge used for testing, such as the strain gauge (203) shown in fig. 2.

Fig. 4B shows a top view of a semiconductor package structure similar to fig. 4A except that the second insulating molding material (403) embedded in the first insulating molding material (402) of fig. 4B includes rounded corners, instead of the sharp corners as shown in fig. 4A, from a top view, so that the second insulating molding material (303) sufficiently and smoothly fills the recess (302') as shown in fig. 3.

Fig. 5 is a schematic diagram of a semiconductor package according to another embodiment of the utility model. As shown in fig. 5, in a semiconductor package (50), a semiconductor die (501) is formed over a substrate (500) and coupled to an upper surface of the substrate (500). It should be understood that the semiconductor die (501) may include a stack of dies and may be wire bonded to an upper surface (not shown) of the substrate (500) via a number of wires. A first insulating molding material (502) is located over the substrate (500) encapsulating the semiconductor die (501) and the conductive lines (not shown) and covering a portion of the upper surface of the substrate (500). It is still to be understood that conductive solder balls (not shown) may be further formed on the lower surface of the substrate (500) to achieve electrical connection of the semiconductor package (50) with an external device.

Still referring to fig. 5, in the semiconductor package (50), the first insulating molding material (502) further includes a plurality of recesses (e.g., three recesses (502') shown in fig. 5), and a second insulating molding material (503) is formed in each recess (502'). Wherein the molding compound used to form the first insulating molding material (502) has a higher modulus, and the molding compound used to form the second insulating molding material (503) has a lower modulus relative to the molding compound of the first insulating molding material (502). That is, three second insulating molding materials (503) having a low modulus are respectively embedded in three top grooves of the first insulating molding material (502) having a high modulus.

When subjected to a strain test such as that shown in fig. 2, the semiconductor package (50) is mounted upside down on a test stand (201) and a strain gauge (203) in a similar fashion to the semiconductor package (200) of fig. 2. At this time, the second insulating molding material (503) located at the center of the three second insulating molding materials (503) is directly contacted with the strain gauge (203) instead of the first insulating molding material (502), and the central second insulating molding material (503) can effectively absorb the stress applied to the semiconductor package (50) by the probe (202), thereby enhancing the package strain of the semiconductor package. It is to be understood that the second insulating molding materials located at both sides of the central second insulating molding material (503) may be symmetrically disposed with respect to the central second insulating molding material (503).

In one embodiment, the top surface of the first insulating molding material (502) is coplanar with the top surfaces of the plurality of second insulating molding materials (503) to make the top surface of the semiconductor package (50) flat and aesthetically pleasing. However, depending on the actual process or other factors, it is also possible to allow the top surface of the first insulating molding material (502) to deviate from being coplanar with the top surfaces of the plurality of second insulating molding materials (503), or the top surfaces of the plurality of second insulating molding materials (503) deviate from being coplanar with each other, which does not affect the package strain of the semiconductor package (50) to be enhanced. In another embodiment, the bottom surfaces of the plurality of second insulating molding materials (503) may further include rounded corners instead of sharp corners as shown in fig. 5, so that the plurality of second insulating molding materials (503) sufficiently and smoothly fill the respective grooves (502').

Compared to the single-body embedded form shown in fig. 3, the semiconductor package structure of fig. 5 embeds a plurality of second insulating molding materials (503) in the first insulating molding material (502) in a multi-body form, so as to further improve the structural characteristics of the semiconductor package (50), such as (but not limited to) improving the package strength and suppressing the warpage.

Fig. 6A shows a top view of the semiconductor package structure shown in fig. 5. As shown in fig. 6A, a first insulating molding material (602) having a higher modulus has embedded therein a plurality of second insulating molding materials (603) having a lower modulus, wherein the second insulating molding material (603) located at the center of the top of the first insulating molding material (602) is in direct contact with a strain gauge (e.g., strain gauge (203) in fig. 2) used for testing.

Fig. 6B shows a top view of a semiconductor package structure similar to fig. 6A except that a plurality of second insulating molding materials (603) embedded in the first insulating molding material (602) of fig. 6B respectively include rounded corners instead of sharp corners as shown in fig. 6A from a top view, so that the second insulating molding material (603) sufficiently and smoothly fills the recess (502') as shown in fig. 3.

Fig. 7 shows a detailed structural diagram of a semiconductor package according to an embodiment of the utility model. As shown in fig. 7, in a semiconductor package (70), a stack of semiconductor dies (701) is formed over a substrate (700) and coupled to an upper surface of the substrate (700) via a plurality of connections (702). A symmetrically disposed stack of memory dies (703) (e.g., a NAND memory die stack) is formed over the semiconductor die (701). Since the bottom area of the stack of memory dies (703) is significantly larger than the top area of the underlying semiconductor die (701) such that overhang occurs, it is necessary to form support pads (704), such as Silicon Spacers (SS), between the upper surface of the substrate (700) and the lower surface of the stack of memory dies (703) on both sides of the semiconductor die (701) to provide the necessary mechanical support to prevent collapse of the stack of memory dies (703). The stack of memory dies 703 may further be connected to an upper surface of the substrate 700 via a number of wires (not shown). In addition, the lower surface of the substrate (700) includes one or more solder balls (707) to further enable electrical connection of the semiconductor package (70) to external devices. A first insulative molding material (705) is located over the substrate (700) encapsulating the semiconductor die (701), the plurality of connections (702), the stack of memory dies (703), the support pads (704), and the number of conductive lines (not shown), and covering a portion of the upper surface of the substrate (700).

Still referring to fig. 7, in a semiconductor package (70), a single, low modulus second insulating molding material (706) is formed atop a first insulating molding material (705) that is embedded atop the high modulus first insulating molding material (705) and makes direct contact with a strain gauge when subjected to a strain test such as that shown in fig. 2, thereby enhancing package strain of the semiconductor package.

It should be understood that the second insulating molding material (706) in fig. 7 may also be embedded in the first insulating molding material (705) in a multi-body form as shown in fig. 5, not limited to the single-body form shown in fig. 7.

Fig. 8 is a schematic structural diagram of a semiconductor package according to another embodiment of the present invention. As shown in fig. 8, in a semiconductor package (80), a stack of semiconductor dies (801) is formed over a substrate (800) and coupled to an upper surface of the substrate (800) via a plurality of connections (802). Unlike fig. 7, the memory die stack 803 is formed directly on the substrate 800 lateral to the semiconductor die 801, so there is no need to employ Silicon Spacers (SS) to provide mechanical support. It should be understood that the memory die stack 803 may further be connected to the substrate 800 via a number of wires (not shown). The lower surface of the substrate (800) includes one or more solder balls (806) to further enable electrical connection of the semiconductor package (80) to external devices. Similar to the embodiment shown in fig. 7, a first insulative molding material (804) encapsulates the semiconductor die (801), the plurality of connections (802), the memory die stack (803), and the number of conductive lines (not shown) over the substrate (800) and covers a portion of the upper surface of the substrate (800). Wherein the first insulating molding material (804) is formed on top of a unitary, low modulus second insulating molding material (805) which is embedded on top of the first insulating molding material (804) having a high modulus and makes direct contact with a strain gauge when subjected to a strain test such as that shown in fig. 2, thereby enhancing package strain of the semiconductor package.

It should be understood that the second insulating molding material (805) in fig. 8 may also be embedded in the first insulating molding material (804) in a multi-body form as shown in fig. 5, without being limited to the single-body form shown in fig. 8.

Fig. 9A to 9D illustrate method steps for forming the semiconductor package structure shown in fig. 3 according to an embodiment of the present invention.

First, in a step shown in fig. 9A, a semiconductor die (901) is formed on an upper surface of a substrate (900). It should be appreciated that the semiconductor Die (901) may be coupled to the upper surface of the substrate (900) via a plurality of connections (not shown) through a Die Attach (DA) and Wire-Bonding (WB) process. It should still be understood that the semiconductor die 901 may have a die structure such as, but not limited to, that shown in fig. 7 and 8.

Next, in the step shown in fig. 9B, a first insulating molding material (902) having a higher modulus is formed over the substrate (900) to encapsulate the semiconductor die (901) and cover a part of the upper surface of the substrate (900).

Again, in the step shown in fig. 9C, a recess (902') is formed on top of the first insulating molding material (902) using, for example, but not limited to, an etching process.

Finally, a second insulating molding material (903) with a lower modulus is injected/embedded in the groove (902') under the same molding process. As an example, the top surface of the semiconductor package may be ground after this step is completed so that the top surfaces of the first insulating molding material (902) and the second insulating molding material (903) are coplanar.

The semiconductor packaging structure provided by the utility model uses the molding compound with lower modulus, and can obviously enhance the packaging strain of the semiconductor package, thereby being beneficial to passing the increasingly severe packaging strain test on one hand and improving the mechanical strain capability of the semiconductor package in practical application on the other hand. At the same time, the present invention allows the thickness of the over-die molding compound to be less than 130 μm, thereby reducing the overall height (i.e., Z-direction height) of the semiconductor package, which not only can increase the design flexibility of the over-die molding compound thickness, but can also allow the molding compound structure to be prepared in a standardized manner. Also, by using molding compounds with different moduli, tape warpage and/or component warpage can be better controlled. For example, the warpage of the device can be controlled between-80 μm and +80 μm at room temperature, and can be controlled between-80 μm and +30 μm at high temperature.

Furthermore, semiconductor chips containing passive devices (e.g., capacitors) typically cannot be thinned too much because doing so can adversely affect the passive devices (e.g., wear out the passive devices, etc.). However, the semiconductor packaging structure provided by the utility model can ensure that the semiconductor chip package obtains good packaging and testing yield rate under the condition of not adopting a thinning process to make room for the thickness of the plastic on the bare chip.

It should be noted that reference throughout this specification to "one embodiment of the utility model" or similar terms means that a particular feature, structure or characteristic described in connection with the other embodiments is included in at least one embodiment and may not necessarily be present in all embodiments. Thus, respective appearances of the phrase "one embodiment of the utility model" or similar terms in various places throughout this specification are not necessarily referring to the same embodiment.

Furthermore, the particular features, structures, or characteristics of any specific embodiment may be combined in any suitable manner with one or more other embodiments.

The technical contents and features of the present invention have been described in the above-mentioned embodiments, but the above-mentioned embodiments are only examples for implementing the present invention. It will be apparent to those skilled in the art that various substitutions and modifications can be made based on the teachings and teachings of the utility model without departing from the spirit of the utility model. Accordingly, the disclosed embodiments of the utility model do not limit the scope of the utility model. Rather, modifications and equivalent arrangements included within the spirit and scope of the claims are included within the scope of the utility model.

Claims (10)

1. A semiconductor package, comprising:

a substrate having a first surface;

a semiconductor die coupled to the first surface of the substrate;

a first insulating material covering the semiconductor die and at least a portion of the first surface of the substrate, wherein the first insulating material includes a first recess located over the semiconductor die; and

a second insulating material located in the first groove, wherein an elastic modulus of the second insulating material is lower than an elastic modulus of the first insulating material.

2. The semiconductor package of claim 1, wherein the second insulating material is centered on top of the first insulating material.

3. The semiconductor package of claim 1, wherein a top surface of the first insulating material is coplanar with a top surface of the second insulating material.

4. The semiconductor package of claim 1, wherein the first recess has one or more rounded corners.

5. The semiconductor package of claim 1, wherein the first insulating material comprises a second recess located above the semiconductor die and separated from the first recess.

6. The semiconductor package of claim 5, wherein the first insulating material comprises a third recess located over the semiconductor die and separated from the first recess and the second recess, wherein the second recess and the third recess are located on either side of the first recess.

7. The semiconductor package according to claim 6, wherein the second and third grooves are symmetrical with respect to the first groove.

8. The semiconductor package according to claim 1, wherein each of the first insulating material and the second insulating material comprises a resin, a hardener, and a filler.

9. The semiconductor package according to claim 8, wherein the first insulating material and the second insulating material comprise the same resin and the same hardener.

10. The semiconductor package according to claim 8, wherein a content of the filler of the first insulating material is higher than a content of the filler of the second insulating material.

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