CN215420220U - Low-power consumption wake-up circuit and electronic equipment - Google Patents
Low-power consumption wake-up circuit and electronic equipment Download PDFInfo
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- CN215420220U CN215420220U CN202120970807.3U CN202120970807U CN215420220U CN 215420220 U CN215420220 U CN 215420220U CN 202120970807 U CN202120970807 U CN 202120970807U CN 215420220 U CN215420220 U CN 215420220U
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Abstract
The utility model discloses a low-power consumption wake-up circuit, which comprises a charging management chip, a power supply module and a power supply module, wherein the charging management chip is provided with at least one multiplexing pin; further comprising: a wake-up module, the wake-up module comprising: a trigger element operatively connected to a system power source; the control end of the first switch element is connected with the trigger element, one end of a switch path of the first switch element is connected with the multiplexing pin, and the other end of the switch path of the first switch element is grounded; and one path of a control end of the second switch element is connected with the system power supply, the other path of the control end of the second switch element is grounded through a first resistor, one end of a switch path of the second switch element is connected with the trigger element, and the other end of the switch path of the second switch element is connected with the multiplexing pin. An electronic device is also disclosed. The low-power wake-up method does not need to design a plurality of independent hardware, does not influence the use of other functions, and has the advantage of good practicability.
Description
Technical Field
The utility model belongs to the technical field of electronic equipment, and particularly relates to a low-power-consumption wake-up circuit and electronic equipment with the same.
Background
A small electronic device such as a wearable device or a wireless headset charging box is generally provided with a lithium battery or a lithium polymer battery. In order to improve the support range of the input voltage, optimize the efficiency of the switch mode, reduce the charging time, and prolong the service life in the discharging stage, a charging chip with battery charging management and system power path management functions is usually designed to realize rapid charging.
When a new product leaves a factory, in order to avoid the situation that the electric quantity of a battery is exhausted due to overhigh power consumption of electronic equipment in the transportation process, a low-power-consumption mode is usually integrated with the charged new product, and a system power supply is automatically cut off in the transportation process. After receiving the product, the user wakes up the system power supply by the hardware with the activation function, so that the electronic equipment enters a normal working mode. Due to the limited volume of the small electronic device, if a separate wake-up hardware is designed, the design space of the electronic device is squeezed, and if the small electronic device is integrated with other hardware, the normal functions of detection, reset and the like can be affected.
Disclosure of Invention
The utility model provides a low-power consumption wake-up circuit aiming at the problems that the volume of small electronic equipment is limited, the design space of the electronic equipment can be extruded if a single wake-up hardware is designed, and the normal functions of detecting and resetting and the like can be influenced if the single wake-up hardware is integrated with other hardware.
In order to realize the purpose of the utility model, the utility model adopts the following technical scheme to realize:
a low-power consumption wake-up circuit comprises a charging management chip, a first power supply and a second power supply, wherein the charging management chip is provided with at least one multiplexing pin; further comprising: a wake-up module, the wake-up module comprising: a trigger element operatively connected to a system power source; the control end of the first switch element is connected with the trigger element, one end of a switch path of the first switch element is connected with the multiplexing pin, and the other end of the switch path of the first switch element is grounded; and one path of a control end of the second switch element is connected with the system power supply, the other path of the control end of the second switch element is grounded through a first resistor, one end of a switch path of the second switch element is connected with the trigger element, and the other end of the switch path of the second switch element is connected with the multiplexing pin.
Further, the charging management chip is configured to enable the system power supply to maintain a low power consumption output in a low power consumption mode; the trigger element executes a wake-up action, the control end of the first switch element is connected with a system power supply maintaining low power consumption output through the trigger element, and a switch path of the first switch element is switched off; and the control end of the second switch element is connected with a system power supply for maintaining low-power-consumption output, and a switch path of the second switch element is conducted and outputs a wake-up level signal to the multiplexing pin.
Further, the charging management chip is configured to enable the system power supply to maintain normal operation output after the multiplexing pin receives the wake-up level signal, the control end of the first switch element is connected to the system power supply maintaining normal operation output through the trigger element, and a switch path of the first switch element is turned on; the control end of the second switch element is connected with a system power supply for maintaining normal working output, and the switch path of the second switch element is turned off.
In order to provide a grounding point with stable system, the trigger element comprises a first end and a second end, the first end of the trigger element is connected with the control end of the first switch element, one path of the second end of the trigger element is connected with the system power supply, and the other path of the second end of the trigger element is grounded through a capacitor; further comprising: one path of a control end of the third switching element is connected with the system power supply, the other path of the control end of the third switching element is grounded through a second resistor, one path of a switching path of the third switching element is connected with the system power supply, the other path of the switching path of the third switching element is connected with the second end of the trigger element, and the other end of the switching path of the third element is grounded.
Optionally, the control end of the first switch element is connected to a system power supply for maintaining normal operation output through a trigger element; the trigger element executes a reset action, the control end of the first switch element receives a reset driving signal, and the switch path of the first switch element switches action to generate and output a reset level signal to the multiplexing pin.
Preferably, the trigger element is a key.
Preferably, the first switching element is an N-channel MOS transistor, and the second switching element is a P-channel MOS transistor.
Preferably, the third switching element is a P-channel MOS transistor.
Further, the method also comprises the following steps: and one end of the electrostatic protection diode is connected with the first end of the trigger element, the other end of the electrostatic protection diode is connected with the control end of the first switch element, and the other end of the electrostatic protection diode is grounded.
Another aspect of the utility model provides an electronic device comprising a low power wake-up circuit; the low-power consumption wake-up circuit comprises a charging management chip, wherein the charging management chip is provided with at least one multiplexing pin; further comprising: a wake-up module, the wake-up module comprising: a trigger element operatively connected to a system power source; the control end of the first switch element is connected with the trigger element, one end of a switch path of the first switch element is connected with the multiplexing pin, and the other end of the switch path of the first switch element is grounded; and one path of a control end of the second switch element is connected with the system power supply, the other path of the control end of the second switch element is grounded through a first resistor, one end of a switch path of the second switch element is connected with the trigger element, and the other end of the switch path of the second switch element is connected with the multiplexing pin.
Compared with the prior art, the utility model has the advantages and positive effects that: through the circuit design disclosed by the utility model, the multiplexing pin of the charging management chip can receive a wake-up level signal or a signal corresponding to other functions through the switching path of the first switching element or the switching path of the second switching element, so that different functions are executed; the on-off action of the first switch element and the second switch element is based on the operation of the same trigger element, a plurality of independent hardware does not need to be designed, the use of other functions is not influenced, and the advantage of good practicability is achieved.
Other features and advantages of the present invention will become more apparent from the following detailed description of the utility model when taken in conjunction with the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a circuit diagram of a charging management chip in an embodiment of a low power wake-up circuit provided in the present invention;
fig. 2 is a circuit diagram of a wake-up module in an embodiment of a low power wake-up circuit provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and examples.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the utility model and are not to be construed as limiting the utility model.
It should be noted that in the description of the present invention, the terms of direction or positional relationship indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, which are merely for convenience of description, and do not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Aiming at the problems that the small electronic equipment is limited in size, if a single wake-up hardware is designed, the design space of the electronic equipment can be squeezed, and if the small electronic equipment is integrated with other hardware, the normal functions of detection, reset and the like can be influenced, a newly designed low-power wake-up circuit is shown in fig. 1 and fig. 2. The low power wake-up circuit includes a charge management chip U1. The charging management chip U1 is matched with a lithium battery or a lithium polymer battery, and a low power consumption mode is arranged in the charging management chip U1. During transportation, the charging management chip U1 enters a low power consumption mode to automatically cut off the system power supply VSYS. The charge management chip U1 optionally has battery charge management and system power VSYS path management functions. The charge management chip U1 has at least one multiplexing pin QON that performs different functions by multiplexing the format of the input signal through the pins QON. As an example, the charging management chip U1 may be a charging management chip U1BQ25619/618 from TEXAS INSTRUMENTS, Inc. In order to realize the time-sharing multiplexing of the wake-up function and other functions, a wake-up module is specially designed in the low-power wake-up circuit. As shown in fig. 2, the wake-up module mainly includes a triggering element SW1, a first switching element Q1 and a second switching element Q2. The triggering element SW1 is operatively connected to the system power supply VSYS, the control terminal of the first switching element Q1 is connected to the triggering element SW1, and the switching path of the first switching element Q1 is connected to the multiplexing pin QON at one terminal and to ground at the other terminal. One control end of the second switch element Q2 is connected with a system power supply VSYS, the other control end is grounded through a first resistor R27, one end of a switch path of the second switch element Q2 is connected with the trigger element SW1, and the other end of the switch path is connected with the multiplexing pin QON. With this circuit design, the multiplexing pin QON of the charge management chip U1 can receive a wake-up level signal or a signal corresponding to other functions through the switching path of the first switching element Q1 or the switching path of the second switching element Q2, thereby performing different functions; the on-off operation of the first switching element Q1 and the second switching element Q2 is based on the operation of the same trigger element SW1, so that a plurality of independent hardware does not need to be designed, the use of other functions is not affected, and the advantage of good practicability is achieved.
Referring to fig. 1 and 2, in particular, the charge management chip U1 is configured to maintain a low power output from the system power supply VSYS in a low power mode. If the triggering element SW1 performs the wake-up action, since the control terminal of the first switching element Q1 is connected to the system power VSYS maintaining a low power consumption output through the triggering element SW1, the switching path of the first switching element Q1 is turned off because the first switching element Q1 does not satisfy the turn-on condition. The control terminal of the second switch element Q2 is connected to the system power VSYS for maintaining low power consumption output, and due to the function of the first resistor R27, the second switch element Q2 satisfies the conducting condition, and the switch path of the second switch element Q2 is conducted and outputs the wake-up level signal to the multiplexing pin QON. Taking the charging management chip U1BQ25619/618 of TEXAS INSTRUMENTS as an example, the wake-up level signal is a low level signal. After the multiplexing pin QON receives the wake-up level signal, the charging management chip U1 automatically exits the low power mode.
Based on the built-in function of the charging management chip U1, the charging management chip U1 is further configured to maintain the system power supply VSYS at a normal operation output after the wake-up level signal is received at the multiplexing pin QON. At this time, the triggering device SW1 has already performed the wake-up action, the control terminal of the first switching device Q1 is connected to the system power VSYS maintaining the normal operation output through the triggering device SW1, the first switching device Q1 satisfies the conducting condition, and the switching path of the first switching device Q1 is conducted. Meanwhile, the control terminal of the second switching element Q2 is connected to the system power VSYS that maintains normal operation output, and the switching path of the second switching element Q2 is turned off when the on condition is no longer satisfied. The multiplexing pin QON of the charge management chip U1 can receive signals corresponding to other functions through the switching path of the first switching element Q1, thereby implementing other functions. For example, the control terminal of the first switching element Q1 is connected to the system power VSYS maintaining normal operation output through the triggering element SW1, and the charging management chip U1 exits the low power consumption mode. In this state, the triggering device SW1 performs a reset operation, the control terminal of the first switching device Q1 receives the reset driving signal, the switching path of the first switching device Q1 switches, and a reset level signal is generated and output to the multiplexing pin QON. Taking the charging management chip U1BQ25619/618 of TEXAS INSTRUMENTS as an example, the reset level signal may be a low level signal with a minimum duration of 8s, and after receiving the reset level signal, the charging management chip U1 automatically turns off the 250mm system power VSYS and maintains the normal operation output again. The reset function is realized by a built-in circuit of the charging management chip U1, and if the charging management chip U1 of other models is adopted, the reset level signal is designed to be matched with the charging management chip U1 of other models, and the description is not repeated.
The circuit connection of the trigger element SW1 is further described in detail. The triggering device SW1 includes a first terminal and a second terminal, the first terminal of the triggering device SW1 is connected to the control terminal of the first switching device Q1, the second terminal of the triggering device SW1 is connected to the system power source VSYS, and the other terminal is connected to the ground via the capacitor C9. In order to ensure a stable grounding point in the circuit, in particular in different connection states, a third switching element Q3 is provided, the control terminal of the third switching element Q3 being connected to the system power supply VSYS in one path and to the ground in the other path via a second resistor. One end of a switch path of the third switching element Q3 is connected to the system power supply VSYS, the other end is connected to the second end of the triggering element SW1, and the other end of the switch path of the third switching element Q3 is grounded. By designing the third switching element Q3, when the system power supply VSYS maintains low power consumption output, the third switching element Q3 meets the conducting condition, the switching path of the third switching element Q3 is conducted to form a stable grounding point, thereby ensuring the stable operation of the circuit, and when the system power supply VSYS maintains normal operation output, the switching path of the third switching element Q3 is turned off, thereby not affecting the normal function of the circuit.
In the present embodiment, the triggering element SW1 is preferably a key, which may be a touch key, a membrane key or other type of physical key. The contacts of the toggle element SW1 are configured between the first and second ends of the toggle element SW 1. The waking action is the action of pressing down the key.
Preferably, the first switching element Q1 is implemented by an N-channel MOS transistor, and the second switching element Q2 is implemented by a P-channel MOS transistor. The gate G of the first switching element Q1 is connected to the triggering element SW1, i.e., the button, the drain D of the first switching element Q1 is connected to the multiplexing pin QON, and the source S of the first switching element Q1 is grounded. The gate G of the second switch element Q2 is connected to the system power supply VSYS in one way, the other way is grounded through the first resistor R27, the source S of the second switch element Q2 is connected to the trigger element SW1, and the drain D is connected to the multiplexing pin QON. In the low power consumption mode, the charging management chip U1 enables the system power supply VSYS to maintain low power consumption output, the key is pressed, the grid G of the first switch element Q1 is connected with the system power supply VSYS maintaining low power consumption output through the key, and the first switch element Q1 keeps off state because the on state of the N-channel MOS transistor is not satisfied. The gate G of the second switch device Q2 is connected to the system power VSYS for maintaining low power consumption output, and due to the very low effective conduction characteristic of the gate G of the P-channel MOS transistor, the second switch device Q2 is short-circuited to ground, the switch path of the second switch device Q2 is turned on, and the multiplexing pin QON receives the wake-up level signal to automatically exit the low power consumption mode. Then the system power supply VSYS maintains normal work output, the grid G of the first switch element Q1 is connected with the system power supply VSYS which maintains normal work output through a key, the N-channel MOS transistor meets the conduction condition, and the switch path of the first switch element Q1 is conducted. The gate G of the second switching element Q2 is connected to the system power VSYS for maintaining normal operation output, and no longer satisfies the conduction condition, the switching path of the second switching element Q2 is turned off, and the normal operation state is maintained.
The on-off state of the third switching element Q3 is similar to that of the first switching element Q1. The gate G of the third switching element Q3 is connected to the system power supply VSYS all the way, the other way is grounded through the second resistor R28, the source S of the third switching element Q3 is connected to the system power supply VSYS all the way, the other way is connected to the second end of the triggering element SW1, and the drain D is grounded. In the low power consumption mode, the charging management chip U1 enables the system power supply VSYS to maintain low power consumption output, and due to the extremely low effective conduction characteristic of the gate G of the P-channel MOS transistor, the third switching element Q3 is short-circuited to ground, and the switching path of the third switching element Q3 is turned on, thereby providing a stable grounding point for the system. After the low power consumption mode is exited, the system power supply VSYS maintains normal work output, the grid G of the third switching element Q3 is connected with the system power supply VSYS maintaining normal work output, the conduction condition is not met any more, the switching path of the third switching element Q3 is turned off, and the normal work of the circuit is not influenced.
It will be understood by those skilled in the art that the first switching element Q1, the second switching element Q2 and the third switching element Q3 may be implemented by other electronic elements, such as a transistor, etc.
Referring to fig. 2, an electrostatic protection diode D1 is further designed in the low power consumption wake-up circuit. One end of the esd protection diode D1 is connected to the first end of the trigger element SW1, the other end is connected to the control end of the first switch element Q1, and the other end of the esd protection diode D1 is grounded.
Another aspect of the utility model provides an electronic device having a low power wake-up circuit disposed therein. For specific circuit connections of the low-power wake-up circuit, reference is made to the detailed descriptions of the above embodiments and the drawings in the specification, and detailed descriptions thereof are omitted. The electronic equipment provided with the low-power-consumption wake-up circuit can achieve the same technical effect. Electronic devices include, but are not limited to, wearable devices, which may be smart watches, smart bracelets, smart rings, smart foot rings, and wireless headset charging boxes.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (10)
1. A low-power consumption wake-up circuit comprises a charging management chip, a first power supply and a second power supply, wherein the charging management chip is provided with at least one multiplexing pin; it is characterized by also comprising:
a wake-up module, the wake-up module comprising:
a trigger element operatively connected to a system power source;
the control end of the first switch element is connected with the trigger element, one end of a switch path of the first switch element is connected with the multiplexing pin, and the other end of the switch path of the first switch element is grounded; and
one path of a control end of the second switch element is connected with the system power supply, the other path of the control end of the second switch element is grounded through the first resistor, one end of a switch path of the second switch element is connected with the trigger element, and the other end of the switch path of the second switch element is connected with the multiplexing pin.
2. The low power wake-up circuit of claim 1, wherein:
the charging management chip is configured to enable the system power supply to maintain low-power-consumption output in a low-power-consumption mode; the trigger element executes a wake-up action, the control end of the first switch element is connected with a system power supply maintaining low power consumption output through the trigger element, and a switch path of the first switch element is switched off; and the control end of the second switch element is connected with a system power supply for maintaining low-power-consumption output, and a switch path of the second switch element is conducted and outputs a wake-up level signal to the multiplexing pin.
3. The low power wake-up circuit of claim 2, wherein:
the charging management chip is configured to enable the system power supply to maintain normal working output after the multiplexing pin receives a wake-up level signal, the control end of the first switch element is connected with the system power supply maintaining normal working output through the trigger element, and a switch path of the first switch element is conducted; the control end of the second switch element is connected with a system power supply for maintaining normal working output, and the switch path of the second switch element is turned off.
4. A low power consumption wake-up circuit as claimed in any one of claims 1 to 3, wherein:
the trigger element comprises a first end and a second end, the first end of the trigger element is connected with the control end of the first switch element, one path of the second end of the trigger element is connected with the system power supply, and the other path of the second end of the trigger element is grounded through a capacitor;
further comprising:
one path of a control end of the third switching element is connected with the system power supply, the other path of the control end of the third switching element is grounded through a second resistor, one path of a switching path of the third switching element is connected with the system power supply, the other path of the switching path of the third switching element is connected with the second end of the trigger element, and the other end of the switching path of the third element is grounded.
5. The wake-up circuit with low power consumption of claim 4, wherein the control terminal of the first switch element is connected to a system power supply for maintaining normal operation output through a trigger element; the trigger element executes a reset action, the control end of the first switch element receives a reset driving signal, and the switch path of the first switch element switches action to generate and output a reset level signal to the multiplexing pin.
6. The wake-up circuit with low power consumption of claim 1, wherein the trigger element is a key.
7. The wake-up circuit with low power consumption of claim 1, wherein the first switching element is an N-channel MOS transistor and the second switching element is a P-channel MOS transistor.
8. The wake-up circuit with low power consumption of claim 4, wherein the third switching element is a P-channel MOS transistor.
9. The wake-up circuit with low power consumption of claim 4, further comprising: and one end of the electrostatic protection diode is connected with the first end of the trigger element, the other end of the electrostatic protection diode is connected with the control end of the first switch element, and the other end of the electrostatic protection diode is grounded.
10. An electronic device comprising a low power wake-up circuit as claimed in any one of claims 1 to 9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115118534B (en) * | 2022-06-07 | 2023-11-17 | 合肥移瑞通信技术有限公司 | Low-power-consumption state control method, device, terminal and storage medium of MBB equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115118534B (en) * | 2022-06-07 | 2023-11-17 | 合肥移瑞通信技术有限公司 | Low-power-consumption state control method, device, terminal and storage medium of MBB equipment |
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