CN215420204U - Circuit structure for eliminating input offset influence of operational amplifier - Google Patents
Circuit structure for eliminating input offset influence of operational amplifier Download PDFInfo
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- CN215420204U CN215420204U CN202121663572.XU CN202121663572U CN215420204U CN 215420204 U CN215420204 U CN 215420204U CN 202121663572 U CN202121663572 U CN 202121663572U CN 215420204 U CN215420204 U CN 215420204U
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Abstract
The utility model discloses a circuit structure for eliminating input offset influence of an operational amplifier, which comprises a first current source and a second current source, wherein the output end of the first current source is provided with a first triode, the output end of the second current source is provided with a second triode, and the output ends of the node potentials of the first triode and the first current source and the node potentials of the second triode and the second current source are provided with a first single-pole double-throw switch. The structure can accurately eliminate the influence of the offset error of the input of the two operational amplifiers on the detection precision on the premise of not adding additional complex functional circuits and power consumption overhead, and effectively eliminate the influence of the offset error of the input of the operational amplifiers on the detection precision on the premise of not adding additional functional modules and power consumption overhead, thereby reducing the additional circuits and power consumption overhead and obviously reducing the chip area and power consumption.
Description
Technical Field
The utility model relates to the technical field of temperature detectors, in particular to a circuit structure for eliminating input offset influence of an operational amplifier.
Background
The high-precision temperature detector chip generally utilizes the characteristic that when two bipolar transistors (emitter area ratio is 1: n) with different sizes flow currents with equal size (or in a certain proportional multiple), the difference value (delta VBE) of base-emitter Voltages (VBE) of the two bipolar transistors is in direct proportion to absolute temperature, a voltage value which changes in positive proportion along with the temperature is output, and after the voltage value is properly amplified by an operational amplifier, the voltage value is compared with a preset calibrated temperature-voltage curve to measure the actual value of the temperature of the chip;
the Δ VBE value is generally about several tens of millivolts in a full temperature range (e.g., between-40 ℃ and 130 ℃) along with temperature changes, but the input offset Voltage (VOS) of the operational amplifier is generally several millivolts in a CMOS process, and if the VBE values of two different transistors are directly subjected to difference processing by using a differential operational amplifier, the magnitude of an error value is not negligible compared with the absolute value of the VBE, which affects temperature detection accuracy, and the input offset voltage VOS value of the operational amplifier has a temperature drift effect, which further introduces temperature nonlinearity of an output voltage curve.
The prior art has the following defects: in the prior art, the temperature drift effect is solved by adopting an operational amplifier input offset technology, but the technology needs to add an additional circuit and power consumption overhead, so that the chip area and the power consumption are obviously increased.
SUMMERY OF THE UTILITY MODEL
In order to overcome the above-mentioned defects in the prior art, embodiments of the present invention provide a circuit structure for eliminating the influence of input offset of an operational amplifier, so as to effectively eliminate the influence of input offset of the operational amplifier on detection accuracy without adding additional functional modules and power consumption overhead, thereby solving the problems in the background art.
In order to achieve the purpose, the utility model provides the following technical scheme: including first current source and second current source, the output of first current source is equipped with first triode, the output of second current source is equipped with the second triode, the output of the node potential of first triode and first current source and the node potential of second triode and second current source is equipped with first single-pole double-throw switch.
In a preferred embodiment, a first operational amplifier is provided at an output end of the first single-pole double-throw switch, a second operational amplifier is provided at an output end of the first operational amplifier, and a second single-pole double-throw switch is provided at an output end of the second operational amplifier.
In a preferred embodiment, the first transistor is electrically connected to a first current source, the second transistor is electrically connected to a second current source, and the first single-pole double-throw switch, the first operational amplifier, the second operational amplifier, and the second single-pole double-throw switch are connected in series.
In a preferred embodiment, the output end of the first operational amplifier is provided with a first resistor, the output end of the first resistor is electrically connected with the second operational amplifier, the output end of the first resistor is provided with a second resistor, and the second resistor is connected with the second operational amplifier in parallel.
In a preferred embodiment, an oscillator is provided at an output terminal of each of the first and second single-pole double-throw switches, and the first and second single-pole double-throw switches are both in signal connection with the oscillator.
In a preferred embodiment, an analog-to-digital converter is disposed at an output end of the second single-pole double-throw switch, a register/digital subtractor is disposed at an output end of the analog-to-digital converter, and the register/digital subtractor is electrically connected to the analog-to-digital converter, which is electrically connected to the second single-pole double-throw switch.
The utility model has the technical effects and advantages that:
the utility model accurately eliminates the influence of the offset error of the input of the two operational amplifiers on the detection precision on the premise of not adding an additional complex functional circuit (such as a chopping technology) and power consumption overhead, and the structure effectively eliminates the influence of the offset error of the input of the operational amplifiers on the detection precision on the premise of not adding an additional functional module and power consumption overhead, thereby reducing the additional circuit and power consumption overhead and obviously reducing the chip area and power consumption.
Drawings
FIG. 1 is a block diagram of a circuit of the present invention.
Fig. 2 is a schematic circuit diagram of the present invention.
The reference signs are: 1. a first current source; 2. a second current source; 3. a first triode; 4. a second triode; 5. a first single pole double throw switch; 6. a first operational amplifier; 7. a second operational amplifier; 8. A second single pole double throw switch; 9. an oscillator; 10. an analog-to-digital converter; 11. a register/digital subtractor; 12. a first resistor; 13. a second resistor.
Schematic circuit diagram symbol:
IS: first/second current source
Q0: a first triode
Q1: second triode
SPDT 1: first single-pole double-throw switch
SPDT 2: second single-pole double-throw switch
OP 1: a first operational amplifier
OP 2: a second operational amplifier
OSC: oscillator
ADC: analog-to-digital converter
And (3) RO: a first resistor
R1: second resistance
VDD: power supply
GND: ground connection
VBE0/VBE 1: node potential
φ// φ: time period
Vos1/Vos 2: input offset voltage
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to the attached drawing 1 in the specification, a circuit structure for eliminating input offset influence of an operational amplifier according to an embodiment of the present invention includes a first current source 1 and a second current source 2, wherein an output terminal of the first current source 1 is provided with a first triode 3, an output terminal of the second current source 2 is provided with a second triode 4, an output terminal of a node potential of the first triode 3 and the first current source 1 and a node potential of the second triode 4 and the second current source 2 is provided with a first single-pole double-throw switch 5, an output terminal of the first single-pole double-throw switch 5 is provided with a first operational amplifier 6, an output terminal of the first operational amplifier 6 is provided with a second operational amplifier 7, an output terminal of the second operational amplifier 7 is provided with a second single-pole double-throw switch 8, the first triode 3 is electrically connected to the first current source 1, and the second triode 4 is electrically connected to the second current source 2, the first single-pole double-throw switch 5, the first operational amplifier 6, the second operational amplifier 7 and the second single-pole double-throw switch 8 are connected in series.
Further, the output end of the first operational amplifier 6 is provided with a first resistor 12, the output end of the first resistor 12 is electrically connected with the second operational amplifier 7, the output end of the first resistor 12 is provided with a second resistor 13, the second resistor 13 is connected with the second operational amplifier 7 in parallel, two equal-sized first current source 1 and second current source 2 generated by the current mirror are respectively injected into the collector electrodes of the first triode 3 and the second triode 4, the base electrodes of the first triode 3 and the second triode 4 are respectively connected with the collector electrodes of the first triode 3 and the second triode 4 to generate two node potentials VBE1 and VBE0, and VBE1 and VBE0 are respectively connected with two input ends of the first single-pole double-throw switch 5.
Further, referring to fig. 2 of the specification, an oscillator 9 is disposed at an output end of the first single-pole double-throw switch 5 and the second single-pole double-throw switch 8, the first single-pole double-throw switch 5 and the second single-pole double-throw switch 8 are both in signal connection with the oscillator 9, a gating control signal of the first single-pole double-throw switch 5 is controlled by a square wave pulse signal (corresponding to a phi time period and/phi time period, respectively) output by the oscillator 9, an output end of the gating control signal is connected with a positive phase input end of the first operational amplifier 6, an inverted phase input end of the first operational amplifier 6 is connected with an output end of the first operational amplifier 6, that is, a unity gain negative feedback form is formed, and an output end of the first operational amplifier 6 and an output end of the second operational amplifier 6 are connected with a negative feedback form
One end of a first resistor 12 is connected, the other end of the first resistor 12 is connected with the inverting input end of a second operational amplifier 7 and one end of a second resistor 13, the non-inverting input end of the second operational amplifier 7 is connected with the base electrode and the collector electrode of a first triode 3, the node potential is VBE0, the output end of the second operational amplifier 7 is connected with the other end of the second resistor 13 and two input ends of a second single-pole double-throw switch 8, the input end of an analog-to-digital converter 10 is connected with the output end of the second single-pole double-throw switch 8, the output end of the analog-to-digital converter 10 is connected with the input end of a register/digital subtracter 11, the output result of the analog-to-digital converter ADC is nbits digital code, in the phi time period of the output signal of an oscillator 9, the output digital code is DOUT1, the DOUT0 and the DOUT1 digital codes are stored by the register/digital subtracter 11, at the end of each period of the oscillator 9 signal, the register/digital subtractor 11 performs a difference operation on DOUT0 and DOUT1, and finally outputs digital codes DOUT1-DOUT0 for characterizing the real-time ambient temperature.
Further, an analog-to-digital converter 10 is disposed at an output end of the second single-pole double-throw switch 8, a register/digital subtractor 11 is disposed at an output end of the analog-to-digital converter 10, the register/digital subtractor 11 is electrically connected to the analog-to-digital converter 10, and the analog-to-digital converter 10 and the second single-pole double-throw switch 8
Electric connection, the electric current source of first triode 3 and second triode 4 is the electric current of certain proportional multiple, and the actual value and the proportional relation of first resistance 12 and second resistance 13 are adjusted according to the different demands of actual temperature monitoring range, and analog to digital converter 10's resolution ratio is adjusted according to the practical application requirement, and oscillator 9's frequency is adjusted according to actual temperature monitoring acquisition cycle, and the territory overall arrangement of first triode 3 and second triode 4 is 1: 8 "Sudoku" form.
The specific implementation mode is as follows: referring to the description of the attached FIG. 1, during the period φ, the expression:
from expression (1), it can be calculated:
similarly, in the period/phi, according to the circuit connection relation, the expression is obtained:
calculated from expression (3):
calculated from expressions (2) and (4):
as can be seen from expression (5), the input offset voltages Vos1 and Vos2 of the first operational amplifier 6 and the second operational amplifier 7 are eliminated during the operation process, so that the desired result of eliminating the input offset error factor of the operational amplifier is obtained.
The points to be finally explained are: first, in the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounted," "connected," and "connected" should be understood broadly, and may be a mechanical connection or an electrical connection, or a communication between two elements, and may be a direct connection, and "upper," "lower," "left," and "right" are only used to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed;
secondly, the method comprises the following steps: in the drawings of the disclosed embodiments of the utility model, only the structures related to the disclosed embodiments are referred to, other structures can refer to common designs, and the same embodiment and different embodiments of the utility model can be combined with each other without conflict;
and finally: the above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the utility model, and any modifications, equivalents, improvements and the like that are within the spirit and principle of the present invention are intended to be included in the scope of the present invention.
Claims (6)
1. The utility model provides a circuit structure of input maladjustment influence is put in elimination fortune, includes first current source (1) and second current source (2), the output of first current source (1) is equipped with first triode (3), the output of second current source (2) is equipped with second triode (4), its characterized in that: and a first single-pole double-throw switch (5) is arranged at the output ends of the node potentials of the first triode (3) and the first current source (1) and the node potentials of the second triode (4) and the second current source (2).
2. The circuit structure of claim 1, wherein the input offset of the operational amplifier is eliminated by: the output end of the first single-pole double-throw switch (5) is provided with a first operational amplifier (6), the output end of the first operational amplifier (6) is provided with a second operational amplifier (7), and the output end of the second operational amplifier (7) is provided with a second single-pole double-throw switch (8).
3. The circuit structure of claim 2, wherein the input offset of the operational amplifier is eliminated by: the first triode (3) is electrically connected with a first current source (1), the second triode (4) is electrically connected with a second current source (2), and the first single-pole double-throw switch (5), the first operational amplifier (6), the second operational amplifier (7) and the second single-pole double-throw switch (8) are connected in series.
4. The circuit structure of claim 2, wherein the input offset of the operational amplifier is eliminated by: the output end of the first operational amplifier (6) is provided with a first resistor (12), the output end of the first resistor (12) is electrically connected with the second operational amplifier (7), the output end of the first resistor (12) is provided with a second resistor (13), and the second resistor (13) is connected with the second operational amplifier (7) in parallel.
5. The circuit structure of claim 2, wherein the input offset of the operational amplifier is eliminated by: the output ends of the first single-pole double-throw switch (5) and the second single-pole double-throw switch (8) are provided with oscillators (9), and the first single-pole double-throw switch (5) and the second single-pole double-throw switch (8) are in signal connection with the oscillators (9).
6. The circuit structure of claim 2, wherein the input offset of the operational amplifier is eliminated by: the output end of the second single-pole double-throw switch (8) is provided with an analog-to-digital converter (10), the output end of the analog-to-digital converter (10) is provided with a register/digital subtracter (11), the register/digital subtracter (11) is electrically connected with the analog-to-digital converter (10), and the analog-to-digital converter (10) is electrically connected with the second single-pole double-throw switch (8).
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| CN202121663572.XU CN215420204U (en) | 2021-07-21 | 2021-07-21 | Circuit structure for eliminating input offset influence of operational amplifier |
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| CN202121663572.XU CN215420204U (en) | 2021-07-21 | 2021-07-21 | Circuit structure for eliminating input offset influence of operational amplifier |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113624356A (en) * | 2021-08-12 | 2021-11-09 | 上海旻森电子科技有限公司 | Circuit technology for eliminating input offset influence of operational amplifier in temperature detector |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113624356A (en) * | 2021-08-12 | 2021-11-09 | 上海旻森电子科技有限公司 | Circuit technology for eliminating input offset influence of operational amplifier in temperature detector |
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