CN215420101U - Low-cost 48V-12V direct current converter - Google Patents
Low-cost 48V-12V direct current converter Download PDFInfo
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- CN215420101U CN215420101U CN202120444485.9U CN202120444485U CN215420101U CN 215420101 U CN215420101 U CN 215420101U CN 202120444485 U CN202120444485 U CN 202120444485U CN 215420101 U CN215420101 U CN 215420101U
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- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 10
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims description 87
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 238000001514 detection method Methods 0.000 claims description 4
- 238000001914 filtration Methods 0.000 claims description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
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Abstract
The utility model discloses a low-cost 48V-12V direct current converter, which is divided into four channels; 1) the 48V positive electrode input end is connected to a pin 26 of a chip U1 through a series resistor, an inductor and an MOS (metal oxide semiconductor) tube, and a pin 13 of a chip U1 is connected to a 12V positive electrode output end through a resistor; 2) the 48V positive electrode input end is connected to a pin 19 of a chip U1 through a series resistor, an inductor and an MOS (metal oxide semiconductor) tube, and a pin 13 of a chip U1 is connected to a 12V positive electrode output end through a resistor; 3) the 48V positive electrode input end is connected to a pin 26 of a chip U2 through a series resistor, an inductor and an MOS (metal oxide semiconductor) tube, and a pin 13 of a chip U2 is connected to a 12V positive electrode output end through a resistor; 4) the 48V positive pole input end is connected to a pin 19 of the chip U2 through a series resistor, an inductor and a MOS (metal oxide semiconductor) tube, and a pin 13 of the chip U2 is connected to a 12V positive pole output end through a resistor. The utility model adopts a double-tube driving mode, thereby realizing low cost and miniaturization.
Description
Technical Field
The utility model relates to a new energy automobile, in particular to a low-cost 48V-12V direct current converter.
Background
The traditional DC/DC converter generally adopts a pulse transformer mode, but has the defects of high cost, large volume, large heat productivity, low efficiency and the like; therefore, the above problems need to be solved.
Disclosure of Invention
The utility model aims to solve the technical problem of providing a low-cost 48V-12V direct current converter, which adopts a double-tube driving mode to form a 12V-500W charger and meets the requirement of supplementing power to a 12V storage battery for a vehicle, thereby realizing low cost and miniaturization.
In order to solve the technical problems, the utility model adopts the following technical scheme: the utility model discloses a low-cost 48V-12V direct current converter, which has the innovation points that: the circuit comprises an aluminum substrate PCB, wherein a chip U1, a chip U2, a 48V positive input end, a 12V positive output end, a plurality of inductors, a plurality of MOS (metal oxide semiconductor) tubes and a plurality of resistors are sequentially arranged on the aluminum substrate PCB at intervals; the 48V positive input end is divided into four main channels after anti-reflection, filtering and detection;
the first path of main channel: the 48V positive electrode input end is connected to the source electrode of an MOS tube Q2 through a series resistor R4 and an inductor L3 in sequence, the grid electrode of the MOS tube Q2 is connected to a pin 26 of a chip U1, and a pin 13 of the chip U1 is connected to a 12V positive electrode output end through a series resistor R10;
the second path of main channel: the 48V positive electrode input end is connected to the source electrode of the MOS tube Q4 through a series resistor R6 and an inductor L4 in sequence, the grid electrode of the MOS tube Q4 is connected to a pin 19 of a chip U1, and a pin 13 of the chip U1 is connected to a 12V positive electrode output end through a series resistor R10;
a third main channel: the 48V positive electrode input end is connected to the source electrode of an MOS tube Q6 through a series resistor R12 and an inductor L5 in sequence, the grid electrode of the MOS tube Q6 is connected to a pin 26 of a chip U2, and a pin 13 of the chip U2 is connected to a 12V positive electrode output end through a series resistor R10;
the fourth main channel: the 48V positive pole input end is connected to the source of the MOS tube Q8 through a series resistor R13 and an inductor L6 in sequence, the gate of the MOS tube Q8 is connected to a pin 19 of the chip U2, and a pin 13 of the chip U2 is connected to a 12V positive pole output end through a series resistor R10.
Preferably, both the chip U1 and the chip U2 are LTC 3784.
Preferably, the device also comprises a plurality of capacitors and diodes; the 48V anode input end is connected with one end of a capacitor C5, a source electrode of a MOS tube Q1, a cathode of a diode D1 and one end of a capacitor C1, one end of a resistor R2 is connected with an anode of a diode D1 and a grid electrode of a MOS tube Q1, a drain electrode of a MOS tube Q1 and the other end of the capacitor C1 are connected with one end of an inductor L1, the other end of the inductor L1 is connected with one end of an inductor L2 and one end of the capacitor C6, the other end of the inductor L2 is connected with one end of capacitors C7 and C4 and one end of a resistor R7, the other end of the resistor R2 and the other ends of capacitors C5, C6, C7 and C4 are grounded, the other end of the resistor R7 is connected with one ends of resistors R9 and R8, the other end of the resistor R8 is connected with one end of a capacitor C2, and the other end of the capacitor C2 and the other end of the resistor R9 are grounded.
Preferably, the other end of the inductor L2 is connected to one end of resistors R4, R6, R12, and R13, pins 2, 12, and 23 of the chip U1, and pins 2, 12, and 23 of the chip U2, the other end of the resistor R4 is connected to one end of the inductor L3 and pin 3 of the chip U1, the other end of the resistor R6 is connected to one end of the inductor L4 and pin 11 of the chip U1, the other end of the resistor R12 is connected to one end of the inductor L5 and pin 3 of the chip U2, and the other end of the resistor R13 is connected to one end of the inductor L6 and pin 11 of the chip U2.
Preferably, the pins 4, 8 and 21 of the chip U1 and the pins 4, 8 and 15 of the chip U2 are grounded, the pin 6 of the chip U1 is connected to the pin 7 of the chip U2, the pin 9 of the chip U1 is connected to the pin 9 of the chip U2, the pin 10 of the chip U1 and the pin 10 of the chip U2 are grounded through a capacitor C23, the pin 14 of the chip U1 is connected to one end of a resistor R14, the pin 14 of the chip U2 is connected to one end of the capacitor C26 and one end of a resistor R14, the other end of the resistor R14 is connected to one end of a capacitor C25, the pin 14 of the chip U2 is connected to one end of the resistor R15, and the other end of the resistor R15 and the other ends of the capacitors C25 and C26 are grounded.
Preferably, the device also comprises a MOS transistor Q3 and a MOS transistor Q5; the other end of the inductor L3 is connected with the source of the MOS tube Q2, the drain of the MOS tube Q3, one end of the capacitor C8 and the pin 27 of the chip U1, the gate of the MOS tube Q3 is connected with the pin 24 of the chip U1, and the source of the MOS tube Q3 is grounded; the other end of the inductor L4 is connected with the source of the MOS tube Q4, the drain of the MOS tube Q5, one end of the capacitor C13 and the pin 16 of the chip U1, the gate of the MOS tube Q5 is connected with the pin 17 of the chip U1, and the source of the MOS tube Q5 is grounded through the capacitor C12; the other end of the capacitor C8 is connected with the cathode of the diode D2 and the pin 25 of the chip U1, the other end of the capacitor C13 is connected with the cathode of the diode D3 and the pin 18 of the chip U1, the anodes of the diodes D2 and D3 are connected with one end of the resistor R3, one end of the capacitor C9 and the pins 7, 15 and 20 of the chip U1, the other end of the resistor R3 is connected with the pin 28 of the chip U1, and the other end of the capacitor C9 is connected with the pin 22 of the chip U1; the MOS tubes Q3 and Q5 are arranged to synchronously rectify the first main channel and the second main channel respectively.
Preferably, the device also comprises a MOS transistor Q7 and a MOS transistor Q9; the other end of the inductor L5 is connected with the source of the MOS tube Q6, the drain of the MOS tube Q7, one end of the capacitor C18 and the pin 27 of the chip U2, the gate of the MOS tube Q7 is connected with the pin 24 of the chip U2, and the source of the MOS tube Q7 is grounded; the other end of the inductor L6 is connected with the source of the MOS tube Q8, the drain of the MOS tube Q9, one end of the capacitor C24 and the pin 16 of the chip U2, the gate of the MOS tube Q9 is connected with the pin 17 of the chip U2, and the source of the MOS tube Q9 is grounded through the capacitor C22; the other end of the capacitor C18 is connected with the cathode of the diode D4 and the pin 25 of the chip U2, the other end of the capacitor C24 is connected with the cathode of the diode D5 and the pin 18 of the chip U2, the anodes of the diodes D4 and D5 are connected with one end of the resistor R11, one end of the capacitor C19 and the pin 20 of the chip U2, the other end of the resistor R11 is connected with the pin 28 of the chip U2, and the other end of the capacitor C19 is connected with the pin 22 of the chip U2; and synchronously rectifying the third main channel and the fourth main channel by arranging MOS (metal oxide semiconductor) tubes Q7 and Q9.
Preferably, the drain of the MOS transistor Q2 is grounded via a capacitor C3, the drain of the MOS transistor Q4 is grounded, the drain of the MOS transistor Q6 is grounded via a capacitor C17, and the drain of the MOS transistor Q8 is grounded.
Preferably, the output current of the first main channel, the second main channel, the third main channel and the fourth main channel is 10A at most, and the maximum output power of the 12V positive electrode output end is 500W.
The utility model has the beneficial effects that:
(1) the utility model adopts a double-tube driving mode to form a 12V-500W charger, and the power supply of a 12V storage battery for a vehicle is satisfied, thereby realizing low cost and miniaturization;
(2) the utility model adopts the aluminum substrate PCB, thereby effectively improving the heat radiation performance and realizing natural cooling;
(3) the utility model adopts microminiature design and occupies small space.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments are briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is an electrical schematic of a low cost 48V-12V DC converter of the present invention.
Detailed Description
The technical solution of the present invention will be clearly and completely described by the following detailed description.
The utility model discloses a low-cost 48V-12V direct current converter, which comprises an aluminum substrate PCB, wherein a chip U1, a chip U2, a 48V positive pole input end, a 12V positive pole output end, a plurality of inductors, a plurality of MOS (metal oxide semiconductor) tubes, a plurality of resistors, a plurality of capacitors and a plurality of diodes are sequentially arranged on the aluminum substrate PCB at intervals; the electrical schematic diagram of the circuit is shown in fig. 1, a 48V positive input end is connected with one end of a capacitor C5, a source of a MOS transistor Q1, a cathode of a diode D1 and one end of a capacitor C1, one end of a resistor R2 is connected with an anode of a diode D1 and a gate of a MOS transistor Q1, a drain of a MOS transistor Q1 and the other end of a capacitor C1 are connected with one end of an inductor L1, the other end of an inductor L1 is connected with one end of an inductor L2 and one end of a capacitor C6, the other end of an inductor L2 is connected with one end of capacitors C7 and C4 and one end of a resistor R7, the other end of a resistor R2 and the other ends of capacitors C5, C6, C7 and C4 are grounded, the other end of a resistor R7 is connected with one end of resistors R9 and R8, the other end of a resistor R8 is connected with one end of a capacitor C2, and the other end of a capacitor C2 and the other end of a resistor R9 are grounded, so as to perform positive, anti-pole, anti-reverse filtering and detection on the 48V input end.
The 48V positive input end of the utility model is divided into four main channels after anti-reflection, filtering and detection; the types of the chips U1 and U2 are LTC 3784; as shown in figure 1 of the drawings, in which,
the first path of main channel: the 48V positive electrode input end is connected to the source electrode of an MOS tube Q2 through a series resistor R4 and an inductor L3 in sequence, the grid electrode of the MOS tube Q2 is connected to a pin 26 of a chip U1, the drain electrode of the MOS tube Q2 is grounded through a capacitor C3, and a pin 13 of the chip U1 is connected to a 12V positive electrode output end through a series resistor R10;
the second path of main channel: the 48V positive electrode input end is connected to the source electrode of an MOS tube Q4 through a series resistor R6 and an inductor L4 in sequence, the grid electrode of the MOS tube Q4 is connected to a pin 19 of a chip U1, the drain electrode of the MOS tube Q4 is grounded, and a pin 13 of a chip U1 is connected to a 12V positive electrode output end through a series resistor R10;
a third main channel: the 48V positive electrode input end is connected to the source electrode of an MOS tube Q6 through a series resistor R12 and an inductor L5 in sequence, the grid electrode of the MOS tube Q6 is connected to a pin 26 of a chip U2, the drain electrode of the MOS tube Q6 is grounded through a capacitor C17, and a pin 13 of the chip U2 is connected to a 12V positive electrode output end through a series resistor R10;
the fourth main channel: the 48V positive pole input end is connected to the source of the MOS tube Q8 through a series resistor R13 and an inductor L6 in sequence, the grid of the MOS tube Q8 is connected to the pin 19 of the chip U2, the drain of the MOS tube Q8 is grounded, and the pin 13 of the chip U2 is connected to the 12V positive pole output end through a series resistor R10.
As shown in fig. 1, the other end of the inductor L2 is connected to one ends of resistors R4, R6, R12, and R13, pins 2, 12, and 23 of the chip U1, and pins 2, 12, and 23 of the chip U2, the other end of the resistor R4 is connected to one end of the inductor L3 and pin 3 of the chip U1, the other end of the resistor R6 is connected to one end of the inductor L4 and pin 11 of the chip U1, the other end of the resistor R12 is connected to one end of the inductor L5 and pin 3 of the chip U2, and the other end of the resistor R13 is connected to one end of the inductor L6 and pin 11 of the chip U2.
As shown in fig. 1, pins 4, 8, 21 of a chip U1 and pins 4, 8, 15 of a chip U2 are grounded, pin 6 of a chip U1 is connected to pin 7 of a chip U2, pin 9 of a chip U1 is connected to pin 9 of a chip U2, pin 10 of a chip U1 and pin 10 of a chip U2 are grounded through a capacitor C23, pin 14 of a chip U1 is connected to one end of a resistor R14, pin 14 of a chip U2 is connected to one end of the capacitor C26 and one end of a resistor R14, the other end of the resistor R14 is connected to one end of the capacitor C25, pin 14 of the chip U2 is connected to one end of the resistor R15, and the other ends of the resistor R15 and the capacitors C25, C26 are grounded.
As shown in fig. 1, the other end of the inductor L3 is connected to the source of the MOS transistor Q2, the drain of the MOS transistor Q3, one end of the capacitor C8 and the pin 27 of the chip U1, the gate of the MOS transistor Q3 is connected to the pin 24 of the chip U1, and the source of the MOS transistor Q3 is grounded; the other end of the inductor L4 is connected with the source of the MOS tube Q4, the drain of the MOS tube Q5, one end of the capacitor C13 and the pin 16 of the chip U1, the gate of the MOS tube Q5 is connected with the pin 17 of the chip U1, and the source of the MOS tube Q5 is grounded through the capacitor C12; the other end of the capacitor C8 is connected with the cathode of the diode D2 and the pin 25 of the chip U1, the other end of the capacitor C13 is connected with the cathode of the diode D3 and the pin 18 of the chip U1, the anodes of the diodes D2 and D3 are connected with one end of the resistor R3, one end of the capacitor C9 and the pins 7, 15 and 20 of the chip U1, the other end of the resistor R3 is connected with the pin 28 of the chip U1, and the other end of the capacitor C9 is connected with the pin 22 of the chip U1; the MOS tubes Q3 and Q5 are arranged to synchronously rectify the first main channel and the second main channel respectively.
As shown in fig. 1, the other end of the inductor L5 is connected to the source of the MOS transistor Q6, the drain of the MOS transistor Q7, one end of the capacitor C18 and the pin 27 of the chip U2, the gate of the MOS transistor Q7 is connected to the pin 24 of the chip U2, and the source of the MOS transistor Q7 is grounded; the other end of the inductor L6 is connected with the source of the MOS tube Q8, the drain of the MOS tube Q9, one end of the capacitor C24 and the pin 16 of the chip U2, the gate of the MOS tube Q9 is connected with the pin 17 of the chip U2, and the source of the MOS tube Q9 is grounded through the capacitor C22; the other end of the capacitor C18 is connected with the cathode of the diode D4 and the pin 25 of the chip U2, the other end of the capacitor C24 is connected with the cathode of the diode D5 and the pin 18 of the chip U2, the anodes of the diodes D4 and D5 are connected with one end of the resistor R11, one end of the capacitor C19 and the pin 20 of the chip U2, the other end of the resistor R11 is connected with the pin 28 of the chip U2, and the other end of the capacitor C19 is connected with the pin 22 of the chip U2; and synchronously rectifying the third main channel and the fourth main channel by arranging MOS (metal oxide semiconductor) tubes Q7 and Q9.
The maximum output current of the first main channel, the second main channel, the third main channel and the fourth main channel is 10A, and the maximum output power of the 12V positive electrode output end is 500W.
The utility model has the beneficial effects that:
(1) the utility model adopts a double-tube driving mode to form a 12V-500W charger, and the power supply of a 12V storage battery for a vehicle is satisfied, thereby realizing low cost and miniaturization;
(2) the utility model adopts the aluminum substrate PCB, thereby effectively improving the heat radiation performance and realizing natural cooling;
(3) the utility model adopts microminiature design and occupies small space.
The above-mentioned embodiments are merely descriptions of the preferred embodiments of the present invention, and do not limit the concept and scope of the present invention, and various modifications and improvements made to the technical solutions of the present invention by those skilled in the art should fall into the protection scope of the present invention without departing from the design concept of the present invention, and the technical contents of the present invention as claimed are all described in the technical claims.
Claims (9)
1. A low cost 48V-12V dc converter, comprising: the circuit comprises an aluminum substrate PCB, wherein a chip U1, a chip U2, a 48V positive input end, a 12V positive output end, a plurality of inductors, a plurality of MOS (metal oxide semiconductor) tubes and a plurality of resistors are sequentially arranged on the aluminum substrate PCB at intervals; the 48V positive input end is divided into four main channels after anti-reflection, filtering and detection;
the first path of main channel: the 48V positive electrode input end is connected to the source electrode of an MOS tube Q2 through a series resistor R4 and an inductor L3 in sequence, the grid electrode of the MOS tube Q2 is connected to a pin 26 of a chip U1, and a pin 13 of the chip U1 is connected to a 12V positive electrode output end through a series resistor R10;
the second path of main channel: the 48V positive electrode input end is connected to the source electrode of the MOS tube Q4 through a series resistor R6 and an inductor L4 in sequence, the grid electrode of the MOS tube Q4 is connected to a pin 19 of a chip U1, and a pin 13 of the chip U1 is connected to a 12V positive electrode output end through a series resistor R10;
a third main channel: the 48V positive electrode input end is connected to the source electrode of an MOS tube Q6 through a series resistor R12 and an inductor L5 in sequence, the grid electrode of the MOS tube Q6 is connected to a pin 26 of a chip U2, and a pin 13 of the chip U2 is connected to a 12V positive electrode output end through a series resistor R10;
the fourth main channel: the 48V positive pole input end is connected to the source of the MOS tube Q8 through a series resistor R13 and an inductor L6 in sequence, the gate of the MOS tube Q8 is connected to a pin 19 of the chip U2, and a pin 13 of the chip U2 is connected to a 12V positive pole output end through a series resistor R10.
2. A low cost 48V-12V dc converter as claimed in claim 1, wherein: the chip U1 and the chip U2 are both LTC 3784.
3. A low cost 48V-12V dc converter as claimed in claim 2, wherein: the device also comprises a plurality of capacitors and diodes; the 48V anode input end is connected with one end of a capacitor C5, a source electrode of a MOS tube Q1, a cathode of a diode D1 and one end of a capacitor C1, one end of a resistor R2 is connected with an anode of a diode D1 and a grid electrode of a MOS tube Q1, a drain electrode of a MOS tube Q1 and the other end of the capacitor C1 are connected with one end of an inductor L1, the other end of the inductor L1 is connected with one end of an inductor L2 and one end of the capacitor C6, the other end of the inductor L2 is connected with one end of capacitors C7 and C4 and one end of a resistor R7, the other end of the resistor R2 and the other ends of capacitors C5, C6, C7 and C4 are grounded, the other end of the resistor R7 is connected with one ends of resistors R9 and R8, the other end of the resistor R8 is connected with one end of a capacitor C2, and the other end of the capacitor C2 and the other end of the resistor R9 are grounded.
4. A low cost 48V-12V dc converter as claimed in claim 3, wherein: the other end of the inductor L2 is connected with one ends of resistors R4, R6, R12 and R13, pins 2, 12 and 23 of a chip U1 and pins 2, 12 and 23 of a chip U2, the other end of the resistor R4 is connected with one end of the inductor L3 and pin 3 of a chip U1, the other end of the resistor R6 is connected with one end of the inductor L4 and pin 11 of the chip U1, the other end of the resistor R12 is connected with one end of the inductor L5 and pin 3 of the chip U2, and the other end of the resistor R13 is connected with one end of the inductor L6 and pin 11 of the chip U2.
5. A low cost 48V-12V dc converter as claimed in claim 4, wherein: pins 4, 8 and 21 of a chip U1 and pins 4, 8 and 15 of a chip U2 are grounded, a pin 6 of a chip U1 is connected with a pin 7 of a chip U2, a pin 9 of the chip U1 is connected with a pin 9 of a chip U2, a pin 10 of a chip U1 and a pin 10 of a chip U2 are grounded through a capacitor C23, a pin 14 of a chip U1 is connected with one end of a resistor R14, a pin 14 of a chip U2 is connected with one end of the capacitor C26 and one end of a resistor R14, the other end of the resistor R14 is connected with one end of a capacitor C25, a pin 14 of the chip U2 is connected with one end of the resistor R15, and the other end of the resistor R15 and the other ends of the capacitors C25 and C26 are grounded.
6. A low cost 48V-12V dc converter as claimed in claim 5, wherein: the MOS transistor Q3 and the MOS transistor Q5 are also included; the other end of the inductor L3 is connected with the source of the MOS tube Q2, the drain of the MOS tube Q3, one end of the capacitor C8 and the pin 27 of the chip U1, the gate of the MOS tube Q3 is connected with the pin 24 of the chip U1, and the source of the MOS tube Q3 is grounded; the other end of the inductor L4 is connected with the source of the MOS tube Q4, the drain of the MOS tube Q5, one end of the capacitor C13 and the pin 16 of the chip U1, the gate of the MOS tube Q5 is connected with the pin 17 of the chip U1, and the source of the MOS tube Q5 is grounded through the capacitor C12; the other end of the capacitor C8 is connected with the cathode of the diode D2 and the pin 25 of the chip U1, the other end of the capacitor C13 is connected with the cathode of the diode D3 and the pin 18 of the chip U1, the anodes of the diodes D2 and D3 are connected with one end of the resistor R3, one end of the capacitor C9 and the pins 7, 15 and 20 of the chip U1, the other end of the resistor R3 is connected with the pin 28 of the chip U1, and the other end of the capacitor C9 is connected with the pin 22 of the chip U1; the MOS tubes Q3 and Q5 are arranged to synchronously rectify the first main channel and the second main channel respectively.
7. A low cost 48V-12V dc converter as claimed in claim 5, wherein: the MOS transistor Q7 and the MOS transistor Q9 are also included; the other end of the inductor L5 is connected with the source of the MOS tube Q6, the drain of the MOS tube Q7, one end of the capacitor C18 and the pin 27 of the chip U2, the gate of the MOS tube Q7 is connected with the pin 24 of the chip U2, and the source of the MOS tube Q7 is grounded; the other end of the inductor L6 is connected with the source of the MOS tube Q8, the drain of the MOS tube Q9, one end of the capacitor C24 and the pin 16 of the chip U2, the gate of the MOS tube Q9 is connected with the pin 17 of the chip U2, and the source of the MOS tube Q9 is grounded through the capacitor C22; the other end of the capacitor C18 is connected with the cathode of the diode D4 and the pin 25 of the chip U2, the other end of the capacitor C24 is connected with the cathode of the diode D5 and the pin 18 of the chip U2, the anodes of the diodes D4 and D5 are connected with one end of the resistor R11, one end of the capacitor C19 and the pin 20 of the chip U2, the other end of the resistor R11 is connected with the pin 28 of the chip U2, and the other end of the capacitor C19 is connected with the pin 22 of the chip U2; and synchronously rectifying the third main channel and the fourth main channel by arranging MOS (metal oxide semiconductor) tubes Q7 and Q9.
8. A low cost 48V-12V dc converter as claimed in claim 5, wherein: the drain of the MOS transistor Q2 is grounded via a capacitor C3, the drain of the MOS transistor Q4 is grounded, the drain of the MOS transistor Q6 is grounded via a capacitor C17, and the drain of the MOS transistor Q8 is grounded.
9. A low cost 48V-12V dc converter as claimed in claim 5, wherein: the maximum output current of the first main channel, the second main channel, the third main channel and the fourth main channel is 10A, and the maximum output power of the 12V positive electrode output end is 500W.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120444485.9U CN215420101U (en) | 2021-03-02 | 2021-03-02 | Low-cost 48V-12V direct current converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120444485.9U CN215420101U (en) | 2021-03-02 | 2021-03-02 | Low-cost 48V-12V direct current converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215420101U true CN215420101U (en) | 2022-01-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120444485.9U Expired - Fee Related CN215420101U (en) | 2021-03-02 | 2021-03-02 | Low-cost 48V-12V direct current converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215420101U (en) |
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2021
- 2021-03-02 CN CN202120444485.9U patent/CN215420101U/en not_active Expired - Fee Related
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Granted publication date: 20220104 |