CN215340236U - Multi-path load board circuit - Google Patents
Multi-path load board circuit Download PDFInfo
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- CN215340236U CN215340236U CN202121673062.0U CN202121673062U CN215340236U CN 215340236 U CN215340236 U CN 215340236U CN 202121673062 U CN202121673062 U CN 202121673062U CN 215340236 U CN215340236 U CN 215340236U
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Abstract
The utility model provides a multi-path load board circuit which comprises a BUCK circuit and a plurality of load circuits, wherein the BUCK circuit is respectively connected with the load circuits, the load circuits comprise a voltage regulating unit, a signal processing unit and a voltage output unit which are sequentially connected, and the voltage output unit of each load circuit outputs different voltage values. The structure of a plurality of load circuits is the same, and the test requirements of various power supplies during PMU integrity test can be realized by changing the resistance value of the power resistor and the input voltage Verf of the operational amplifier.
Description
Technical Field
The utility model relates to the technical field of PMU power integrity testing, in particular to a multi-path load board circuit.
Background
With the rapid development of the internet, the cloud computing technology is continuously rising, the network service volume is continuously increased, and the application of electronic products such as servers is also gradually increased. Correspondingly, the use of PCIe (peripheral component interconnect express) cards having functions of image processing, video decoding, acceleration, etc. is increasing. These PCIe cards are commonly used as low-Power, high-performance processor chips, and need to be supplied with a fixed PMU (Power Management Unit). These PMUs can output multiple sets of BUCKs, LDOs and Switchs at the same time, and have the characteristics of multiple output power types and small current.
The E-Load (electronic Load) used by the SV power integrity test at present is only suitable for supplying a single-path (at most three paths) large-current electronic Load.
All E-loads are usually used for large currents, and have limited channels, which cannot meet the test requirement of simultaneous loading of multiple low current outputs of PMUs.
SUMMERY OF THE UTILITY MODEL
The utility model provides a multi-path load board circuit which is used for solving the problem that the existing PMU power integrity test means cannot meet the test requirement.
In order to achieve the purpose, the utility model adopts the following technical scheme:
the utility model provides a multi-path load board circuit which comprises a BUCK circuit and a plurality of load circuits, wherein the BUCK circuit is respectively connected with the load circuits, the load circuits comprise a voltage regulating unit, a signal processing unit and a voltage output unit which are sequentially connected, and the voltage output unit of each load circuit outputs different voltage values.
Further, the BUCK circuit includes a first BUCK circuit converting the 12V voltage into a 0.6V voltage and a second BUCK circuit converting the 12V voltage into a 3.3V voltage; the output end of the first BUCK circuit is connected with the voltage regulating unit, and the output end of the second BUCK circuit is connected with the signal processing unit.
Further, the voltage adjusting unit includes a resistor R25 and a variable resistor U4, one end of the resistor R25 is connected to the 0.6V power supply, the other end is connected to the signal processing unit and the 1 pin of the variable resistor U4, respectively, and the 3 pin of the variable resistor U4 is connected to the signal processing unit and the ground, respectively.
Further, the signal processing unit comprises an operational amplifier U6, a MOS transistor Q2 and a power resistor R29, wherein a V + pin of the operational amplifier U6 is connected with a 3.3V power supply, a V-pin is grounded, a + IN pin is connected with the other end of the resistor R25, an IN pin is connected with one end of the power resistor R29, an OUTPUT pin is connected with a grid of the MOS transistor Q2 through a resistor R27, a source of the MOS transistor Q2 is connected with one end of the power resistor R29, a drain OUTPUT voltage VOUT, and the other end of the power resistor R29 is grounded.
Furthermore, the voltage output power supply comprises a filter circuit, the filter circuit comprises a plurality of capacitors connected in parallel, one end of the filter circuit is connected with the output voltage VOUT, and the other end of the filter circuit is grounded; the two ends of the filter circuit are also used for connecting a load.
Further, the load board circuit further comprises a display circuit, the display circuit comprises an MOS tube Q17, a light emitting diode LED and a resistor R68, the grid electrode of the MOS tube Q17 is connected with the output voltage VOUT, the source electrode is grounded, and the drain electrode is connected with a 3.3V power supply sequentially through the light emitting diode LED and the resistor R68.
Further, the BUCK circuit comprises a BUCK converter, and the model of the BUCK converter is TPS53318 DQPR.
The effects provided in the contents of the present invention are only the effects of the embodiments, not all the effects of the present invention, and one of the above technical solutions has the following advantages or advantageous effects:
the multi-load board designed by the utility model has the same structure of a plurality of load circuits, and can realize the test requirements of various power supplies during PMU integrity test by changing the resistance value of the power resistor and the input voltage Verf of the operational amplifier.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of the structure of a load board circuit according to the present invention;
FIG. 2 is a circuit diagram of a first BUCK circuit of the present invention;
FIG. 3 is a circuit diagram of a second BUCK circuit of the present invention;
FIG. 4 is a circuit diagram of the load circuit of the present invention;
fig. 5 is a circuit diagram of a display circuit according to the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the utility model. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the utility model.
The utility model provides a multi-path load board circuit, which comprises a BUCK circuit and a plurality of load circuits, wherein the BUCK circuit is respectively connected with the load circuits, the load circuits comprise a voltage regulating unit, a signal processing unit and a voltage output unit which are sequentially connected, and the voltage output unit of each load circuit outputs different voltage values.
To meet the testing requirements for PMU power integrity, take the PMU RK808 of RockChip as an example. The PMU can simultaneously output 4 groups of Buck power supplies, 8 groups of LDOs and 2 groups of switches, and 14 groups of outputs simultaneously supply power to the main chip. Correspondingly, 14 load circuits are required.
As shown in fig. 2 and 3, the BUCK circuit includes a first BUCK circuit that converts a 12V voltage into a 0.6V voltage and a second BUCK circuit that converts a 12V voltage into a 3.3V voltage; the output end of the first BUCK circuit is connected with the voltage regulating unit, and the output end of the second BUCK circuit is connected with the signal processing unit.
The BUCK circuit includes a BUCK converter, model number TPS53318 DQPR. The peripheral circuits shown in fig. 2 and 3 are connected to reduce the voltage of 12V to 0.6V and 3.3V respectively, so as to supply power for the load circuit.
As shown in fig. 4, a load circuit will be described as an example. The voltage adjusting unit of the load circuit comprises a resistor R25 and a variable resistor U4, wherein one end of the resistor R25 is connected with a 0.6V power supply, the other end of the resistor R25 is respectively connected with the signal processing unit and a 1 pin of the variable resistor U4, and a 3 pin of the variable resistor U4 is respectively connected with the signal processing unit and the ground.
The signal processing unit comprises an operational amplifier U6, a MOS tube Q2 and a power resistor R29, wherein a V + pin of the operational amplifier U6 is connected with a 3.3V power supply, a V-pin is grounded, a + IN pin is connected with the other end of the resistor R25, an IN pin is connected with one end of the power resistor R29, an OUTPUT pin is connected with the grid of the MOS tube Q2 through a resistor R27, the source of the MOS tube Q2 is connected with one end of the power resistor R29, the drain OUTPUTs voltage VOUT, and the other end of the power resistor R29 is grounded.
The voltage output power supply comprises a filter circuit, the filter circuit comprises a plurality of capacitors connected in parallel, one end of the filter circuit is connected with the output voltage VOUT, and the other end of the filter circuit is grounded; the two ends of the filter circuit are also used for connecting a load.
The working principle of the load circuit is as follows: when the voltage V1 on the power resistor R29 is smaller than Vref1, the-IN of the operational amplifier U6 is smaller than + IN, the operational amplifier increases the output, the MOS transistor Q2 increases the conduction degree, and the current increases; when the voltage V1 on the R29 is smaller than Vref1, the-IN of the operational amplifier U6 is larger than + IN, the operational amplifier reduces the output, the Q2 reduces the derivation degree, and the current is reduced. As such, the current on the loop may always be equal to Vref 1/R28.
U4 is a variable resistor and adjusting the U4 resistance value sets the value of Vref 1. If the load demand is 5A, Vref1 should be set to 5A x 0.05 ohm-0.25V. When Vref1 is 0.25V, the resistance of variable resistor U4 should be set to 7.14 k.
The load circuit has a load current range: the rated power of the power resistor R28 is 5W, and the maximum current passing through the power resistor R28 is 10A; the voltage adjustable range of Vref1 is 0.029-0.594V, and the adjustable current range is 0.58-11.89A; the rated current range of the load circuit is 0.58-10A by combining two conditions. Similarly, for other groups of load circuits, the rated current range of the load circuit can be adjusted by changing the size of the power resistor. To meet the testing requirements for PMU power integrity.
As shown in fig. 5, the load board circuit further includes a display circuit for displaying the state of the output voltage VOUT. Taking the display VOUT1 as an example, the display circuit includes a MOS transistor Q17, a light emitting diode LED and a resistor R68, the gate of the MOS transistor Q17 is connected to the output voltage VOUT, the source is grounded, and the drain is connected to the 3.3V power supply through the light emitting diode LED and the resistor R68 in sequence.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (7)
1. The multichannel load board circuit is characterized by comprising a BUCK circuit and a plurality of load circuits, wherein the BUCK circuit is respectively connected with the load circuits, each load circuit comprises a voltage regulating unit, a signal processing unit and a voltage output unit which are sequentially connected, and the voltage output unit of each load circuit outputs different voltage values.
2. The multi-load board circuit of claim 1, wherein the BUCK circuit comprises a first BUCK circuit that converts a 12V voltage to a 0.6V voltage and a second BUCK circuit that converts a 12V voltage to a 3.3V voltage; the output end of the first BUCK circuit is connected with the voltage regulating unit, and the output end of the second BUCK circuit is connected with the signal processing unit.
3. The multi-load board circuit of claim 1, wherein the voltage regulating unit comprises a resistor R25 and a variable resistor U4, one end of the resistor R25 is connected to a 0.6V power supply, the other end is connected to the signal processing unit and a 1 pin of the variable resistor U4, and a 3 pin of the variable resistor U4 is connected to the signal processing unit and the ground.
4. The multi-load board circuit of claim 3, wherein the signal processing unit comprises an operational amplifier U6, a MOS transistor Q2 and a power resistor R29, the V + pin of the operational amplifier U6 is connected to a 3.3V power supply, the V-pin is grounded, the + IN pin is connected to the other end of the resistor R25, the IN pin is connected to one end of the power resistor R29, the OUTPUT pin is connected to the gate of the MOS transistor Q2 through a resistor R27, the source of the MOS transistor Q2 is connected to one end of the power resistor R29, the drain OUTPUT voltage VOUT, and the other end of the power resistor R29 is grounded.
5. The multi-load-board circuit of claim 4, wherein the voltage output unit comprises a filter circuit, the filter circuit comprises a plurality of capacitors connected in parallel, one end of the filter circuit is connected to the output voltage VOUT, and the other end of the filter circuit is grounded; the two ends of the filter circuit are also used for connecting a load.
6. The multi-load-board circuit of claim 5, further comprising a display circuit, wherein the display circuit comprises a MOS transistor Q17, a Light Emitting Diode (LED) and a resistor R68, the gate of the MOS transistor Q17 is connected to the output voltage VOUT, the source is grounded, and the drain is connected to a 3.3V power supply sequentially through the LED and the resistor R68.
7. The multi-load board circuit of claim 1, wherein the BUCK circuit comprises a BUCK converter having a model number TPS53318 DQPR.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121673062.0U CN215340236U (en) | 2021-07-22 | 2021-07-22 | Multi-path load board circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121673062.0U CN215340236U (en) | 2021-07-22 | 2021-07-22 | Multi-path load board circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215340236U true CN215340236U (en) | 2021-12-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121673062.0U Active CN215340236U (en) | 2021-07-22 | 2021-07-22 | Multi-path load board circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215340236U (en) |
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2021
- 2021-07-22 CN CN202121673062.0U patent/CN215340236U/en active Active
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