CN215268098U - SOC integrated circuit device for composite micro-energy collection - Google Patents

Abstract

The utility model discloses a SOC integrated circuit device for compound micro energy is collected belongs to compound micro energy and collects the field, and its CMOS full wave rectifier circuit module input termination piezoelectricity-photoelectric energy collector's original alternating current output exports for the following CMOS energy collection circuit module of direct current access, in the energy storage after the preceding stage full wave rectification is collected to CMOS energy collection circuit module arrived its preceding stage buffering small capacitance, in the energy storage of CMOS energy storage circuit module in with preceding stage buffering small capacitance arrived its back stage buffering large capacitance, the energy conversion in the big capacitance of back stage buffering is stable voltage for back load power supply to CMOS voltage stabilizing circuit module. The utility model discloses an electric capacity is as storage medium, with all circuit integration on a chip, and the size is little, the low power dissipation.

Description

SOC integrated circuit device for composite micro-energy collection

Technical Field

The utility model relates to a SOC integrated circuit device for compound little energy is collected belongs to compound little energy and collects the field.

Background

At present, in order to reduce the degree of dependence on fossil energy, energy collection technology becomes increasingly important, especially the collection of some micro-energy, for example, wearable devices today can bring great convenience to human life. However, such devices have a small volume, and the batteries with large configuration have high cost, and the energy collection system has an excessively large volume, poor integration level, low efficiency and inconvenient use.

Disclosure of Invention

In order to compensate prior art's shortcoming, the utility model provides a small, with low costs, for the SOC integrated circuit device that is used for compound little energy to collect of wearable equipment power supply.

The utility model discloses a technical scheme:

the utility model relates to a SOC integrated circuit device for compound micro energy is collected, it includes piezoelectricity-photoelectricity energy collector and SOC integrated circuit module, piezoelectricity-photoelectricity energy collector is connected with SOC integrated circuit module;

the SOC integrated circuit module comprises a CMOS full-wave rectifying circuit module, a CMOS energy collecting circuit module, a CMOS energy storage circuit module and a CMOS voltage stabilizing circuit module, wherein the input end of the CMOS full-wave rectifying circuit module is connected with the original alternating current output of the piezoelectric-photoelectric energy collector, the output of the CMOS full-wave rectifying circuit module is direct current and is connected to the CMOS energy collecting circuit module behind, the CMOS energy collecting circuit module collects energy obtained after front-stage full-wave rectification and stores the energy into a front-stage buffer small capacitor, the CMOS energy storage circuit module stores the energy in the front-stage buffer small capacitor C2 into a rear-stage buffer large capacitor, and the voltage stabilizing circuit module converts the energy in the rear-stage buffer large capacitor into stable voltage to supply power to a rear load.

Further, the piezoelectric-photovoltaic energy collector comprises a piezoelectric energy collector and a photovoltaic energy collector, the piezoelectric energy collector is directly connected with the SOC integrated circuit module, and the photovoltaic energy collector is connected with the SOC integrated circuit module through a diode.

Furthermore, the CMOS full-wave rectification circuit module is composed of N-type MOS transistors Q1 and Q3 and P-type MOS transistors Q2 and Q4, and the Q1, the Q2, the Q3 and the Q4 are all ultra-low power consumption CMOS devices.

Further, the CMOS energy collecting circuit module comprises a Schmitt trigger control circuit, a resistor R1, a small buffer capacitor, an N-type MOS tube Q10 and a P-type MOS tube Q9; the Schmitt trigger control circuit is controlled by a CMOS Schmitt trigger, and the small buffer capacitor comprises a capacitor C1 and a capacitor C2;

one end of the capacitor C1 is connected to the output end Vio of the energy collector, and the other end of the capacitor C1 is grounded; one end of the capacitor C2 is connected with the input end of the CMOS Schmitt trigger and the drain electrode of the P-type MOS tube Q9, and the other end is grounded;

one end of the R1 is connected with the output end Vio of the CMOS energy collecting circuit module, the other end is connected with the drain electrode of an N-type MOS tube Q10, the grid electrode of the N-type MOS tube Q10 is connected with the output Vio of the CMOS energy collecting circuit module, the source electrode is grounded, the drain electrode is connected with one end of a resistor R1, the grid electrode of the N-type MOS tube Q10 is connected with the drain electrode of a P-type MOS tube Q9, the source electrode is connected with the output Vio of the CMOS energy collecting circuit module, the drain electrode is connected with the positive electrode end of a capacitor C2, a power supply of the Schmidt trigger is connected with the output Vio end of the CMOS energy collecting circuit module, the input end is connected with the positive electrode of the capacitor C2, Vin1, namely, micro-energy signals needing to be collected are provided, the output end of the Schmidt trigger provides enabling signals EN for the chip, and the GND port is grounded.

Further, the CMOS schmitt trigger comprises P-type MOS transistors Q11, Q12, Q15, N-type MOS transistors Q13, Q14, and Q16, the P-type MOS transistors and the N-type MOS transistors are clamped to each other, so that the front-stage small capacitor C1 is preferentially charged to supply power to the CMOS schmitt trigger, the rear-stage small buffer capacitor C2 is charged when the voltage of the buffer small capacitor C1 reaches a certain threshold, and the buffer small capacitor C2 outputs energy to the CMOS energy storage circuit module when the voltage of the buffer small capacitor C2 reaches the control voltage of the CMOS schmitt trigger.

Further, the CMOS energy storage circuit module comprises a basic boost circuit, a buffer large capacitor, resistors R3, R4, R5, R6, R7, R8, a comparator I, an error amplifier I, a voltage reference source I and a sawtooth wave generator I, wherein the comparator I comprises a MOS tube Q36, a MOS tube Q37, a MOS tube Q38, a MOS tube Q39, a MOS tube Q40, a MOS tube Q41, a CMOS tube Q42 and a CMOS tube Q43, a current source circuit consisting of MOS tubes Q44 to Q55, a Q39 in the current source is connected with the drain terminals of the Q47 and the Q48, a Q40 in the current source is connected with the grid terminal of the Q55 and the drain terminal of the MOS tube Q54, and therefore bias current is supplied to the whole differential amplifier; the error amplifier I is composed of a current source circuit composed of MOS transistors Q22 to Q27 and a secondary operational amplifier with Miller compensation composed of MOS transistors Q28 to Q35, wherein the grid electrode of Q22 of the current source is connected with the grid electrodes of Q28 and Q34, and suitable bias current is provided for the secondary operational amplifier; the voltage reference I is composed of MOS transistors Q55-Q59, resistors R11, R12, transistors Q60, Q61 and Q62, and the output end Vref of the voltage reference I provides voltage reference for the chip; the sawtooth wave generator I is composed of Q62, Q63, Q64, Q65 and Q66, resistors R13, R14, R15, R16 and R17, capacitors C7 and C8 and a comparator III.

Further, the buffer large capacitor comprises a capacitor C4 and a capacitor C5.

Further, the CMOS energy storage circuit module adopts a boost circuit to boost the input voltage to 1.8V to 5.5V, and is suitable for charging the capacitors C4 and C5.

Further, the voltage stabilizing circuit comprises a basic buck-boost circuit, resistors R18, R19, R20, R21, a comparator II, an error amplifier II, a voltage reference II and a sawtooth wave generator II, wherein the comparator II is composed of a current source circuit composed of MOS transistors Q86, Q87, Q88, Q89, Q90, Q91, Q92 and Q93 and a differential amplifier composed of MOS transistors Q94 to Q105, Q89 in the current source is connected to the drain terminals of Q97 and Q98, Q90 in the current source is connected to the gate terminal of Q105 and the drain terminal of Q104, so that bias current is provided for the whole differential amplifier; the error amplifier II is composed of a current source circuit composed of MOS transistors Q72 to Q77 and a second-stage operational amplifier with Miller compensation composed of MOS transistors Q78 to Q85, wherein the grid electrode of Q72 of the current source is connected with the grid electrodes of Q78 and Q84, and suitable bias current is provided for the operational amplifier; the voltage reference II is composed of MOS transistors Q106 to Q110, resistors R24 and R25, transistors Q111, Q112 and Q113, and an output end REF of the voltage reference II provides voltage reference for the chip; the sawtooth wave generator II is composed of Q114, Q115, Q116, Q117 and Q118, resistors R26, R27, R28, R29, R30, capacitors C11 and C12 and a comparator IV.

Further, the CMOS voltage stabilizing circuit module adopts a buck-boost circuit to convert the voltage from 1.8V to 5.5V into the voltage of 5V to continuously supply power to a rear-end load and a battery.

Advantageous effects

The SOC integrated circuit chip for collecting the piezoelectric-photoelectric composite micro energy can achieve the following effects:

firstly, the energy in two forms of piezoelectricity and photoelectricity can be compositely collected at the same time, and the energy of human body movement is collected;

secondly, the CMOS process is adopted, the power consumption is low, the efficiency is high, the circuit size of the SOC chip is greatly reduced, the capacitor is adopted as a storage medium in the aspect of energy storage, power supply for wearable equipment is facilitated, and the market value is high.

Drawings

Fig. 1 is a CMOS circuit diagram of an SOC integrated circuit device for composite micro energy collection according to the present invention;

FIG. 2 is a schematic diagram of a circuit configuration of the CMOS full-wave rectifier circuit module of FIG. 1;

FIG. 3 is a schematic circuit diagram of the CMOS energy harvesting circuit module of FIG. 1;

FIG. 4 is an internal block diagram of the CMOS energy storage circuit block of FIG. 1;

FIG. 5 is an internal block diagram of the CMOS voltage regulator circuit of FIG. 1;

FIG. 6 is a circuit diagram of a CMOS error amplifier I in an energy storage circuit;

FIG. 7 is a circuit diagram of a CMOS comparator I in the energy storage circuit;

FIG. 8 is a circuit configuration diagram of a CMOS comparator III in a sawtooth generator I;

FIG. 9 is a circuit diagram of a voltage reference I in the energy storage circuit;

FIG. 10 is a schematic diagram of the generation circuit of a sawtooth generator I of the energy storage circuit;

FIG. 11 is a circuit diagram of a CMOS error amplifier II in a voltage regulator circuit;

FIG. 12 is a circuit configuration diagram of a CMOS comparator II in the voltage regulator circuit;

FIG. 13 is a circuit configuration diagram of a CMOS comparator IV in a sawtooth wave generator II;

FIG. 14 is a circuit configuration diagram of a voltage reference II of the voltage regulator circuit;

fig. 15 is a diagram showing a generating circuit configuration of a sawtooth wave generator ii in the voltage regulator circuit.

Detailed Description

The invention is further described below with reference to the drawings and specific preferred embodiments.

The utility model relates to a SOC integrated circuit device for compound micro energy is collected, it includes piezoelectricity-photoelectric energy collector and SOC integrated circuit module, piezoelectricity-photoelectric energy collector and SOC integrated circuit module lug connection. The piezoelectric-photoelectric energy collector can convert energy brought by solar energy and pressure into weak electric energy. The piezoelectric-photoelectric energy collector comprises a piezoelectric energy collector and a photoelectric energy collector, the piezoelectric energy collector is directly connected with the SOC integrated circuit module, and the photoelectric energy collector is connected with the SOC integrated circuit module through a diode D1.

The SOC integrated circuit module comprises a CMOS full-wave rectifying circuit module, a CMOS energy collecting circuit module, a CMOS energy storage circuit module and a CMOS voltage stabilizing circuit module. The CMOS full-wave rectifying circuit module inputs original alternating current output of the piezoelectric-photoelectric energy collector and outputs direct current to a CMOS energy collecting circuit module behind the piezoelectric-photoelectric energy collector, the CMOS energy collecting circuit module collects energy after front-stage full-wave rectification and stores the energy into a front-stage buffer small capacitor C2, the CMOS energy storage circuit module stores energy in a front-stage buffer small capacitor C2 into rear-stage buffer large capacitors C4 and C5, and the CMOS voltage stabilizing circuit module converts energy in the rear-stage buffer large capacitors C4 and C5 into stable voltage to supply power to a rear load. The Vio of the whole circuit is connected with the output end of the CMOS full-wave rectifying circuit module. Most devices of the whole SOC integrated circuit device are integrated by adopting MOS devices, and the rectifier tube adopts an ultra-low power consumption CMOS device, so that the energy loss is low and the speed is high. The CMOS energy collecting circuit module is controlled by a CMOS Schmitt trigger, the CMOS energy storage circuit module adopts a boost circuit and a voltage storage unit with a capacitor as a medium, and the CMOS voltage stabilizing circuit module adopts a buck-boost circuit.

In this embodiment, the CMOS full-wave rectifier circuit module adopts an ultra-low power consumption CMOS rectifier circuit, as shown in fig. 2, which is composed of N-type MOS transistors Q1 and Q3 and P-type MOS transistors Q2 and Q4, and the rectifier transistors Q1, Q2, Q3, and Q4 are ultra-low power consumption CMOS devices, so that the power consumption is low and the speed is high. When weak electric signals Vpiezo and Vphoto collected from the outside pass through the input end of the rectifying circuit, a voltage similar to direct current is generated at the output end and then is supplied to the CMOS energy collecting circuit at the rear.

In this embodiment, the CMOS energy collection circuit module includes a schmitt trigger control circuit, a small buffer capacitor, a resistor R1, an N-type MOS transistor Q10, and a P-type MOS transistor Q9, where the schmitt trigger control circuit is controlled by a CMOS schmitt trigger, and the small buffer capacitor includes a capacitor C1 and a capacitor C2, which are storage media, as shown in fig. 3. The CMOS Schmitt trigger is composed of P-type MOS transistors Q11, Q12, Q15, N-type MOS transistors Q13, Q14 and Q16, as shown in FIG. 3, the P-type MOS transistors and the N-type MOS transistors are clamped mutually, so that a front-stage buffer small capacitor C1 is charged preferentially to supply power to the CMOS Schmitt trigger, a rear-stage buffer small capacitor C2 is charged after the voltage of a front-stage buffer small capacitor C1 reaches a certain threshold value, and the rear-stage buffer small capacitor C2 outputs energy to the CMOS energy storage circuit module after the voltage of a rear-stage buffer small capacitor C2 reaches the control voltage of the CMOS Schmitt trigger.

Specifically, one end of the capacitor C1 is connected to the output terminal Vio of the energy collector, and the other end is grounded. One end of the capacitor C2 is connected with the input end of the CMOS Schmidt trigger and the drain electrode of the P-type MOS tube Q9, and the other end is grounded. One end of the R1 is connected with the output end Vio of the energy collector, the other end is connected with the drain electrode of an N-type MOS tube Q10, the grid electrode of the N-type MOS tube Q10 is connected with the output Vio of the energy collector, the source electrode is grounded, the drain electrode is connected with one end of a resistor R1, the grid electrode of the N-type MOS tube Q10 is connected with the drain electrode of a P-type MOS tube Q9, the source electrode is connected with the output Vio of the energy collector, the drain electrode is connected with the positive electrode end of a capacitor C2, the power supply of the Schmidt trigger is connected with the output Vio end of the energy collector, the input end is connected with the positive electrode of the capacitor C2, Vin1 is provided, namely, a micro-energy signal needing to be collected, the output end of the Schmidt trigger provides an enabling signal EN for a chip, and the GND port is grounded.

In this embodiment, the CMOS energy storage circuit module includes a basic boost circuit, a buffer large capacitor, a resistor R3, R4, R5, R6, R7, R8, a comparator i, an error amplifier i, a voltage reference source i, and a sawtooth wave generator i, as shown in fig. 4, the buffer large capacitor includes a capacitor C4 and a capacitor C5. The comparator I circuit is shown in FIG. 5, and is composed of a current source circuit composed of MOS transistors Q36, Q37, Q38, Q39, Q40, Q41, Q42 and Q43 and a differential amplifier composed of MOS transistors Q44 to Q55, wherein Q39 in the current source is connected to the drain terminals of Q47 and Q48, and Q40 in the current source is connected to the gate terminal of Q55 and the drain terminal of Q54, so that bias current is provided for the whole differential amplifier. As shown in fig. 6, the error amplifier i circuit is composed of a current source circuit composed of MOS transistors Q22 to Q27 and a second-stage operational amplifier with miller compensation composed of MOS transistors Q28 to Q35, wherein the gate of the Q22 of the current source is connected to the gates of Q28 and Q34, so as to provide a proper bias current for the second-stage operational amplifier. The voltage reference i circuit is shown in fig. 7 and is composed of MOS transistors Q55 to Q59, resistors R11 and R12, transistors Q60, Q61, and Q62, and its output terminal Vref provides a voltage reference for the chip. The sawtooth wave generator I is composed of Q62, Q63, Q64, Q65 and Q66, resistors R13, R14, R15, R16, R17, capacitors C7 and C8 and a comparator III as shown in FIG. 8, and the comparator III is shown in FIG. 9. When the whole circuit works, an input signal Vin1 generated by an energy collecting circuit is boosted through a basic boost circuit, then storage of a capacitor C4 and a capacitor C5 in the later stage is started, an output signal is sampled by R3 and R4, the sampled signal is connected to the reverse input end of an error amplifier I through a resistor R6, the output of a voltage reference I is connected to the same-direction input end of the error amplifier I, the error amplifier I amplifies the error signals of the two and then sends the amplified error signals to the non-inverting input end of a comparator, the reverse input end of the comparator I is connected with the output of a sawtooth wave generator I, then a PWM signal is output from the output end of the comparator I, and a push-pull circuit composed of Q18 and Q19 is driven, so that the whole circuit is subjected to loop control, and the whole stability is improved.

The CMOS energy storage circuit module adopts a boost circuit to boost the input weak voltage to the voltage of 1.8V to 5.5V, and charges the rear-stage buffer large capacitors C4 and C5.

In this embodiment, the voltage regulator circuit includes a basic buck-boost circuit, resistors R18, R19, R20, R21, a comparator ii, an error amplifier ii, a voltage reference ii, and a sawtooth wave generator ii, as shown in fig. 10. The comparator ii circuit is shown in fig. 11, and is composed of a current source circuit composed of MOS transistors Q86, Q87, Q88, Q89, Q90, Q91, Q92, and Q93, and a differential amplifier composed of MOS transistors Q94 to Q105, wherein Q89 of the current source is connected to the drain terminals of Q97 and Q98, and Q90 of the current source is connected to the gate terminal of Q105 and the drain terminal of Q104, so as to supply bias current to the entire differential amplifier. The error amplifier ii circuit is composed of a current source circuit composed of MOS transistors Q72 to Q77 and a miller-compensated two-stage operational amplifier composed of MOS transistors Q78 to Q85, as shown in fig. 12, wherein the gate of the Q72 of the current source is connected to the gates of Q78 and Q84, so as to provide a proper bias current for the operational amplifier. The voltage reference ii circuit is shown in fig. 13 and is composed of MOS transistors Q106 to Q110, resistors R24 and R25, and transistors Q111, Q112, and Q113, and its output terminal REF provides a voltage reference for the chip. The sawtooth wave generator ii is shown in fig. 14 and is composed of Q114, Q115, Q116, Q117, Q118, resistors R26, R27, R28, R29, R30 capacitors C11, C12, and a comparator iv, which is shown in fig. 15. When the whole circuit works, an input signal Vin2 generated by a boost circuit is stabilized through a basic buck-boost circuit, then, VOUT starts to supply power to a backward-stage load, R18 and R19 sample an output signal, the sampled signal is connected to the reverse input end of an error amplifier II through a resistor R20, the output of a voltage reference II is connected to the same-direction input end of the error amplifier II, the error amplifier II amplifies the error signal of the error amplifier II and then sends the amplified signal to the non-inverting input end of a comparator II, the reverse input end of the comparator II is connected with the output of a sawtooth wave generator II, then a PWM signal is output from the output end of the comparator II, and then a push-pull circuit composed of Q70 and Q71 is driven, so that the whole circuit is subjected to loop control, and the whole stability is improved.

The CMOS voltage stabilizing circuit module adopts a buck-boost circuit to convert the voltage from 1.8V to 5.5V into the voltage of 5V so as to continuously supply power to a rear-end load and a battery.

In this embodiment, the comparator, the error amplifier, the voltage reference, and the sawtooth wave generator used in the boost circuit and the buck-boost circuit module may be of the same type. Most devices of the whole system are integrated by adopting MOS devices.

In this embodiment, VIN + and VIN-in the specific circuits of the comparator, the error amplifier, the voltage reference and the sawtooth wave generator have no connection relationship, and are only shown as the homodromous input terminal + and the inverse input terminal-in the respective circuits.

The utility model relates to a SOC integrated circuit device for compound micro energy is collected is applicable to two kinds of energy collection modes of piezoelectricity and photoelectricity, and two kinds of energy of piezoelectricity and photoelectricity can be collected simultaneously to the energy collection circuit, has the commonality, can insert a plurality of piezoelectricity-photoelectricity energy collectors simultaneously, inserts through CMOS full wave rectifier circuit module, has simplified the energy collection circuit, and low power dissipation, small, the function is strong, efficient, long having very big promotion during to current wearable equipment's continuation of the journey.

Above only the utility model discloses an it is preferred embodiment, the utility model discloses a scope of protection not only limits in above-mentioned embodiment, and the all belongs to the utility model discloses a technical scheme under the thinking all belongs to the utility model discloses a scope of protection. It should be noted that, for those skilled in the art, a plurality of modifications and decorations without departing from the principle of the present invention should be considered as the protection scope of the present invention.

Claims (9)

1. An SOC integrated circuit device for composite micro-energy harvesting, characterized by: the system comprises a piezoelectric-photoelectric energy collector and an SOC integrated circuit module, wherein the piezoelectric-photoelectric energy collector comprises a piezoelectric energy collector and a photoelectric energy collector, the piezoelectric energy collector is directly connected with the SOC integrated circuit module, the photoelectric energy collector is connected with the SOC integrated circuit module through a diode D1, and the piezoelectric-photoelectric energy collector is connected with the SOC integrated circuit module;

the SOC integrated circuit module comprises a CMOS full-wave rectifying circuit module, a CMOS energy collecting circuit module, a CMOS energy storage circuit module and a CMOS voltage stabilizing circuit module, wherein the input end of the CMOS full-wave rectifying circuit module is connected with the original alternating current output of a piezoelectric-photoelectric energy collector, the output of the CMOS full-wave rectifying circuit module is direct current and is connected to the CMOS energy collecting circuit module behind, the CMOS energy collecting circuit module collects energy obtained after front-stage full-wave rectification and stores the energy into a front-stage buffer small capacitor, the CMOS energy storage circuit module stores the energy in the front-stage buffer small capacitor into a rear-stage buffer large capacitor, and the voltage stabilizing circuit module converts the energy in the rear-stage buffer large capacitor into stable voltage to supply power to a rear load.

2. The SOC integrated circuit device of claim 1, wherein: the CMOS full-wave rectifying circuit module is composed of N-type MOS tubes Q1 and Q3 and P-type MOS tubes Q2 and Q4, and the Q1, the Q2, the Q3 and the Q4 are all ultra-low power consumption CMOS devices.

3. The SOC integrated circuit device of claim 1, wherein: the CMOS energy collecting circuit module comprises a Schmitt trigger control circuit, a resistor R1, a small buffer capacitor, an N-type MOS tube Q10 and a P-type MOS tube Q9; the Schmitt trigger control circuit is controlled by a CMOS Schmitt trigger, and the small buffer capacitor comprises a capacitor C1 and a capacitor C2;

one end of the capacitor C1 is connected to the output end Vio of the energy collector, and the other end of the capacitor C1 is grounded; one end of the capacitor C2 is connected with the input end of the CMOS Schmitt trigger and the drain electrode of the P-type MOS tube Q9, and the other end is grounded;

one end of the resistor R1 is connected with the output end Vio of the CMOS energy collecting circuit module, the other end is connected with the drain electrode of the N-type MOS tube Q10, the grid electrode of the N-type MOS tube Q10 is connected with the output Vio of the energy collector, the source electrode is grounded, the drain electrode is connected with one end of the resistor R1, the grid electrode of the N-type MOS tube Q10 is connected with the drain electrode of the P-type MOS tube Q9, the source electrode is connected with the output Vio of the energy collector, the drain electrode is connected with the positive electrode end of the capacitor C2, the power supply of the Schmidt trigger is connected with the output Vio end of the energy collector, the input end is connected with the positive electrode of the capacitor C2, Vin1 is provided, namely, a micro-energy signal needing to be collected, the output end of the Schmidt trigger provides an enabling signal EN for the chip, and the GND port is grounded.

4. The SOC integrated circuit device of claim 3, wherein: the CMOS Schmitt trigger comprises P-type MOS tubes Q11, Q12, Q15 and N-type MOS tubes Q13, Q14 and Q16, wherein the P-type MOS tubes and the N-type MOS tubes are clamped mutually, so that a front-stage buffer small capacitor C1 is charged preferentially to supply power to the CMOS Schmitt trigger, when the voltage of the buffer small capacitor C1 reaches a certain threshold value, a rear-stage buffer small capacitor C2 is charged, and when the voltage of the buffer small capacitor C2 reaches the control voltage of the CMOS Schmitt trigger, the buffer small capacitor C2 outputs energy to the CMOS energy storage circuit module.

5. The SOC integrated circuit device of claim 1, wherein: the CMOS energy storage circuit module comprises a basic boost circuit, a buffer large capacitor, resistors R3, R4, R5, R6, R7 and R8, a comparator I, an error amplifier I, a voltage reference source I and a sawtooth wave generator I, wherein the comparator I consists of MOS (metal oxide semiconductor) tubes Q36, Q37, Q38, Q39, Q40, Q41, Q42 and Q43, a current source circuit and a differential amplifier consisting of MOS tubes Q44 to Q55, Q39 in the current source is connected to the drain terminals of Q47 and Q48, Q40 in the current source is connected to the gate of Q55 and the drain terminal of Q54, and therefore bias current is supplied to the whole differential amplifier; the error amplifier I is composed of a current source circuit composed of MOS transistors Q22 to Q27 and a secondary operational amplifier with Miller compensation composed of MOS transistors Q28 to Q35, wherein the grid electrode of Q22 of the current source is connected with the grid electrodes of Q28 and Q34, and suitable bias current is provided for the secondary operational amplifier; the voltage reference I is composed of MOS transistors Q55-Q59, resistors R11 and R12, transistors Q60, Q61 and Q62, and the output end Vref1 of the voltage reference I provides voltage reference for the chip; the sawtooth wave generator I is composed of Q62, Q63, Q64, Q65 and Q66, resistors R13, R14, R15, R16 and R17, capacitors C7 and C8 and a comparator III.

6. The SOC integrated circuit device of claim 5, wherein: the buffer large capacitor comprises a capacitor C4 and a capacitor C5.

7. The SOC integrated circuit device of claim 6, wherein: the CMOS energy storage circuit module adopts a boost circuit to boost the input voltage to 1.8V to 5.5V, and is suitable for charging capacitors C4 and C5.

8. The SOC integrated circuit device of claim 1, wherein: the voltage stabilizing circuit comprises a basic buck-boost circuit, resistors R18, R19, R20 and R21, a comparator II, an error amplifier II, a voltage reference II and a sawtooth wave generator II, wherein the comparator II comprises a current source circuit consisting of MOS (metal oxide semiconductor) tubes Q86, Q87, Q88, Q89, Q90, Q91, Q92 and Q93 and a differential amplifier consisting of MOS tubes Q94 to Q105, Q89 in the current source is connected to the drain terminals of Q97 and Q98, Q90 in the current source is connected to the gate terminal of Q105 and the drain terminal of Q104, and therefore bias current is provided for the whole differential amplifier; the error amplifier II is composed of a current source circuit composed of MOS transistors Q72 to Q77 and a second-stage operational amplifier with Miller compensation composed of MOS transistors Q78 to Q85, wherein the grid electrode of Q72 of the current source is connected with the grid electrodes of Q78 and Q84, and suitable bias current is provided for the operational amplifier; the voltage reference II is composed of MOS transistors Q106 to Q110, a resistor R24, a resistor R25, transistors Q111, Q112 and Q113, and the output end Vref2 of the voltage reference II provides voltage reference for the chip; the sawtooth wave generator II is composed of Q114, Q115, Q116, Q117 and Q118, resistors R26, R27, R28, R29 and R30, capacitors C11 and C12 and a comparator IV.

9. The SOC integrated circuit device of claim 8, wherein: the CMOS voltage stabilizing circuit module adopts a buck-boost circuit to convert the voltage from 1.8V to 5.5V into the voltage of 5V so as to continuously supply power to a rear-end load and a battery.

Images