CN215117308U - Current proportional amplification circuit - Google Patents
Current proportional amplification circuit Download PDFInfo
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- CN215117308U CN215117308U CN202120997493.6U CN202120997493U CN215117308U CN 215117308 U CN215117308 U CN 215117308U CN 202120997493 U CN202120997493 U CN 202120997493U CN 215117308 U CN215117308 U CN 215117308U
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Abstract
The utility model provides a current proportion amplifying circuit, including mirror image circuit, first biasing circuit, second biasing circuit and reference voltage generating circuit, first biasing circuit, second biasing circuit all include operational amplifier circuit and mos pipe, and the first input end of first biasing circuit is coupled with the output of reference voltage generating circuit, and the second input end is coupled with the grid of mirror image circuit source end and inserts reference current, and the drain electrode of mirror image circuit source end is coupled to the output; the first input end of the second bias circuit is coupled with the drain electrode of the source end of the mirror image circuit, the second input end of the second bias circuit is coupled with the drain electrode of the mirror image end of the mirror image circuit, and the output end of the second bias circuit outputs amplified current. The utility model discloses an adopt the fortune to put circuit and combine mos pipe to adjust the drain voltage of current mirror both sides, make grid, drain electrode, the source voltage difference of current mirror both sides very little, realized even output voltage is very low to make current mirror work also can realize the accurate of current mirror amplifying in linear region, reduced the requirement to output voltage.
Description
Technical Field
The utility model relates to an electronic circuit field, concretely but not limited to relate to a current proportion amplifier circuit.
Background
In circuit design, a reference circuit is required to be amplified to output in a certain proportion, and it is necessary to design a simple and reliable current amplification current.
A common current amplifying circuit is a current mirror, taking an NMOS current mirror as an example, as shown in fig. 1, a reference current Iref flows through M1 with gates and Drain short-circuited, and in addition, K NMOS with the same size as M1 are used, gates and Source are short-circuited in M1, respectively, and as can be known from MOS characteristics operating in a saturation region, an output current Iout ═ K ═ Iref flowing through K × M1 realizes current amplification.
Because the MOS Drain terminal voltages on the left side and the right side of the current mirror are different, a channel modulation effect exists, and the current obtained by final mirroring is different from K Iref. In a circuit with high precision requirement, a structure shown in fig. 2 is often adopted, a primary bias circuit is further superposed, and since the voltage at the point a of the current mirror is fixed and the current flowing through a single MOS is the same, the voltage difference VgsA of the Gate-Source of a single M2 NMOS is basically the same, and the voltage at the point B is equal to the voltage at the point C and is equal to the voltage at the point a-VgsA, so that the voltages of the Gate/Source/Drain of M1 and K × M1 are almost equal, and the current obtained by mirroring is closer to the proportion K of the number of MOS.
As can be seen from fig. 1 and 2, the conventional current mirror amplifying circuit has a certain requirement on the Drain terminal voltages on the left and right sides of the current mirror, and if a circuit with a relatively high output Iout voltage is used, the Drain terminal voltages on the two sides of the current mirror can be consistent by superimposing a first-stage bias circuit, but the traditional current mirror amplifying circuit is difficult to achieve the Drain terminal voltages consistent in a circuit with a relatively low output Iout voltage, so that high-precision amplification is achieved.
In view of the above, it is desirable to provide a new circuit structure or method to solve at least some of the above problems.
SUMMERY OF THE UTILITY MODEL
To one or more problems among the prior art, the utility model provides a current proportion amplifier circuit combines the drain electrode voltage of mos pipe regulation current mirror both sides through adopting the operational amplifier circuit, makes grid, drain electrode, the source electrode voltage difference of current mirror both sides very little, has realized that the precision that even output voltage is very low messenger current mirror work has also realized the current mirror in linear region enlargies, has reduced the requirement to output voltage.
Realize the utility model discloses the technical solution of purpose does:
a current proportional amplifying circuit comprising a mirror circuit, a first bias circuit, a second bias circuit, and a reference voltage generating circuit, wherein:
the mirror circuit comprises a mirror circuit source end and a mirror circuit mirror end, wherein a grid electrode of the mirror circuit source end is in short circuit with a grid electrode of the mirror circuit mirror end, and a source electrode of the mirror circuit source end is in short circuit with a source electrode of the mirror circuit mirror end and is grounded;
the first bias circuit and the second bias circuit respectively comprise an operational amplifier circuit and a mos tube, wherein a first input end of the first bias circuit is coupled with an output end of the reference voltage generating circuit, a second input end of the first bias circuit is coupled with a grid electrode of a source end of the mirror circuit and is connected with reference current, and an output end of the first bias circuit is coupled with a drain electrode of the source end of the mirror circuit; the first input end of the second bias circuit is coupled with the drain electrode of the source end of the mirror image circuit, the second input end of the second bias circuit is coupled with the drain electrode of the mirror image end of the mirror image circuit, and the output end of the second bias circuit outputs amplified current;
the reference voltage generating circuit comprises a plurality of mos tubes connected in series, the mos tubes are the same as the mos tube at the source end of the mirror image circuit, the grid electrode of each mos tube is used as a voltage input end and is connected with a fixed voltage, the drain electrode between every two adjacent mos tubes is connected with the source electrode, the source electrode of the first mos tube is grounded, the drain electrode of the last mos tube is connected with a plurality of times of reference currents and is used as a voltage output end, the output voltage of the drain electrode of the last mos tube is used as reference voltage, and the reference voltage is corresponding voltage when the mos tube at the source end of the mirror image circuit flows into the reference currents and works in a linear region.
Optionally, the first bias circuit includes a first operational amplifier and a first mos transistor, a non-inverting input terminal of the first operational amplifier is coupled to an output terminal of the reference voltage generating circuit, an inverting input terminal of the first operational amplifier is coupled to a drain of the source terminal of the mirror circuit, an output terminal of the first operational amplifier is coupled to a gate of the first mos transistor, a source of the first mos transistor is coupled to the drain of the source terminal of the mirror circuit, and a drain of the first mos transistor is coupled to the gate of the source terminal of the mirror circuit and is connected to the reference current.
Optionally, the first mos transistor is a PMOS transistor or an NMOS transistor.
Optionally, the second bias circuit includes a second operational amplifier and a second mos transistor, a non-inverting input terminal of the second operational amplifier is coupled to the drain of the source terminal of the mirror circuit, an inverting input terminal of the second operational amplifier is coupled to the drain of the mirror terminal of the mirror circuit, an output terminal of the second bias circuit is coupled to the gate of the second mos transistor, a source of the second mos transistor is coupled to the drain of the mirror terminal of the mirror circuit, and a drain of the second mos transistor is used as an output terminal for outputting the amplified current.
Optionally, the second mos transistor is a PMOS transistor or an NMOS transistor.
Optionally, the mirror ratio between the source end of the mirror circuit and the mirror end of the mirror circuit is n: m, where n is the number of mos transistors at the source end of the mirror circuit, n is greater than or equal to 1, m is the number of mos transistors at the mirror end of the mirror circuit, and m is greater than or equal to 1.
Optionally, the mos transistor at the source end of the mirror circuit and the mos transistor at the mirror end of the mirror circuit are the same PMOS transistor or NMOS transistor.
Optionally, the mos transistor of the reference voltage generating circuit is a PMOS transistor or an NMOS transistor that is the same as the mos transistor at the source end of the mirror circuit.
The utility model adopts the above technical scheme to compare with prior art, have following technological effect:
the utility model discloses a current proportion amplifier circuit is through adopting the drain voltage of two way bias circuit closed loop regulation mirror image circuit both sides, makes the grid of mirror image circuit both sides, drain electrode, source voltage homoenergetic equal, has realized mirror image circuit's accurate duplication to when output voltage is lower, also can realize that the high accuracy of electric current is enlargied, reduced the requirement to output voltage, to bias circuit input reference voltage, realized that the self-adaptation works at the electric current of linear region enlargies simultaneously.
Drawings
Fig. 1 shows a schematic diagram of a conventional current amplifying circuit.
Fig. 2 shows a schematic diagram of a conventional circuit amplifier with a bias circuit.
Fig. 3 shows a schematic diagram of the current proportional amplifying circuit of the present invention.
Fig. 4 shows an internal circuit diagram of the current proportional amplifying circuit of the present invention.
Fig. 5 shows a schematic diagram of a reference voltage generating circuit of the current scaling circuit of the present invention.
The same reference numbers in different drawings identify the same or similar elements or components.
Detailed Description
For further understanding of the present invention, preferred embodiments of the present invention will be described below with reference to examples, but it should be understood that these descriptions are only for the purpose of further illustrating the features and advantages of the present invention, and are not intended to limit the claims of the present invention.
The description in this section is for exemplary embodiments only, and the present invention is not limited to the scope of the embodiments described. Combinations of different embodiments, or technical features of different embodiments, or similar prior art means, or technical features of embodiments, may be substituted for each other within the scope of the present invention.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a conductor, wherein the electrically conductive medium may contain parasitic inductance or parasitic capacitance, or through an intermediate circuit or component as described in the embodiments in the specification; indirect connections may also include connections through other active or passive devices that perform the same or similar function, such as connections through switches, signal amplification circuits, follower circuits, and so on. "plurality" or "plurality" means two or more.
According to an aspect of the present invention, a current proportional amplifying circuit, as shown in fig. 3, includes a mirror circuit 4, a first bias circuit 1, a second bias circuit 2, and a reference voltage generating circuit 3. The first input terminal of the first bias circuit 1 is coupled to the output terminal of the reference voltage generating circuit 3, the second input terminal is connected to the reference current Iref and is coupled to the output terminal of the source terminal of the mirror circuit 4, and the output terminal is coupled to the input terminal of the source terminal of the mirror circuit 4. The first input terminal of the second bias circuit 2 is coupled to the input terminal of the source terminal of the mirror circuit 4, the second input terminal is coupled to the output terminal of the mirror circuit 4, and the output terminal outputs the amplified current.
The current proportional amplifying circuit of the present embodiment is further described below by taking an NMOS current mirror as an example. As shown in fig. 4, the mirror circuit 4 includes a mirror circuit source terminal and a mirror circuit mirror terminal, and in one embodiment, the mirror circuit source terminal includes an NMOS transistor M1 (hereinafter, an NMOS transistor of the mirror circuit source terminal is referred to as M1), the mirror circuit mirror terminal includes K NMOS transistors M1 (hereinafter, K × M1 refers to K NMOS transistors of the mirror circuit mirror terminal), and K is a positive integer, so that a mirror ratio between the mirror circuit source terminal M1 and the mirror circuit mirror terminal K × M1 is K. The grid of the mirror image circuit source end M1 is in short circuit with the grid of the mirror image circuit mirror image end K M1, and the source of the mirror image circuit source end M1 is in short circuit with the source of the mirror image circuit mirror image end K M1 and is grounded. The drain of the mirror circuit source terminal M1 is coupled to the output terminal of the first bias circuit 1, and in one embodiment, a first input terminal of the first bias circuit 1 is coupled to the output terminal of the reference voltage generating circuit 3, and a second input terminal thereof is coupled to the gate of the mirror circuit source terminal M1 and is connected to the reference current Iref. The drain of the mirror circuit mirror terminal K × M1 is coupled to the second input terminal of the second bias circuit 2, and in one embodiment, the first input terminal of the second bias circuit 2 is coupled to the drain of the mirror circuit source terminal M1, and the output terminal outputs the amplified current.
The first bias circuit 1 and the second bias circuit 2 both comprise an operational amplifier circuit and a mos transistor. In one embodiment, as shown in fig. 4, the first bias circuit 1 includes an operational amplifier OP1 and an NMOS transistor M3, a non-inverting input terminal of the operational amplifier OP1 is coupled to an output terminal of the reference voltage generating circuit 3, that is, a non-inverting input terminal of the operational amplifier OP1 is coupled to the reference voltage Vref output by the reference voltage generating circuit 3, an inverting input terminal of the operational amplifier OP1 is coupled to a drain of the mirror circuit source terminal M1, and an output terminal of the operational amplifier OP1 is coupled to a gate of the NMOS transistor M3. The source of the NMOS transistor M3 is coupled to the drain of the mirror source M1, and the drain of the NMOS transistor M3 is coupled to the gate of the mirror source M1 and connected to the reference current Iref. The operational amplifier OP1 adjusts the source voltage of the NMOS transistor M3 (i.e., the voltage at point a in fig. 4) by adjusting the gate voltage of the NMOS transistor M3. In another embodiment, as shown in fig. 4, the second bias circuit 2 includes an operational amplifier OP2 and an NMOS transistor M2, wherein a non-inverting input terminal of the operational amplifier OP2 is coupled to a drain of the mirror source terminal M1, an inverting input terminal of the operational amplifier OP2 is coupled to a drain of the mirror source terminal K × M1, an output terminal of the operational amplifier OP is coupled to a gate of the NMOS transistor M2, a source of the NMOS transistor M2 is coupled to a drain of the mirror source terminal K × M1, and a drain of the NMOS transistor M2 serves as an output terminal for outputting the amplified current Iout. The operational amplifier OP2 adjusts the gate voltage of the NMOS transistor M2 to adjust the source voltage of the NMOS transistor M2 (i.e., the voltage at point B in fig. 4) so that the error between the source voltage and the voltage at point a input from the non-inverting input terminal of the operational amplifier OP2 is as small as possible. Since the operational amplifier OP1 has an output offset voltage, the output voltage of the source of the NMOS transistor M3 (i.e., the voltage at point a in the figure) is different from the reference voltage Vref, and when the voltage at point a is connected to the non-inverting input terminal of the operational amplifier OP2, the error between the output voltage of the drain of the mirror terminal K × M1 of the mirror circuit (i.e., the voltage at point B in the figure) and the voltage at point a can be reduced.
The reference voltage generation circuit 3 is configured to generate and output a reference voltage Vref. In one embodiment, as shown in fig. 5, the reference voltage generating circuit 3 includes K2 serial NMOS transistors, where K2 is a positive integer, and in another embodiment, the reference voltage generating circuit 3 includes K2 serial NMOS transistors, each of which is the same NMOS transistor as the mirror circuit source terminal M1 (hereinafter, K2 × M1 is used to refer to K2 NMOS transistors of the reference voltage generating circuit 3). The grid of each NMOS tube in the reference voltage generating circuit K2M 1 is used as a voltage input end and is connected with a fixed voltage Vgate, the drain between adjacent NMOS tubes in K2M 1 is connected with the source, the source of the first NMOS tube is grounded, the drain of the last NMOS tube is connected with K1 times of reference current K1 Iref and is used as a voltage output end, the output voltage of the drain of the last NMOS tube is used as reference voltage Vref, and the reference voltage Vref is the voltage corresponding to the condition that the mirror circuit source end M1 flows in the reference current Iref and works in a linear region.
The voltage required by the whole circuit system to output the amplified current Iout is the voltage at the point B, namely the sum of the voltage at the point a and the drain-source voltage of the NMOS transistor M2. Since the voltage drop of the drain-source of the NMOS transistor M2 can be made small by reducing the linear region on-resistance of the NMOS transistor M2, the voltage required for outputting the amplified current Iout is positively correlated with the voltage at the point a.
Therefore, the grid voltage, the source voltage and the drain voltage of the source end M1 of the mirror circuit and the mirror end K M1 of the mirror circuit can be equal, and accurate copying of the mirror circuit is achieved. The conventional current mirror MOS transistor generally works in a saturation region to reduce the influence of drain voltage on the transistor. The current proportion amplifying circuit adopting the structure has the advantages that the voltage difference between the three ends of the Gate/drain/Source at the left side and the right side of the mirror image circuit is small, even if the reference voltage Vref is low and the mirror image circuit works in a linear area, the mirror image circuit can be accurately amplified, and therefore the requirement on output voltage is reduced. When the reference voltage Vref generated by the reference voltage generation circuit 3 is the voltage corresponding to the mirror circuit source terminal M1, which flows the reference current Iref and operates in the linear region, the current proportional amplification of the linear region can be adaptively achieved.
The following describes the operation of the current scaling circuit according to this embodiment in detail:
the first bias circuit 1 flows a reference current Iref and applies a reference voltage Vref for adjusting the drain voltage of the mirror circuit source terminal M1, the reference voltage Vref being generated and formed by the reference voltage generation circuit 3; in one embodiment, the first bias circuit 1 includes an operational amplifier OP1 and an NMOS transistor M3, the operational amplifier OP1 inputs a reference voltage Vref and a source voltage of the NMOS transistor M3 (i.e., a drain voltage of the mirror source terminal M1), while the operational amplifier OP1 outputs a regulation signal to a gate of the NMOS transistor M3, a reference current Iref flows into a drain of the NMOS transistor M3, and a regulated voltage (i.e., a point a voltage) and a regulated current are output from a source of the NMOS transistor M3.
The source of the NMOS transistor M3 is coupled to the drain of the source terminal M1 of the mirror circuit and outputs a current to the mirror circuit, and the mirror circuit performs mirror amplification on the current and outputs the current through the drain of the mirror terminal K × M1 of the mirror circuit.
The second bias circuit 2 adjusts the drain voltage of the mirror terminal K × M1 of the mirror circuit according to the drain voltage (i.e., the voltage at the point a) of the mirror circuit source terminal M1; in one embodiment, the second bias circuit 2 includes an operational amplifier OP2 and an NMOS transistor M2, the operational amplifier OP2 inputs the voltage at the point a and the source voltage of the NMOS transistor M2 (i.e., the drain voltage of the mirror terminal K × M1 of the mirror circuit), and the operational amplifier OP2 outputs an adjustment signal to the gate of the NMOS transistor M2, so that the drain of the NMOS transistor M2 outputs an amplified current proportional to the reference current. The Drain-Source voltage drop of NMOS transistor M2 can be made small by reducing the linear region on-resistance of NMOS transistor M2. Thus, the drain of the NMOS transistor M2 outputs the amplified current Iout — K × Iref.
When the reference voltage adopts the mirror circuit source end M1 to flow the reference current and works at the voltage corresponding to the linear region, the current proportion amplification of the self-adaptive working linear region can be realized.
Those skilled in the art should understand that the logic controls such as "high" and "low", "set" and "reset", "and gate" and "or gate", "non-inverting input" and "inverting input" in the logic controls referred to in the specification or the drawings may be exchanged or changed, and the subsequent logic controls may be adjusted to achieve the same functions or purposes as the above-mentioned embodiments.
The description and applications of the present invention are illustrative and are not intended to limit the scope of the invention to the embodiments described above. The descriptions related to the effects or advantages in the specification may not be reflected in practical experimental examples due to uncertainty of specific condition parameters or influence of other factors, and the descriptions related to the effects or advantages are not used for limiting the scope of the invention. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the present invention.
Claims (8)
1. A current proportional amplifying circuit, comprising a mirror circuit, a first bias circuit, a second bias circuit and a reference voltage generating circuit, wherein:
the mirror circuit comprises a mirror circuit source end and a mirror circuit mirror end, wherein a grid electrode of the mirror circuit source end is in short circuit with a grid electrode of the mirror circuit mirror end, and a source electrode of the mirror circuit source end is in short circuit with a source electrode of the mirror circuit mirror end and is grounded;
the first bias circuit and the second bias circuit respectively comprise an operational amplifier circuit and a mos tube, wherein a first input end of the first bias circuit is coupled with an output end of the reference voltage generating circuit, a second input end of the first bias circuit is coupled with a grid electrode of a source end of the mirror circuit and is connected with reference current, and an output end of the first bias circuit is coupled with a drain electrode of the source end of the mirror circuit; the first input end of the second bias circuit is coupled with the drain electrode of the source end of the mirror image circuit, the second input end of the second bias circuit is coupled with the drain electrode of the mirror image end of the mirror image circuit, and the output end of the second bias circuit outputs amplified current;
the reference voltage generating circuit comprises a plurality of mos tubes connected in series, the mos tubes are the same as the mos tubes of the mirror image circuit, the grid electrode of each mos tube is used as a voltage input end and is connected with a fixed voltage, the drain electrode between every two adjacent mos tubes is connected with the source electrode, the source electrode of the first mos tube is grounded, the drain electrode of the last mos tube is connected with a plurality of times of reference currents and is used as a voltage output end, the output voltage of the drain electrode of the last mos tube is used as reference voltage, and the reference voltage is corresponding voltage when the reference current flows into the mos tube at the source end of the mirror image circuit and works in a linear region.
2. The current scaling circuit of claim 1, wherein the first bias circuit comprises a first operational amplifier and a first mos transistor, a non-inverting input terminal of the first operational amplifier is coupled to the output terminal of the reference voltage generating circuit, an inverting input terminal of the first operational amplifier is coupled to a drain of the source terminal of the mirror circuit, an output terminal of the first operational amplifier is coupled to a gate of the first mos transistor, a source of the first mos transistor is coupled to the drain of the source terminal of the mirror circuit, and a drain of the first mos transistor is coupled to the gate of the source terminal of the mirror circuit and is connected to the reference current.
3. The current scaling circuit of claim 2, wherein the first mos transistor is a PMOS transistor or an NMOS transistor.
4. The current scaling circuit of claim 1, wherein the second bias circuit comprises a second operational amplifier and a second mos transistor, a non-inverting input terminal of the second operational amplifier is coupled to a drain of the source terminal of the mirror circuit, an inverting input terminal of the second operational amplifier is coupled to a drain of the mirror terminal of the mirror circuit, an output terminal of the second operational amplifier is coupled to a gate of the second mos transistor, a source of the second mos transistor is coupled to a drain of the mirror terminal of the mirror circuit, and a drain of the second mos transistor serves as an output terminal for outputting the amplified current.
5. The current scaling circuit of claim 4, wherein the second mos transistor is a PMOS transistor or an NMOS transistor.
6. The current proportion amplifying circuit of claim 1, wherein a mirror ratio between the source terminal of the mirror circuit and the mirror terminal of the mirror circuit is n: m, wherein n is the number of mos transistors at the source terminal of the mirror circuit, n is greater than or equal to 1, m is the number of mos transistors at the mirror terminal of the mirror circuit, and m is greater than or equal to 1.
7. The current proportional amplifying circuit of claim 1 or 6, wherein the mos transistor at the source terminal of the mirror circuit and the mos transistor at the mirror terminal of the mirror circuit are the same PMOS transistor or NMOS transistor.
8. The current scaling circuit of claim 7, wherein the mos transistor of the reference voltage generating circuit is a PMOS transistor or an NMOS transistor that is the same as the mos transistor of the source terminal of the mirror circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120997493.6U CN215117308U (en) | 2021-05-11 | 2021-05-11 | Current proportional amplification circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120997493.6U CN215117308U (en) | 2021-05-11 | 2021-05-11 | Current proportional amplification circuit |
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| CN215117308U true CN215117308U (en) | 2021-12-10 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115459718A (en) * | 2022-08-02 | 2022-12-09 | 深圳精控集成半导体有限公司 | Gain amplification circuit and amplifier |
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2021
- 2021-05-11 CN CN202120997493.6U patent/CN215117308U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115459718A (en) * | 2022-08-02 | 2022-12-09 | 深圳精控集成半导体有限公司 | Gain amplification circuit and amplifier |
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