CN215072342U - PWM (pulse-Width modulation) circuit controlled by multiple logic judgment conditions - Google Patents
PWM (pulse-Width modulation) circuit controlled by multiple logic judgment conditions Download PDFInfo
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Abstract
The utility model relates to a PWM pulse width modulation circuit of many logics judgement condition control, including PWM signal shaping circuit, logic condition judgement circuit, PWM signal control circuit and output drive circuit, PWM pulse width modulation signal inserts PWM signal shaping circuit, PWM signal shaping circuit is connected with output drive circuit and PWM signal control circuit electricity respectively, a plurality of logics are judged condition signal and are corresponded and insert logic condition judgement circuit, logic condition judgement circuit is connected with PWM signal control circuit electricity, PWM signal control circuit is connected with output drive circuit electricity, output drive circuit exports PWM signal externally. The utility model discloses carry out the plastic to PWM pulse width modulation signal earlier, carry out logic judgement to a plurality of relevant logic conditions again, through PWM signal control circuit control output/turn-off PWM signal, the duty cycle of adjustment waveform through output drive circuit output at last, realizes the judgement control of a plurality of logic judgement conditions, and the circuit is simple, convenient and practical.
Description
Technical Field
The utility model relates to a pulse width modulation technical field especially relates to a PWM pulse width modulation circuit of condition control is judged to many logics.
Background
With the rapid development of national 5G mobile communication, the requirements on the electrical performance and technical indexes of a 30KVA high-power UPS module in a communication power supply system are higher and higher. The technical index requirement on the waveform of the PWM signal is higher and higher, the PWM signal is realized by the PWM circuit controlled by the multi-logic judgment condition, so that the MOSFET tube can work more effectively at high frequency, the working efficiency of the rectification and inversion main power circuit of the UPS module is higher, and the electrical performance and the technical index of the module are improved. Conventional simple PWM pulse width modulation circuits cannot achieve the above functions.
Disclosure of Invention
The utility model aims to solve the technical problem that to the not enough of above-mentioned prior art, a PWM pulse width modulation circuit of condition control is judged to many logics is provided.
The utility model provides an above-mentioned technical problem's technical scheme as follows: a PWM (pulse-Width modulation) circuit controlled by multiple logic judgment conditions comprises a PWM signal shaping circuit, a logic condition judgment circuit, a PWM signal control circuit and an output drive circuit, wherein PWM pulse-Width modulation signals are connected into the PWM signal shaping circuit, the output end of the PWM signal shaping circuit is respectively electrically connected with one input end of the output drive circuit and one input end of the PWM signal control circuit, multiple logic judgment condition signals are correspondingly connected into multiple input ends of the logic condition judgment circuit, the output end of the logic condition judgment circuit is electrically connected with the other input end of the PWM signal control circuit, the output end of the PWM signal control circuit is electrically connected with the other input end of the output drive circuit, and the output end of the output drive circuit outputs the PWM signals to the outside.
The utility model has the advantages that: the utility model discloses a PWM pulse width modulation circuit of many logics judgement condition control, through PWM signal shaping circuit carries out the plastic to PWM pulse width modulation signal, strains out clutter signal, simultaneously, judges the circuit by logic condition again and carries out the logic judgement to a plurality of relevant logic conditions, through PWM signal control circuit control output/turn-off PWM signal, the duty cycle of adjustment wave form, through output drive circuit output at last, realizes the judgement control of a plurality of logics judgement conditions, and the circuit is simple, convenient and practical.
On the basis of the technical scheme, the utility model discloses can also do as follows the improvement:
further: the PWM signal shaping circuit comprises a NAND logic trigger chip U1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2 and a transistor Q1, wherein a PWM pulse width modulation signal is electrically connected with the base of the transistor Q1 through the resistor R1, the capacitor C1 is connected with the resistor R1 in parallel, the resistor R2 is electrically connected between the base and the emitter of the transistor Q1, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is electrically connected with two input ends of the NAND logic trigger chip U1 through the resistor R3, two input ends of the NAND logic trigger chip U1 are also electrically connected with the power input end of the NAND logic trigger chip U1 through the resistor R4, the power input end of the NAND logic trigger chip U1 is electrically connected with an external power supply +15V, the power input end of the NAND logic trigger chip U1 is grounded through the capacitor C2, the grounding end of the NAND gate logic trigger chip U1 is grounded, and the output end of the NAND gate logic trigger chip U1 is electrically connected with the input end of the output drive circuit and one input end of the PWM signal control circuit respectively.
The beneficial effects of the further scheme are as follows: the PWM _ IN signal is shaped by a filter circuit consisting of a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a capacitor C1, clutter signals are removed, so that the PWM signal waveform is more standard and is not deformed, the shaped PWM signal is triggered and overturned by NAND gate logic of a NAND gate logic trigger chip U1, the waveform of the PWM signal enhances the noise interference degree and slowly changes the correcting waveform, and the PWM signal with better quality is output.
Further: the logic condition judging circuit comprises an operational amplifier U3, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a diode D1, a diode D2, a diode D3, a triode Q5 and a triode Q6;
one logic judgment condition signal is connected to one end of the resistor R12, the resistor R13 and the capacitor C6 are connected in parallel between the other end of the resistor R12 and the ground, the other end of the resistor R12 is electrically connected to the non-inverting input end of the operational amplifier U3 through the resistor R14, the resistor R17 is electrically connected between the non-inverting input end and the output end of the operational amplifier U3, the inverting input end of the operational amplifier U3 is electrically connected to the reference voltage +5VREF through the resistor R15, the resistor R16 and the capacitor C7 are connected in parallel between the inverting input end of the operational amplifier U3 and the ground, the positive power supply input end of the operational amplifier U3 is grounded through the capacitor C8, the negative power supply input end of the operational amplifier U3 is grounded through the capacitor C9, the output end of the operational amplifier U3 is electrically connected to the power supply +15V through the resistor R18, and the output end of the operational amplifier U3 is electrically connected to the positive electrode 1, the cathode of the diode D1 is electrically connected with the other input end of the PWM signal control circuit;
the other logic judgment condition signal is connected to the anode of the diode D2, and the cathode of the diode D2 is electrically connected with the other input end of the PWM signal control circuit;
the other logic judgment condition signal is connected to the base of the transistor Q5 through the resistor R19, the resistor R20 is electrically connected between the base and the emitter of the transistor Q5, the emitter of the transistor Q5 is grounded, the collector of the transistor Q5 is electrically connected to +15V of the power supply through the resistor R21, the collector of the transistor Q5 is electrically connected to the base of the transistor Q6 through the resistor R22, the emitter of the transistor Q6 is electrically connected to +15V of the power supply, the collector of the transistor Q6 is grounded through the resistor R23, the collector of the transistor Q6 is electrically connected to the positive electrode of the diode D3 through the resistor R24, and the negative electrode of the diode D3 is electrically connected to the other input terminal of the PWM signal control circuit.
The beneficial effects of the further scheme are as follows: each logic condition judgment signal is judged through the multi-path logic condition judgment branch, so that the result of the multi-path logic condition judgment branch can be synthesized to control the output or turn off the PWM signal waveform, and the judgment control of a plurality of logic judgment conditions is realized.
Further: the PWM signal control circuit comprises a D flip-flop chip U2, a resistor R9, a resistor R10, a resistor R11, a capacitor C4, a capacitor C5 and a triode Q4, a preset end S1 of the D flip-flop chip U2 is grounded, a data end D1 and a power input end VDD of the D flip-flop chip U2 are respectively and electrically connected with +15V of a power supply, a power input end VDD of the D flip-flop chip U2 is grounded through the capacitor C4, and a clock signal end C1 of the D flip-flop chip U2 and an output end of the PWM signal shaping circuitThe reset end R1 of the D flip-flop chip U2 is electrically connected with the output end of the logic condition judgment circuit, the grounding end VSS of the D flip-flop chip U2 is grounded, and the output end of the D flip-flop chip U2 is connected with the output end of the logic condition judgment circuit
The resistor R10 and the resistor R11 are sequentially connected in series with the ground, the common end of the resistor R10 and the resistor R11 is electrically connected with the base electrode of the triode Q4, the emitter electrode of the triode Q4 is grounded, and the collector electrode of the triode Q4 is electrically connected with the other input end of the output driving circuit.
The beneficial effects of the further scheme are as follows: the D trigger chip U2 controls the output or cut-off of the PWM signal output by the PWM signal shaping circuit according to the level signal output by the multi-channel logic condition judging circuit, and when the PWM signal is output, the PWM signal output by the PWM signal shaping circuit and the signal output by the D trigger are superposed to adjust the duty ratio of the waveform of the PWM signal and control the working state of an external MOS tube.
Further: the output driving circuit comprises a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C3, a triode Q2 and a triode Q3, wherein the output end of the PWM signal shaping circuit is grounded through the resistor R7, the output end of the PWM signal shaping circuit is electrically connected with one end of the resistor R6, the other end of the resistor R6 is electrically connected with the base of the triode Q2 and the base of the triode Q3, the resistor R5 is connected with the resistor R6 in parallel, the resistor R8 and the capacitor C3 are connected between the other end of the resistor R6 and the ground in parallel, the collector of the triode Q2 is electrically connected with +15V, the collector of the triode Q3 is grounded, and the emitter of the triode Q2 is electrically connected with the emitter of the triode Q3 and used as the output end to output PWM signals.
The beneficial effects of the further scheme are as follows: the gate driving loading capacity of an external main power MOSFET is increased through a driving circuit for clamping output waveforms up and down through a triode Q2 and a triode Q3; through a circuit formed by the resistor R5, the resistor R6, the resistor R7, the resistor R8 and the capacitor C3, parameters of an output driving circuit are matched with performance indexes such as forward and reverse switching time and input impedance of an external main power MOSFET, a more stable PWM pulse width modulation signal PWM _ OUT is output, and the external main power MOSFET is enabled to achieve a more efficient switching working state.
Drawings
Fig. 1 is a schematic structural diagram of a PWM pulse width modulation circuit controlled by multiple logical judgment conditions according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a PWM signal shaping circuit according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a logic condition determining circuit according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of a PWM signal control circuit and an output driving circuit according to an embodiment of the present invention.
Detailed Description
The principles and features of the present invention are described below in conjunction with the following drawings, the examples given are only intended to illustrate the present invention and are not intended to limit the scope of the present invention.
As shown in fig. 1, a PWM pulse width modulation circuit controlled by multiple logic judgment conditions includes a PWM signal shaping circuit, a logic condition judgment circuit, a PWM signal control circuit and an output driving circuit, where a PWM pulse width modulation signal is connected to the PWM signal shaping circuit, an output end of the PWM signal shaping circuit is electrically connected to one input end of the output driving circuit and one input end of the PWM signal control circuit, multiple logic judgment condition signals are correspondingly connected to multiple input ends of the logic condition judgment circuit, an output end of the logic condition judgment circuit is electrically connected to another input end of the PWM signal control circuit, an output end of the PWM signal control circuit is electrically connected to another input end of the output driving circuit, and an output end of the output driving circuit outputs a PWM signal to the outside.
The utility model discloses a PWM pulse width modulation circuit of many logics judgement condition control, through PWM signal shaping circuit carries out the plastic to PWM pulse width modulation signal, strains out clutter signal, simultaneously, judges the circuit by logic condition again and carries out the logic judgement to a plurality of relevant logic conditions, through PWM signal control circuit control output/turn-off PWM signal, the duty cycle of adjustment wave form, through output drive circuit output at last, realizes the judgement control of a plurality of logics judgement conditions, and the circuit is simple, convenient and practical.
As shown in fig. 2, in one or more embodiments of the present invention, the PWM signal shaping circuit includes a nand logic flip-flop U1 (model number is MC14013), a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2, and a transistor Q1, the PWM pulse width modulation signal is electrically connected to the base of the transistor Q1 through the resistor R1, the capacitor C1 is connected in parallel to the resistor R1, the resistor R2 is electrically connected between the base and the emitter of the transistor Q1, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is electrically connected to two inputs of the nand logic flip-flop U1 through the resistor R3, two inputs of the nand logic flip-flop U1 are also electrically connected to the power input of the nand logic flip-flop U1 through the resistor R4, the power input of the nand logic flip-flop U1 is electrically connected to an external power supply +15V, the power supply input end of the NAND gate logic trigger chip U1 is grounded through the capacitor C2, the ground end of the NAND gate logic trigger chip U1 is grounded, and the output end of the NAND gate logic trigger chip U1 is electrically connected with the input end of the output drive circuit and one input end of the PWM signal control circuit respectively.
The PWM _ IN signal is shaped by a filter circuit consisting of a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a capacitor C1, clutter signals are removed, so that the PWM signal waveform is more standard and is not deformed, the shaped PWM signal is triggered and overturned by NAND gate logic of a NAND gate logic trigger chip U1, the waveform of the PWM signal enhances the noise interference degree and slowly changes the correcting waveform, and the PWM signal with better quality is output.
As shown in fig. 3, in one or more embodiments of the present invention, the logic condition determining circuit includes an operational amplifier U3 (model LM2903), a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a diode D1, a diode D2, a diode D3, a transistor Q5, and a transistor Q6;
wherein, a logic judgment condition signal is connected to one end of the resistor R12, the resistor R13 and the capacitor C6 are connected in parallel between the other end of the resistor R12 and the ground, the other end of the resistor R12 is electrically connected to the non-inverting input end of the operational amplifier U3 through the resistor R14, the resistor R17 is electrically connected between the non-inverting input end and the output end of the operational amplifier U3, the inverting input end of the operational amplifier U3 is electrically connected to the reference voltage +5VREF through the resistor R15, the resistor R16 and the capacitor C7 are connected in parallel between the inverting input end of the operational amplifier U3 and the ground, the positive power input end of the operational amplifier U3 is grounded through the capacitor C8, the negative power input end of the operational amplifier U3 is grounded through the capacitor C9, the output end of the operational amplifier U3 is electrically connected to the power supply +15V through the resistor R18, the output end of the operational amplifier U3 is electrically connected with the anode of the diode D1, and the cathode of the diode D1 is electrically connected with the other input end of the PWM signal control circuit;
the other logic judgment condition signal is connected to the anode of the diode D2, and the cathode of the diode D2 is electrically connected with the other input end of the PWM signal control circuit;
the other logic judgment condition signal is connected to the base of the transistor Q5 through the resistor R19, the resistor R20 is electrically connected between the base and the emitter of the transistor Q5, the emitter of the transistor Q5 is grounded, the collector of the transistor Q5 is electrically connected to +15V of the power supply through the resistor R21, the collector of the transistor Q5 is electrically connected to the base of the transistor Q6 through the resistor R22, the emitter of the transistor Q6 is electrically connected to +15V of the power supply, the collector of the transistor Q6 is grounded through the resistor R23, the collector of the transistor Q6 is electrically connected to the positive electrode of the diode D3 through the resistor R24, and the negative electrode of the diode D3 is electrically connected to the other input terminal of the PWM signal control circuit.
Here, the diode D1, the diode D2, and the diode D3 are key components of the or gate logic condition determination circuit, and any one of the three logic conditions is active at a high level, i.e., the PWM signal waveform can be controlled to be turned off. The judgment condition signal 1(V1) is one of the analog quantities of the voltage AI detected by the UPS, V1 is compared with the divided voltage value of the reference voltage +5VREF via the non-inverting input terminal of the operational amplifier chip U3, and if the divided voltage value is higher than the reference voltage +5VREF, the output of the operational amplifier U3 to the diode D1 is at a high level. The edit judgment condition signal 2(V2) is a PWM signal control level output from the single chip microcomputer, and is output to the diode D2 to turn off the PWM signal waveform when the PWM signal is at a high level. The edit judgment condition signal 3(V3) is a control signal sent from the other unit control circuit, and when V3 is at a high level, the transistors Q5 and Q6 are turned on and output to the diode D3 as a high level.
Each logic condition judgment signal is judged through the multi-path logic condition judgment branch, so that the result of the multi-path logic condition judgment branch can be synthesized to control the output or turn off the PWM signal waveform, and the judgment control of a plurality of logic judgment conditions is realized.
It should be noted that, here, three logic judgment condition signals are listed, in practice, the number of the logic judgment condition signals may be flexibly set as required, and the corresponding logic judgment branch circuit structures are matched, which are not listed here one by one.
As shown in fig. 4, in one or more embodiments of the present invention, the PWM signal control circuit includes a D flip-flop chip U2, a resistor R9, a resistor R10, a resistor R11, a capacitor C4, a capacitor C5 and a transistor Q4, the preset terminal S1 of the D flip-flop chip U2 is grounded, the data terminal D1 and the power input terminal VDD of the D flip-flop chip U2 are respectively electrically connected to +15V of the power supply, the power input terminal VDD of the D flip-flop chip U2 is grounded through the capacitor C4, the clock signal terminal C1 of the D flip-flop chip U2 is electrically connected to the output terminal of the PWM signal shaping circuit, the reset terminal R1 of the D flip-flop chip U2 is electrically connected to the output terminal of the logic condition determination circuit, the ground terminal VSS of the D flip-flop chip U2 is grounded, and the output terminal of the D flip-flop chip U2 is electrically connected to the output terminal of the logic condition determination circuit
The resistor R10 and the resistor R11 are sequentially connected in series with the ground, the common end of the resistor R10 and the resistor R11 is electrically connected with the base electrode of the triode Q4, the emitter electrode of the triode Q4 is grounded, and the collector electrode of the triode Q4 is electrically connected with the other input end of the output driving circuit.
The D trigger chip U2 controls the output or cut-off of the PWM signal output by the PWM signal shaping circuit according to the level signal output by the multi-channel logic condition judging circuit, and when the PWM signal is output, the PWM signal output by the PWM signal shaping circuit and the signal output by the D trigger are superposed to adjust the duty ratio of the waveform of the PWM signal and control the working state of an external MOS tube.
Specifically, here, the D flip-flop chip U2 (model MC14013) is a dual-way D flip-flop chip, the clock C1 pin inputs the clock waveform, the data D1 pin is at high level, and the S1 pin is set to low level: when the reset R1 pin is high level, the reverse output
The pin is always at a high level; when the reset R1 pin is at low level, the output is reversed
The pin outputs a clock inversion waveform. Reverse output
When the pin outputs high level, the triode Q4 is conducted to work, and the PWM signal waveform of the driving circuit is turned off. The output of the PWM signal shaping circuit is connected to a clock C1 pin of a NAND gate logic trigger chip U1, the output of the logic condition judging circuit is connected to a reset R1 pin, and the PWM signal waveform is cut off when the reset R1 pin is in a high level; the reset R1 pin reversely outputs the PWM signal waveform when the power is low level, the PWM output waveform at the moment is actually the superposition of two paths of output waveforms, the duty ratio of the PWM signal output waveform can be adjusted, and the working state of the external main MOSFET is further controlled.
As shown in fig. 4, in one or more embodiments of the present invention, the output driving circuit includes a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C3, a transistor Q2, and a transistor Q3, the output end of the PWM signal shaping circuit is grounded through the resistor R7, the output end of the PWM signal shaping circuit is electrically connected with one end of the resistor R6, the other end of the resistor R6 is electrically connected with the base of the triode Q2 and the base of the triode Q3, the resistor R5 is connected in parallel with the resistor R6, the resistor R8 and the capacitor C3 are connected in parallel between the other end of the resistor R6 and the ground, the collector of the transistor Q2 is electrically connected with the +15V power supply, the collector of the transistor Q3 is grounded, an emitter of the transistor Q2 is electrically connected to an emitter of the transistor Q3, and outputs a PWM signal as an output terminal.
The gate driving loading capacity of an external main power MOSFET is increased through a driving circuit for clamping output waveforms up and down through a triode Q2 and a triode Q3; through a circuit formed by the resistor R5, the resistor R6, the resistor R7, the resistor R8 and the capacitor C3, parameters of an output driving circuit are matched with performance indexes such as forward and reverse switching time and input impedance of an external main power MOSFET, a more stable PWM pulse width modulation signal PWM _ OUT is output, and the external main power MOSFET is enabled to achieve a more efficient switching working state.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.
Claims (5)
1. A PWM circuit controlled by multiple logic judgment conditions is characterized in that: the PWM signal shaping circuit is connected with PWM pulse width modulation signals, the output end of the PWM signal shaping circuit is respectively electrically connected with one input end of the output driving circuit and one input end of the PWM signal control circuit, a plurality of logic judgment condition signals are correspondingly connected with a plurality of input ends of the logic condition judgment circuit, the output end of the logic condition judgment circuit is electrically connected with the other input end of the PWM signal control circuit, the output end of the PWM signal control circuit is electrically connected with the other input end of the output driving circuit, and the output end of the output driving circuit outputs the PWM signals to the outside.
2. The multi-logic decision condition controlled PWM pulse width modulation circuit according to claim 1, wherein: the PWM signal shaping circuit comprises a NAND logic trigger chip U1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2 and a transistor Q1, wherein a PWM pulse width modulation signal is electrically connected with the base of the transistor Q1 through the resistor R1, the capacitor C1 is connected with the resistor R1 in parallel, the resistor R2 is electrically connected between the base and the emitter of the transistor Q1, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is electrically connected with two input ends of the NAND logic trigger chip U1 through the resistor R3, two input ends of the NAND logic trigger chip U1 are also electrically connected with the power input end of the NAND logic trigger chip U1 through the resistor R4, the power input end of the NAND logic trigger chip U1 is electrically connected with an external power supply +15V, the power input end of the NAND logic trigger chip U1 is grounded through the capacitor C2, the grounding end of the NAND gate logic trigger chip U1 is grounded, and the output end of the NAND gate logic trigger chip U1 is electrically connected with the input end of the output drive circuit and one input end of the PWM signal control circuit respectively.
3. The multi-logic decision condition controlled PWM pulse width modulation circuit according to claim 1, wherein: the logic condition judging circuit comprises an operational amplifier U3, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a diode D1, a diode D2, a diode D3, a triode Q5 and a triode Q6;
one logic judgment condition signal is connected to one end of the resistor R12, the resistor R13 and the capacitor C6 are connected in parallel between the other end of the resistor R12 and the ground, the other end of the resistor R12 is electrically connected to the non-inverting input end of the operational amplifier U3 through the resistor R14, the resistor R17 is electrically connected between the non-inverting input end and the output end of the operational amplifier U3, the inverting input end of the operational amplifier U3 is electrically connected to the reference voltage +5VREF through the resistor R15, the resistor R16 and the capacitor C7 are connected in parallel between the inverting input end of the operational amplifier U3 and the ground, the positive power supply input end of the operational amplifier U3 is grounded through the capacitor C8, the negative power supply input end of the operational amplifier U3 is grounded through the capacitor C9, the output end of the operational amplifier U3 is electrically connected to the power supply +15V through the resistor R18, and the output end of the operational amplifier U3 is electrically connected to the positive electrode 1, the cathode of the diode D1 is electrically connected with the other input end of the PWM signal control circuit;
the other logic judgment condition signal is connected to the anode of the diode D2, and the cathode of the diode D2 is electrically connected with the other input end of the PWM signal control circuit;
the other logic judgment condition signal is connected to the base of the transistor Q5 through the resistor R19, the resistor R20 is electrically connected between the base and the emitter of the transistor Q5, the emitter of the transistor Q5 is grounded, the collector of the transistor Q5 is electrically connected to +15V of the power supply through the resistor R21, the collector of the transistor Q5 is electrically connected to the base of the transistor Q6 through the resistor R22, the emitter of the transistor Q6 is electrically connected to +15V of the power supply, the collector of the transistor Q6 is grounded through the resistor R23, the collector of the transistor Q6 is electrically connected to the positive electrode of the diode D3 through the resistor R24, and the negative electrode of the diode D3 is electrically connected to the other input terminal of the PWM signal control circuit.
4. The multi-logic decision condition controlled PWM pulse width modulation circuit according to claim 1, wherein: the PWM signal control circuit comprises a D flip-flop chip U2,A resistor R9, a resistor R10, a resistor R11, a capacitor C4, a capacitor C5, and a transistor Q4, wherein a preset terminal S1 of the D flip-flop chip U2 is grounded, a data terminal D1 and a power input terminal VDD of the D flip-flop chip U2 are respectively electrically connected to +15V of a power supply, a power input terminal VDD of the D flip-flop chip U2 is grounded through the capacitor C4, a clock signal terminal C1 of the D flip-flop chip U2 is electrically connected to an output terminal of the PWM signal shaping circuit, a reset terminal R1 of the D flip-flop chip U2 is electrically connected to an output terminal of the logic condition determining circuit, a ground terminal VSS of the D flip-flop chip U2 is grounded, and an output terminal of the D flip-flop chip U2 is electrically connected to the ground
The resistor R10 and the resistor R11 are sequentially connected in series with the ground, the common end of the resistor R10 and the resistor R11 is electrically connected with the base electrode of the triode Q4, the emitter electrode of the triode Q4 is grounded, and the collector electrode of the triode Q4 is electrically connected with the other input end of the output driving circuit.
5. The multi-logic judgment condition controlled PWM pulse width modulation circuit according to any one of claims 1 to 4, wherein: the output driving circuit comprises a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C3, a triode Q2 and a triode Q3, wherein the output end of the PWM signal shaping circuit is grounded through the resistor R7, the output end of the PWM signal shaping circuit is electrically connected with one end of the resistor R6, the other end of the resistor R6 is electrically connected with the base of the triode Q2 and the base of the triode Q3, the resistor R5 is connected with the resistor R6 in parallel, the resistor R8 and the capacitor C3 are connected between the other end of the resistor R6 and the ground in parallel, the collector of the triode Q2 is electrically connected with +15V, the collector of the triode Q3 is grounded, and the emitter of the triode Q2 is electrically connected with the emitter of the triode Q3 and used as the output end to output PWM signals.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117792372A (en) * | 2024-02-28 | 2024-03-29 | 广州市品众电子科技有限公司 | Infrared emission chip with constant current drive, cascading system and driving method |
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2021
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117792372A (en) * | 2024-02-28 | 2024-03-29 | 广州市品众电子科技有限公司 | Infrared emission chip with constant current drive, cascading system and driving method |
| CN117792372B (en) * | 2024-02-28 | 2024-06-07 | 广州市品众电子科技有限公司 | Infrared emission chip with constant current drive, cascading system and driving method |
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