CN215008218U - Substrate and memory device including the same - Google Patents

Abstract

The utility model relates to a substrate, include: a core layer formed of a dielectric material; a conductive pattern formed on the first surface of the core layer, a plating process line of the conductive pattern including at least one conductive pattern opening, at least a portion of at least one signal line of the conductive pattern being electrically disconnected from the plating process line at the at least one conductive pattern opening; a solder mask covering the conductive pattern, the solder mask including an electrical contact opening exposing the electrical contact portion and at least one solder mask opening exposing the at least one conductive pattern opening of the plating process line such that the core layer and the conductive pattern are not covered by the solder mask at the at least one solder mask opening; and at least one curable filling part formed of a curable material filling the at least one solder resist mask opening and the at least one conductive pattern opening. The present invention also relates to a semiconductor device including the above substrate.

Description

Substrate and memory device including the same

Technical Field

The present invention relates to a substrate, and more particularly, to a substrate in which an opening at a disconnection of a signal line and an electroplating process line is filled with a curable material additionally formed. Furthermore, the present invention relates to a memory device comprising such a substrate.

Background

The strong growth in demand for portable consumer electronics has driven the need for high capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory cards, have been widely used to meet the increasing demand for digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, make such storage devices ideal for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game consoles, PDAs and cellular telephones.

With the rapid development of the electronic industry, the size of electronic products is gradually reduced, and the integration level is gradually improved. Accordingly, to integrate more electronic components and electrical contact structures over a smaller area, substrates for electronic products also face manufacturing challenges. Typically, the substrate has conductive patterns formed on a surface of its core layer, and electrical signals are conducted from electronic components (such as memory die) mounted on the substrate through signal lines in the conductive patterns and routed to external electrical connection structures on the substrate, such as contact fingers, solder balls, solder pads, and the like. A plating layer of a conductive material such as nickel (Ni)/gold (Au) is usually electroplated on the electrical contact structure to protect and improve the conductive performance.

During the plating process of electroplating the above-mentioned conductive material over the electrical contact structures, it is necessary to supply an electrical current provided by an external current source to these electrical contact structures. As an example, during a plating process using an electrolyte solution of a metal cation compound, electrons are supplied to these electrical contact structures, so that metal cations in the electrolyte solution are reduced by getting electrons and are deposited on the surfaces of these electrical contact structures, thereby forming a plated layer of metal.

In the conventional manufacturing process of a substrate, two or more signal lines are generally connected to the same plating process line to supply a current required during the plating process. Therefore, it is necessary to form openings in the solder resist mask to remove portions of the plating process lines in the openings by applying an etch-back process through the openings after the plating process to electrically disconnect the signal lines from each other and/or to electrically disconnect the plating process lines from the signal lines, thereby preventing short circuits between the signal lines and reducing antenna effects due to connection with the longer plating process lines. However, in this process, the opening in the solder mask reserved for the etch-back process reduces the structural integrity of the substrate and is not accepted by some customizers of the substrate. In addition, techniques of the substrate without a reserved etch-back opening on the solder mask have been currently developed, but these techniques have the drawback of being costly and incompatible with conventional substrate manufacturing processes.

SUMMERY OF THE UTILITY MODEL

The above disadvantages are at least partly overcome by a substrate according to the invention. Specifically, the substrate according to the present invention can plate the electrical contact portions of the signal lines that have been covered with the solder resist mask using the plating process lines, and electrically disconnect the signal lines and/or the signal lines and the plating process lines after the plating, achieving a solder resist mask opening for applying the etch-back process that is not exposed on the solder resist mask of the final substrate product.

In an aspect of the present invention, there is provided a substrate, including: a core layer formed of a dielectric material and including a first surface and a second surface opposite to the first surface; a conductive pattern formed on the first surface of the core layer, the conductive pattern including at least one signal line and a plating process line, and each of the at least one signal line including an electrical contact portion formed at one end thereof, the electrical contact portion having a plating layer, the plating process line being electrically connected to the at least one signal line simultaneously during a plating process of the plating layer of the electrical contact portion to thereby supply a current required for the plating, wherein the plating process line further includes at least one conductive pattern opening at which at least a portion of the at least one signal line is electrically disconnected from the plating process line; a solder mask covering the conductive pattern, the solder mask including an electrical contact opening exposing the electrical contact portion and at least one solder mask opening exposing the at least one conductive pattern opening of the plating process line such that the core layer and the conductive pattern are not covered by the solder mask at the at least one solder mask opening; and at least one curable filling part filling the at least one solder mask opening and the at least one conductive pattern opening, the at least one curable filling part being formed of a curable material.

In one embodiment, the curable material is at least partially flowable during filling of the at least one soldermask opening and the at least one conductive pattern opening.

In one embodiment, the curable material is a thermosetting resin.

In one embodiment, the thermosetting resin is selected from an epoxy resin, a polyimide-based resin, or a maleimide-based resin mixed with inorganic filler particles.

In one embodiment, an upper surface of the at least one curable filling part is flush with an upper surface of the solder mask.

In one embodiment, a die attach film on the soldermask is also included, covering at least some of the curable fill.

In one embodiment, the cured at least one curable filler is similar in material properties and intimately bonded to the die attach film.

In one embodiment, the die attach film is affixed to the soldermask to cover at least some of the curable fill portions before the curable material is fully cured.

In one embodiment, the upper surface of the at least one curable filling part is higher than the upper surface of the solder mask before the die attach film is attached, and the die attach film presses the at least one curable filling part after the die attach film is attached so that the upper surface of the at least one curable filling part is flush with the upper surface of the solder mask.

According to another aspect of the present invention, there is provided a memory device comprising the substrate described in any of the above embodiments.

Drawings

The drawings illustrate embodiments according to the present invention and prior art substrates, which are not drawn to scale and do not in any way limit the meaning and scope of the claimed subject matter. On the contrary, the drawings are for illustrative purposes only and it is not to be understood that all the features appearing in the drawings are necessary or preferred features of the technical solution. Some features or structures may not be shown in some of the views for clarity of illustration. In the flow chart, the order of the method steps should not be construed as being limited to the order shown. Like reference numerals refer to like features throughout the several views of the drawings, in which:

FIGS. 1A-1C are side cross-sectional views of a substrate according to the prior art;

fig. 2A is a top view of a substrate according to one embodiment of the present invention;

FIG. 2B is a side cross-sectional view of the substrate shown in FIG. 2A taken along line X-X;

fig. 3A is a top view of a substrate according to another embodiment of the present invention;

FIG. 3B is a side cross-sectional view of the substrate shown in FIG. 3A taken along line X-X;

fig. 4 is a side cross-sectional view of a memory device according to one embodiment of the invention;

fig. 5 is a flow chart illustrating a process of manufacturing a substrate according to an embodiment of the present invention; and is

Fig. 6A-6H are side cross-sectional views illustrating an in-process structure during various steps of a manufacturing process of a substrate according to an embodiment of the invention.

Detailed Description

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art. The terms "first," "second," and the like, as used in the description and in the claims, may be used to describe various elements, components, regions, layers, steps and/or sections, but do not denote any order, quantity or importance, but rather are used to distinguish one element, component, region, layer, step and/or section. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

Spatially relative terms, such as "on …," "under …," "upper," "lower," "above," "below," and the like, may describe herein, for ease of description, the illustrated relationship of one element or feature to at least one other element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device is turned over, an element or feature described as being "below," "beneath," or "beneath" another element or feature would then be oriented above the other element. Further, it will be understood that when an element or feature is referred to as being "between" two elements or features, it can be considered that the element or feature is the only element or feature between the two elements or features, or that at least one intervening element or feature may also be present. It will also be understood that when an element or feature is referred to as being "on …," "connected to," "coupled to," or "attached to" another element or feature, it can be directly "on …," "connected to," "coupled to," or "attached to" the other element or feature, or at least one intervening element or feature may also be present. In contrast, when an element or feature is referred to as being "directly on …", "directly connected to", "directly coupled to", or "directly attached to" another element or feature, there are no intervening elements or features present.

These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that are to be understood as "including, but not limited to," and may be used interchangeably. The terms "or" and "as used herein mean, and are used interchangeably with, the term" and/or, "unless the context clearly dictates otherwise. As used herein, "such as" refers to the phrase "such as, but not limited to," and is used interchangeably therewith.

Fig. 1A is a side cross-sectional view of a prior art substrate 100. The substrate 100 includes: a core layer 120, the core layer 120 having opposing first and second surfaces 122, 124; a conductive pattern formed on the first surface 122 of the core layer 120, including a signal line 144 and a plating process line 146; and a solder mask 160 covering the signal lines 144 and the plating process lines 146. The signal line 144 includes an electrical contact portion 142 for external electrical connection. The electrical contact portion 142 is plated with a plating layer 143. During a plating process for forming the plating layer 143, the plating process line 146 is electrically connected to the electrical contact portion 142 of the signal line 144, and simultaneously supplies a current required for plating to the electrical contact portion 142 by an external current source (not shown). During the plating process, both the signal line 144 and the plating process line 146 are electrically connected to each other. It will be appreciated that in high frequency operation, the connection of the signal line 144 to the longer plating process line 146 results in a higher antenna effect and potential interference with the electrical signal, and therefore requires the signal line to be electrically disconnected from the plating process line after the plating process. Further, in the case where there are a plurality of signal lines 144, in order to facilitate the supply of current to the plurality of signal lines 144 with the same plating process line 146 during the plating process, the signal lines 144 may be at least partially electrically connected to each other. Therefore, it is also necessary to break the electrical connection between the signal lines 144 after the plating process in order to independently transmit the electrical signals. In order to break the above-mentioned electrical connection, an opening is formed in the solder resist mask 160 at a portion corresponding to the plating process line, and an etch-back process is applied through the opening to form a conductive pattern opening at a corresponding position of the plating process line, thereby breaking the electrical connection between the signal line and the plating process line and breaking the electrical connection between the plurality of signal lines. The conductive pattern opening 148a and the solder mask opening 162a are exemplarily shown in fig. 1A in the middle of the substrate, and the conductive pattern opening 148b and the solder mask opening 162b are at the edge of the substrate.

However, the above process requires the formation of openings 162a, 162b in solder mask 160. This results in that the first surface 122 of the core layer 120 is disadvantageously directly exposed to the outside at the location of the openings 162a, 162b after the etch-back process is applied. This reduces the integrity of the protection of soldermask 160 for substrate 100 as a whole and does not meet the design requirements of many customizers of the substrate. By way of example, when electrical contact portion 142 is used to connect to a Ball Grid Array (BGA) of a chip, where underfill is employed between the BGA and the electrical contacts, the underfill material tends to not completely fill openings 162 due to the presence of solder mask openings 162, thereby creating voids that affect the moisture resistance, sealing, and mechanical properties of substrate 100.

Fig. 1B is a side cross-sectional view of another prior art substrate 100'. The substrate 100 'includes a die attach film 180, the die attach film 180 being affixed over the solder mask 160 of the substrate 100' and covering at least some of the solder mask openings 162a, 162 b. Although at least some of the solder mask openings 162a, 162b are covered by the die attach film 180, voids 190a, 190b still exist in the solder mask 160 and the conductive pattern at the corresponding locations covered. This reduces the integrity of the substrate 100' and does not meet the design requirements of many customizers of the substrate. For example, when the electrical contacts 142 are used to connect via wire bonds to semiconductor die that are adhered to the substrate 100 with a die attach film, these voids 190a, 190b can potentially affect the moisture resistance, sealing, and mechanical properties of the substrate 100, degrade the mechanical support to the semiconductor die, and are not accepted by some substrate customizers.

FIG. 1C is a side cross-sectional view of yet another prior art substrate 100 ". The substrate 100 "includes a curable die attach film 180 ', the curable die attach film 180 ' being affixed over the soldermask 160 of the substrate 100 ' and covering at least some of the soldermask openings 162a, 162 b. Unlike the conventional die attach film 180, the curable die attach film 180' is at least partially flowable during application and can be pressed at least partially into and fill the solder mask openings 162a, 162b by the pressure applied thereon. However, since the curable die attach film 180 'tends to overflow to the periphery under pressure at the edge of the substrate 100 ", the solder mask opening 162b at the edge tends not to be completely filled, leaving a void 190 b'. Furthermore, the cost of the curable die attach film 180' is much higher than the conventional die attach film 180 and therefore impacts the economics of the substrate 100 ″.

The substrate according to the present invention overcomes, at least in part, the disadvantages of the conventional substrate 100 described above, and can be compatible with conventional substrate manufacturing processes while taking into account economy. In other words, the substrate according to the present invention can be formed by performing the plating and etch-back processes after forming the solder resist mask, and there is no opening on the solder resist mask to expose the core layer and the conductive pattern, and there is no need to use a curable die attach film, which is expensive. An embodiment of a substrate according to the present invention will be described in detail below with reference to fig. 2A to 3B.

Fig. 2A is a top view of a substrate 200 according to an embodiment of the present invention; fig. 2B is a side cross-sectional view of the substrate 200 shown in fig. 2A along line X-X. As shown in fig. 2A and 2B, in this embodiment, the substrate 200 includes a core layer 220 formed of a dielectric material, the core layer 220 having opposing first and second surfaces 222, 224. The substrate 200 also includes a conductive pattern 240 formed on the first surface 222 of the core layer 220. As shown by the dotted line blocks in fig. 2A and 2B, the conductive pattern 240 includes signal lines 244a, 244B and a plating process line 246. The signal lines 244a, 244b include electrical contact portions 242a, 242b formed at one ends thereof, respectively, and the electrical contact portions 242a, 242b have plating layers 243a, 243b, respectively. During the plating process of the plating layer of the electrical contact portions 242a, 242b, one end of the plating process line 246 is electrically connected to an external current source (not shown), and current is supplied to the signal lines 244a, 244b via the plating process line 246, respectively, thereby supplying current required for plating to the electrical contact portions 242a, 242 b. The substrate 200 also includes a solder mask 260a that covers the first surface 222 of the core layer 220 and the conductive pattern 240 on the first surface 222. Soldermask 260a includes electrical contact openings 264a through which electrical contact portions 242a, 242b are exposed for external electrical connection. Conductive pattern openings 248a, 248b are provided at the location of at least portions of the plating process line 246, such that at said conductive pattern openings 248a, 248b, at least portions of the signal lines 244a, 244b are electrically disconnected from the plating process line 246, and electrical connection between the signal lines 244a, 244b is disconnected. The solder mask 260a covering the plating process line 246 has solder mask openings 262a, 262b at locations corresponding to the conductive pattern openings 248a, 248b, respectively.

The substrate 200 further comprises curable fillers 270a, 270b, and the curable fillers 270a, 270b fill in the conductive pattern opening 248a, solder mask opening 262a and conductive pattern opening 248b, solder mask opening 262b, respectively, to cover the portions of the core layer 220 not covered by the solder mask 260a and the sidewalls of the plating process line 246 and solder mask 260a at that location. In this way, the substrate 200 has better structural integrity. Gaps in the underfill material are prevented in the case of a BGA attached to a chip and voids in the substrate are prevented in the case of a semiconductor die attached over the substrate, resulting in better sealing, moisture resistance and mechanical properties.

As shown in fig. 2A and 2B, in the present embodiment, the upper surfaces of the curable filling parts 270a, 270B are flush with the upper surface of the solder resist mask 260 a. Thus, the surface of the substrate 100 is flat, which is advantageous for the subsequent process. In some embodiments, the curable fillers 270a, 270b have a cylindrical structure that substantially corresponds to the shape of the conductive pattern openings 248a, 248b and solder mask openings 262a, 262b to promote a more complete filling of the curable material of the curable fillers 270a, 270b therein and a tighter bond with the cylindrical sidewalls of the openings.

In some embodiments, optionally, substrate 200 further comprises a backside conductive pattern (not shown) and a backside solder mask 260b on second surface 224 of core layer 220, and backside solder mask 260b covers backside conductive pattern and second surface 224 of core layer 220. In some embodiments, the backside conductive pattern on the second surface 224 may be electrically connected with at least a portion of the conductive pattern 240 by an electrical connection structure such as a conductive via.

In the substrate 200 shown in fig. 2A and 2B, the core layer 220 may be formed of any suitable dielectric material, including organic (polymer) dielectric materials such as, but not limited to, phenolic resins, epoxy resins, BT resins (bismaleimide-triazine resins), polyimides, polytetrafluoroethylene, and the like, as well as inorganic dielectric materials such as, but not limited to, glass, fiberglass, silicon, gallium nitride, and the like, as well as any other suitable dielectric material, or combinations thereof.

The conductive pattern 240 of the substrate 200, including the signal lines 244a, 244b and the plating process line 246, may be applied using any suitable technique, such as, but not limited to, printing, spraying, plating, etching, photolithography, and the like, or combinations thereof, and may be formed from any suitable conductive material, including metallic conductive materials, such as, but not limited to, copper, gold, aluminum alloys, and the like, as well as any other suitable conductive material, such as, but not limited to, nano-or micro-conductive particles dispersed in a solvent or medium, polymeric conductive materials, and the like, or combinations thereof. The plating layers 243a, 243b on the electrical contact portions 242a, 242b of the substrate 200 may be applied using any suitable plating technique and may be formed of any suitable material, including but not limited to Ni, Au, or alloys or combinations thereof.

The curable fills 270a, 270b of the substrate 200 may be formed using any suitable curable material. The curable material is at least partially flowable when applied into the solder mask openings 262a, 262b and the conductive pattern openings 248a, 248b to facilitate injection, and fully cured in a subsequent process to securely fill in the openings and provide a seal. By way of example, the curable material may be cured by means such as, but not limited to, UV curing, thermal curing, and the like. As an example, the curable material is a thermosetting material, which may be selected from thermosetting resins such as, but not limited to, epoxy resins, polyimide-based resins, or maleimide-based resins. In some embodiments, inorganic filler particles such as, but not limited to, metal oxides, metal hydroxides, metal carbonates, or metal silicates are mixed into the thermosetting material in order to improve moisture resistance and adjust viscosity and thixotropy. As an example, the curable material may be an epoxy material mixed with silica filler particles, which is substantially similar to the material of the die attach film or silver paste used to attach the die to the substrate, so that a tighter bond may be formed with the die attach film or silver paste and the sidewalls of the soldermask openings 262a, 262 b. Optionally, the curable material may also contain a curing accelerator to promote the formation of a three-dimensional network structure, for example under heating, to cure the material. Generally, the curable material is less expensive than a common solder resist mask material, and thus the cost can be further reduced.

As described above, in prior art substrates 100, 100 ', 100 ", there is a directly exposed solder mask opening 162a, 162b, or a gap 190a, 190 b' in the substrate, thereby reducing the structural integrity, sealing, moisture resistance, and mechanical properties of the substrate 100. In contrast, the substrate 200 according to the above-described embodiment of the present invention is filled with the curable fillers 270a, 270b in the solder resist mask openings 262a, 262b of the solder resist mask 260a and the conductive pattern openings 248a, 248b of the conductive pattern 240, so that the solder resist mask 260a and the curable fillers 270a, 270b cover the first surface 222 of the core layer 220 and the conductive pattern 240 as a whole, exposing only the electrical contact portions 242a, 242 b. Thus, the substrate 200 according to an embodiment of the present invention has better structural integrity than the prior art substrate 100. In addition, it is possible to prevent a gap from being generated in an underfill material due to insufficient underfill in the case of a Ball Grid Array (BGA) connected to a chip, and to avoid a void in a substrate in the case of attaching a semiconductor die over the substrate, thereby having better sealing, moisture-proof, and mechanical properties, and providing better mechanical support to the semiconductor die.

In addition, the order of the manufacturing steps of the substrate 200 according to an embodiment of the present invention is similar to the overall process order of the manufacturing steps of the conventional substrate 100, and the curable filling parts 270a and 270b are additionally formed, so that it is possible to have better compatibility with the conventional manufacturing process. The curable material of the curable filling part is, in turn, inexpensive per se and can be injected into all solder mask openings 262a, 262b and conductive pattern openings 248a, 248b of the conductive pattern 240 on the substrate 200 (as will be described in more detail below) in one operation by means of a programmed injection head, thereby reducing material and process costs and improving throughput.

Fig. 3A is a top view of a substrate according to another embodiment of the present invention; fig. 3B is a side cross-sectional view of the substrate shown in fig. 3A taken along line X-X. Referring to fig. 3A and 3B, a substrate 300 according to another embodiment of the present invention includes a core layer 320, a conductive pattern 340 including signal lines 344a and 344B and plating process line 346, a solder mask 360a, curable fills 370a and 370B, and optional backside conductive pattern (not shown) and backside solder mask 360B. The above-described features are substantially similar to corresponding features in the substrate 200 and may be formed from the same processes and materials, and thus, a description thereof will not be repeated. Substrate 300 differs from substrate 200 in that substrate 300 further includes a die attach film 380 affixed over soldermask 360 a. The die attach film 380 covers at least some of the curable filler portions 370a, 370 b. The die attach film 380 overlying the soldermask 360a exerts a downward force on the curable filler portions 370a, 370b to make their surfaces more planar and more tightly filled for the respective openings, further ensuring that the upper surfaces of the curable filler portions 370a, 370b are substantially flush with the upper surface of the soldermask 360a for subsequent mounting of components such as semiconductor die.

Further, since the conductive pattern openings 348a, 348b and the solder mask openings 362a, 362b have been filled and occupied by the curable filling portions 370a, 370b, the solid ordinary die attach film 380 can be used without using an expensive die attach film having at least partial flowability, thereby reducing costs.

In some embodiments, the curable material of curable fills 370a, 370b of substrate 300 is at least partially flowable during filling of conductive pattern openings 348a, 348b and solder mask openings 362a, 362 b. It will be appreciated that although the amount of curable material injected into each opening is designed to be substantially the same as the volume of the corresponding conductive pattern opening and solder mask opening after curing, the curable material injected with the injection head may form a convex droplet and partially protrude beyond the upper surface of solder mask 360a due to the surface tension of the fluid and possible volume changes during curing. In this embodiment, the die attach film 380 is applied before the curable material is completely cured to flatten the curable material filled in the conductive pattern openings 348a, 348b and the solder mask openings 362a, 362b so that the upper surface thereof is flush with the upper surface of the solder mask 360a, thereby further improving the flatness of the substrate 300.

Fig. 4 is a side cross-sectional view of a memory device 4000 according to one embodiment of the invention. Referring to fig. 4, a memory device 4000 according to an embodiment of the present invention includes the above-described substrate according to the present invention, a die attach film 480 attached over the substrate, and a semiconductor die 490 attached over the substrate via the die attach film 480. The conductive pattern openings 448a, 448b and solder mask openings 462a, 462b in the substrate 400 according to the present invention are filled with the curable filling parts 470a, 470b, and the upper surfaces of the curable filling parts 470a, 470b are substantially flush with the upper surface of the solder mask 460a, and therefore, there is no gap between the semiconductor die 490 and the substrate in the memory device 4000 and no gap in the substrate, thereby providing improved moisture resistance, sealing and mechanical properties. In addition, gaps due to insufficient filling may also be avoided during packaging of the memory device 4000 with a molding compound (not shown).

The manufacturing flow of the substrates 200, 300 according to the present invention will be described below with reference to the flow chart of fig. 5 and the schematic diagrams 6A-6H. The materials and methods used to form the various features of the structures and the final products during the manufacturing process are substantially the same as described above with respect to the corresponding structures and, therefore, will not be repeated here.

Fig. 6A is a side cross-sectional view illustrating structure 600 in-process after step 510 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. At step 510, a core layer 620 of dielectric material is provided, the core layer 620 comprising opposing first and second surfaces 622, 624. Then, a conductive pattern 640 is formed on the first surface 622 of the core layer 620. The conductive pattern 640 includes a signal line 644a and other signal lines (not shown), and a plating process line 646. The signal line 644a is formed at one end thereof with an electrical contact portion 642a, and the other signal lines are each formed at one end thereof with other electrical contact portions (not shown). Optionally, a backside conductive pattern (not shown) is formed on the second surface 624 of the core layer 620. The conductive pattern 640 and optional backside conductive pattern may be formed of any suitable material using any suitable technique described above.

Fig. 6B is a side cross-sectional view illustrating structure 600 in-process after step 520 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. At step 520, solder mask 660a is applied over first surface 622 of core layer 620 and conductive pattern 640, such that solder mask 660a covers conductive pattern 640 and first surface 622 of core layer 620. Solder mask 660a reserves electrical contact opening 664a such that electrical contact 642a and other electrical contacts are exposed through reserved electrical contact opening 664 a. Optionally, a backside solder mask 660b is formed on the second surface 624 of the core layer 620 to cover the second surface 624 of the core layer 620 and an optional backside conductive pattern (not shown). Soldermask 660a, optional backside soldermask 660b may be formed of any suitable material using any suitable technique described above.

Fig. 6C is a side cross-sectional view illustrating structure 600 in-process after step 530 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. At step 530, an external current source required for plating is connected to plating process line 646, plating layer 643a onto electrical contact portion 642a, while plating other plating layers (not shown) onto other electrical contact portions (not shown). As an example, in the case of performing plating with an electrolytic solution of a metal cation compound, the electrolytic solution is applied to the electric contact portion 642a and other electric contact portion locations, and the cathode of an external current source is connected to one end of the plating process line 646, and the anode of the external current source is connected to the electrolytic solution to supply electrons, which are carriers of electric current, to the metal cations in the electrolytic solution via the electric contact portion 642a and other electric contact portions, so that the metal cations are reduced and deposited on the electric contact portion 642a and other electric contact portions, thereby forming a plated layer 643a covering the electric contact portion 642a and other plated layers covering the other electric contact portions.

Fig. 6D is a side cross-sectional view illustrating structure 600 in-process after step 540 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. At step 540, solder mask openings 662a, 662b are formed in the solder mask 660a where the conductive pattern openings 648a, 648b are to be formed in the plating process line 646, and an etch-back process is applied to the plating process line 646 through the solder mask openings 662a, 662b to form the conductive pattern openings 648a, 648 b. In some embodiments, the solder mask openings 662a, 662b are first formed in the solder mask 660a, followed by an etch back process applied through the solder mask openings 662a, 662 b. In this case, the solder mask openings 662a, 662b may be formed at the same time as the solder mask 660a is applied, or may be formed in the solder mask 660a by photolithography, etching, or the like after the solder mask 660a is applied. In other embodiments, the solder mask openings 662a, 662b and the conductive pattern openings 648a, 648b may be formed simultaneously through the solder mask 660a and the plating process line 646 in the same process step. It is understood that the conductive pattern openings 648a, 648b can have any suitable shape and size that is at least no less than the width of the plating process line 646 at that location so that the plating process line 646 is completely electrically disconnected at the conductive pattern openings 648a, 648 b.

Fig. 6E is a side cross-sectional view illustrating structure 600 in-process after step 550 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. At step 550, a curable material having at least partial flowability is applied to fill the solder mask openings 662a, 662b and the conductive pattern openings 648a, 648 b. It will be appreciated that the amount of curable material applied in each solder mask opening and conductive pattern opening is no less than the sum of the volumes of the respective solder mask opening and conductive pattern opening after curing to completely fill the respective solder mask opening and conductive pattern opening after curing. In some embodiments, the location profile of each of the solder mask openings 662a, 662b and the conductive pattern openings 648a, 648b may be input into the implanter according to the design of the substrate. The implanter may program the travel trajectory of the injection head and the amount of injection at each opening according to the positional profile so that an appropriate amount of curable material is injected into each solder mask opening and conductive pattern opening during a single injection process.

Fig. 6F is a side cross-sectional view illustrating structure 600 in process after optional step 560 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. In optional step 560, die attach film 680 is affixed over soldermask 660a, and die attach film 680 covers at least some of soldermask openings 662a, 662 b. In some embodiments, die attach film 680 covers each of solder mask openings 662a, 662 b. The curable material applied in step 550 is then cured, and the resulting structure 600 as shown in fig. 6F substantially corresponds to the substrate 300 according to another embodiment of the present invention shown in fig. 3A-3B.

The curable material has at least partial flowability during application of the curable material to the solder mask openings 662a, 662b and the conductive pattern openings 648a, 648 b. Accordingly, in some embodiments, a sufficient amount of curable material 670a ', 670 b' is applied that forms an upper surface that protrudes beyond an upper surface of soldermask 660a due to surface tension, as shown in FIG. 6G. To ensure that the resulting substrate surface is flat, the curable material 670a ', 670 b' that protrudes beyond the upper surface of the solder mask 660a needs to be flattened to completely fill the solder mask openings 662a, 662b and the conductive pattern openings 648a, 648 b. In some embodiments, after in-process structure 600 is formed in step 550 as shown in fig. 6G, die attach film 680 is adhered to the upper surface of soldermask 660a to cover curable material 670a ', 670 b' and flattened so that its upper surface is flush with the upper surface of soldermask 660 a. Flattening the curable material 670a ', 670 b' with the die attach film 680 may facilitate more complete filling of the solder mask openings 662a, 662b and the conductive pattern openings 648a, 648b, venting any air or voids that may remain, and more fully and securely bonding with the sidewalls of the solder mask openings 662a, 662b and the conductive pattern openings 648a, 648b such that an improved seal is formed therewith after curing.

Next, the curable material 670a ', 670B' is completely cured into curable filling portions 670a, 670B, and the resulting structure 600 as shown in fig. 6H substantially corresponds to the substrate 300 according to another embodiment of the present invention shown in fig. 3A-3B. In this way, the curable material 670a ', 670 b' can be planarized in the same process step as the pasting die attach film 680, thereby simplifying the process in the case of using a curable material with higher surface tension or lower fluidity. Furthermore, where the curable material is similar in nature to die attach film 680, curable fills 670a, 670b may form a more integral bond with the sidewalls of attached die attach film 680 and solder mask openings 662a, 662b, thereby improving the integrity of the substrate.

Step 560 shown in fig. 5 is optional and step 560 may not be performed. In such an embodiment, after forming the structure shown in fig. 6E at step 550, the curable material applied at step 550 is cured, and the resulting structure 600 shown in fig. 6E substantially corresponds to the substrate 200 shown in fig. 2A-2B according to one embodiment of the present invention. It will be appreciated that in such embodiments, it may be desirable to ensure that the upper surface is substantially flush with the upper surface of soldermask 660a prior to curing, which may be achieved by using a curable material with a lower surface tension or higher flow, or by additionally flattening the curable material with a flat surface prior to curing.

Fig. 6A-6H illustrate a method of fabrication that is substantially similar to the embodiments of substrates 200 and 300. It will be appreciated that portions of the substrate may be formed using the methods and materials described above, all of which are within the scope of the method of manufacturing the substrate according to the present description.

Although the foregoing refers to particular implementations, it should be understood that the invention is not so limited. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and are within the scope of the disclosure.

Claims (10)

1. A substrate, comprising:

a core layer formed of a dielectric material and including a first surface and a second surface opposite to the first surface;

a conductive pattern formed on the first surface of the core layer, the conductive pattern including at least one signal line and a plating process line, and the at least one signal line each including an electrical contact portion formed at one end thereof, the electrical contact portion having a plating layer, the plating process line being electrically connected to the at least one signal line simultaneously during a plating process of the plating layer of the electrical contact portion, thereby providing a current required for plating, wherein the plating process line further includes at least one conductive pattern opening at which at least a portion of the at least one signal line is electrically disconnected from the plating process line;

a solder mask covering the conductive pattern, the solder mask including an electrical contact opening exposing the electrical contact portion and at least one solder mask opening exposing at least one conductive pattern opening of the plating process line such that the core layer and the conductive pattern are not covered by the solder mask at the at least one solder mask opening; and

at least one curable filling part filling the at least one solder mask opening and the at least one conductive pattern opening, the at least one curable filling part being formed of a curable material.

2. The substrate of claim 1, wherein the curable material is at least partially flowable during filling of the at least one soldermask opening and the at least one conductive pattern opening.

3. The substrate of claim 2, wherein the curable material is a thermosetting resin.

4. A substrate according to claim 3, wherein said thermosetting resin is selected from epoxy resins, polyimide-based resins or maleimide-based resins mixed with inorganic filler particles.

5. The substrate according to any of claims 1-4, characterized in that the upper surface of the at least one curable filling part is flush with the upper surface of the solder mask.

6. The substrate of any of claims 1-4, further comprising a die attach film on the soldermask that covers at least some of the curable fill.

7. The substrate of claim 6, wherein the at least one curable filler after curing is similar in material properties and intimately bonded to the die attach film.

8. The substrate of claim 7, wherein the die attach film is affixed to the solder mask to cover at least some of the curable fill portions before the curable material is fully cured.

9. The substrate of claim 8, wherein an upper surface of the at least one curable filler is higher than an upper surface of the solder mask before the die attach film is attached, and wherein the die attach film presses the at least one curable filler to make the upper surface of the at least one curable filler flush with the upper surface of the solder mask after the die attach film is attached.

10. A memory device comprising the substrate of any one of claims 1-9.

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