CN214384754U

CN214384754U - Substrate and memory device including the same

Info

Publication number: CN214384754U
Application number: CN202120432381.6U
Authority: CN
Inventors: 杨正雄; 史月全; 于强忠; 王艾雯; 锺陈毅; 陈姿蓉; 徐景芛
Original assignee: Western Digital Technologies Inc
Current assignee: Western Digital Technologies Inc
Priority date: 2021-02-26
Filing date: 2021-02-26
Publication date: 2021-10-12
Anticipated expiration: 2031-02-26

Abstract

The utility model relates to a substrate, include: a core layer comprising opposing first and second surfaces; a first conductive pattern including at least one signal line and a plating process line formed on the first surface of the core layer, each of the at least one signal line including an electrical contact portion having a plating layer formed at one end thereof, wherein the at least one signal line is electrically disconnected from the plating process line at an opening of the conductive pattern in the plating process line; a first solder mask covering the first conductive pattern, the first solder mask including an electrical contact opening exposing the electrical contact portion and a solder mask opening exposing the conductive pattern opening of the plating process line such that the core layer and the first conductive pattern are not covered by the first solder mask at the solder mask opening; and a second solder mask filling the solder mask opening and the conductive pattern opening. The present invention also relates to a semiconductor device including the above substrate.

Description

Substrate and memory device including the same

Technical Field

The present invention relates to a substrate, and more particularly, to a substrate covered with a solder resist mask additionally formed at a disconnection of a signal line and an electroplating process line. Furthermore, the present invention relates to a memory device comprising such a substrate.

Background

The strong growth in demand for portable consumer electronics has driven the need for high capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory cards, have been widely used to meet the increasing demand for digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, make such storage devices ideal for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game consoles, PDAs and cellular telephones.

With the rapid development of the electronic industry, the size of electronic products is gradually reduced, and the integration level is gradually improved. Accordingly, to integrate more electronic components and electrical contact structures over a smaller area, substrates for electronic products also face manufacturing challenges. Typically, the substrate has conductive patterns formed on a surface of its core layer, and electrical signals are conducted from electronic components (such as memory die) mounted on the substrate through signal lines in the conductive patterns and routed to external electrical connection structures on the substrate, such as contact fingers, solder balls, solder pads, and the like. A plating layer of a conductive material such as nickel (Ni)/gold (Au) is usually electroplated on the electrical contact structure to protect and improve the conductive performance.

During the plating process of electroplating the above-mentioned conductive material over the electrical contact structures, it is necessary to supply an electrical current provided by an external current source to these electrical contact structures. As an example, during a plating process using an electrolyte solution of a metal cation compound, electrons are supplied to these electrical contact structures, so that metal cations in the electrolyte solution are reduced by getting electrons and are deposited on the surfaces of these electrical contact structures, thereby forming a plated layer of metal.

In the conventional manufacturing process of a substrate, two or more signal lines are generally connected to the same plating process line to supply a current required during the plating process. Therefore, it is necessary to form openings in the solder resist mask to remove portions of the plating process lines in the openings by applying an etch-back process through the openings after the plating process to electrically disconnect the signal lines from each other and/or to electrically disconnect the plating process lines from the signal lines, thereby preventing short circuits between the signal lines and reducing antenna effects due to connection with the longer plating process lines. However, in this process, the opening in the solder mask reserved for the etch-back process reduces the structural integrity of the substrate and is not accepted by some customizers of the substrate. In addition, techniques of the substrate without a reserved etch-back opening on the solder mask have been currently developed, but these techniques have the drawback of being costly and incompatible with conventional substrate manufacturing processes.

SUMMERY OF THE UTILITY MODEL

The above disadvantages are at least partly overcome by a substrate according to the invention. Specifically, the substrate according to the present invention can plate the electrical contact portions of the signal lines that have been covered with the solder resist mask using the plating process lines, and electrically disconnect the signal lines and/or the signal lines and the plating process lines after the plating, achieving a solder resist mask opening for applying the etch-back process that is not exposed on the solder resist mask of the final substrate product.

According to an aspect of the present invention, there is provided a substrate, including: a core layer formed of a dielectric material and including a first surface and a second surface opposite to the first surface; a first conductive pattern formed on the first surface of the core layer, the first conductive pattern including at least one signal line and a plating process line, and each of the at least one signal line including an electrical contact portion formed at one end thereof, the electrical contact portion having a plating layer, the plating process line being electrically connected to the at least one signal line simultaneously during a plating process of the plating layer of the electrical contact portion to thereby provide a current required for the plating, wherein the plating process line further includes a conductive pattern opening at which at least a portion of the at least one signal line is electrically disconnected from the plating process line; a first solder mask covering the first conductive pattern, the first solder mask including an electrical contact opening exposing the electrical contact portion and a solder mask opening exposing the conductive pattern opening of the plating process line such that the core layer and the first conductive pattern are not covered by the first solder mask at the solder mask opening; and a second solder mask filling the solder mask opening and the conductive pattern opening.

In one embodiment, the second solder mask is filled only in the solder mask opening and the conductive pattern opening, and an upper surface of the second solder mask is flush with an upper surface of the first solder mask.

In an embodiment, the upper surface of the second solder mask protrudes from the upper surface of the first solder mask and covers at least the area of the first solder mask around the solder mask opening.

In one embodiment, the second solder mask entirely covers the upper surface of the first solder mask.

In one embodiment, the material of the first and second solder masks is selected from the group consisting of: polyimide, acrylate, polyurethane, epoxy, and urethane.

In one embodiment, the second solder mask is formed from the same material as the first solder mask.

In one embodiment, the second solder mask is formed of a different material than the first solder mask.

In one embodiment, a material interface exists between the first soldermask and the second soldermask.

In one embodiment, there is no material interface between the first soldermask and the second soldermask.

As used herein, electrically disconnecting the signal line from the plating process line refers to electrically disconnecting the signal line from the main portion of the plating process line by breaking the conductive structure at least one location on the plating process line, and does not mean that the signal line and any portion of the plating process line are not physically connected to each other.

According to another aspect of the present invention, there is provided a memory device comprising the substrate described in any of the above embodiments.

Drawings

The drawings illustrate embodiments according to the present invention and prior art substrates, which are not drawn to scale and do not in any way limit the meaning and scope of the claimed subject matter. On the contrary, the drawings are for illustrative purposes only and it is not to be understood that all the features appearing in the drawings are necessary or preferred features of the technical solution. Some features or structures may not be shown in some of the views for clarity of illustration. In the flow chart, the order of the method steps should not be construed as being limited to the order shown. Like reference numerals refer to like features throughout the several views of the drawings, in which:

FIG. 1A is a top view of a substrate according to the prior art;

FIG. 1B is a cross-sectional view of the substrate shown in FIG. 1A taken along line X-X;

fig. 2A is a top view of a substrate according to one embodiment of the present invention;

FIG. 2B is a cross-sectional view of the substrate shown in FIG. 2A taken along line X-X;

fig. 3A is a top view of a substrate according to another embodiment of the present invention;

FIG. 3B is a cross-sectional view of the substrate shown in FIG. 3A taken along line X-X;

fig. 4A is a top view of a substrate according to yet another embodiment of the present invention;

FIG. 4B is a cross-sectional view of the substrate shown in FIG. 4A taken along line X-X;

fig. 5 is a flow chart illustrating a process of manufacturing a substrate according to an embodiment of the present invention; and is

Fig. 6A-6I are cross-sectional views illustrating in-process structures during various steps of a manufacturing process of a substrate according to embodiments of the invention.

Detailed Description

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art. The terms "first," "second," and the like, as used in the description and in the claims, may be used to describe various elements, components, regions, layers, steps and/or sections, but do not denote any order, quantity or importance, but rather are used to distinguish one element, component, region, layer, step and/or section. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

Spatially relative terms, such as "on …," "under …," "upper," "lower," "above," "below," and the like, may describe herein, for ease of description, the illustrated relationship of one element or feature to at least one other element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device is turned over, an element or feature described as being "below," "beneath," or "beneath" another element or feature would then be oriented above the other element. Further, it will be understood that when an element or feature is referred to as being "between" two elements or features, it can be considered that the element or feature is the only element or feature between the two elements or features, or that at least one intervening element or feature may also be present. It will also be understood that when an element or feature is referred to as being "on …," "connected to," "coupled to," or "attached to" another element or feature, it can be directly "on …," "connected to," "coupled to," or "attached to" the other element or feature, or at least one intervening element or feature may also be present. In contrast, when an element or feature is referred to as being "directly on …", "directly connected to", "directly coupled to", or "directly attached to" another element or feature, there are no intervening elements or features present.

These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that are to be understood as "including, but not limited to," and may be used interchangeably. The terms "or" and "as used herein mean, and are used interchangeably with, the term" and/or, "unless the context clearly dictates otherwise. As used herein, "such as" refers to the phrase "such as, but not limited to," and is used interchangeably therewith.

FIG. 1A is a top view of a prior art substrate 100; fig. 1B is a sectional view taken along line X-X in fig. 1A. The substrate 100 includes: a core layer 120, the core layer 120 having opposing first and

second surfaces

122, 124; a first conductive pattern 140 formed on the first surface 122 of the core layer 120, including

signal lines

144a, 144b and a plating process line 146; and a solder mask 160 covering the

signal lines

144a, 144b and the plating process line 146. The

signal lines

144a, 144b include

electrical contact portions

142a, 142b, respectively, for external electrical connection. The

electrical contact portions

142a, 142b are plated with plating layers 143a, 143 b. During the plating process for forming the plating layers 143a, 143b, the plating process line 146 is electrically connected to the

electrical contact portions

142a, 142b of the

signal lines

144a, 144b, and simultaneously supplies the

electrical contact portions

142a, 142b with a current required for the plating by an external current source (not shown). During the plating process, the

signal lines

144a, 144b and the plating process line 146 are all electrically connected to each other. It is understood that in order to enable the signal line 144a and the signal line 144b to transmit different electrical signals, respectively, it is necessary to break the electrical connection between the different signal lines after the plating process. In addition, in high frequency operation, the connection of the signal line with the longer plating process line causes a higher antenna effect and potential interference to the electrical signal, and therefore, the electrical connection between the signal line and the plating process line needs to be disconnected after the plating process. In order to break the above-mentioned electrical connection, an opening 162 is formed in the solder resist mask 160 at a portion corresponding to the connection of the plating process line 146 to the signal line 144a, and an etch-back process is applied through the opening 162 to form a conductive pattern opening 148a at a corresponding position of the plating process line 146, thereby breaking the electrical connection between the signal line 144a and the signal line 144b, and breaking the electrical connection between the signal line 144a and the plating process line 146. Similarly, a portion (not shown) of the plating process line 146 may also be removed by etching back at other positions of the plating process line 146, thereby additionally electrically disconnecting the signal line 144b from the plating process line 146 to reduce the antenna effect.

However, the above process requires the formation of the opening 162 in the solder mask 160. This results in that the first surface 122 of the core layer 120 is disadvantageously directly exposed to the outside at the location of the opening 162 after the etch-back process is applied. This reduces the integrity of the protection of soldermask 160 for substrate 100 as a whole and does not meet the design requirements of many customizers of the substrate. For example, when

electrical contacts

142a, 142b are used to connect to a Ball Grid Array (BGA) of a chip, where underfill is employed between the BGA and the electrical contacts, the underfill material tends to not completely fill the openings 162 due to the presence of solder mask openings 162, thereby creating voids that affect the moisture resistance, sealing, and mechanical properties of the substrate 100.

The substrate according to the present invention overcomes, at least in part, the disadvantages of the conventional substrate 100 described above and is compatible with conventional substrate manufacturing processes. In other words, the substrate according to the present invention can be formed by performing the plating and etch-back processes after forming the solder resist mask, and there is no opening on the solder resist mask to expose the core layer and the conductive pattern. An embodiment of a substrate according to the present invention will be described in detail below with reference to fig. 2A to 4B.

Fig. 2A is a top view of a substrate according to one embodiment of the present invention; fig. 2B is a cross-sectional view of the substrate shown in fig. 2A along line X-X. As shown in fig. 2A and 2B, in this embodiment, the substrate 200 includes a core layer 220 formed of a dielectric material, the core layer 220 having opposing first and

second surfaces

222, 224. The substrate 200 also includes a first conductive pattern 240 formed on the first surface 222 of the core layer 220. As shown by the dotted line box in fig. 2A, the first conductive pattern 240 includes

signal lines

244a, 244b and a plating process line 246. The

signal lines

244a, 244b include

electrical contact portions

242a, 242b formed at one ends thereof, respectively, and the

electrical contact portions

242a, 242b have plating layers 243a, 243b, respectively. During the plating process of the plating layer of the

electrical contact portions

242a, 242b, one end of the plating process line 246 is electrically connected to an external current source (not shown), and current is supplied to the

signal lines

244a, 244b via the plating process line 246, respectively, thereby supplying current required for plating to the

electrical contact portions

242a, 242 b. The substrate 200 also includes a first solder mask 260a that covers the first surface 222 of the core layer 220 and the first conductive pattern 240 on the first surface 222. First solder mask 260a includes electrical contact openings 264a through which

electrical contact portions

242a, 242b are exposed for external electrical connection. Substrate 200 also includes a second solder mask 260 c. A conductive pattern opening 248a is provided at a position of at least a portion of the plating process line 246 such that at least a portion of the signal line 244a is electrically disconnected from the plating process line 246 at the conductive pattern opening 248 a. The first solder mask 260a covering the plating process line 246 has a solder mask opening 262a at a position corresponding to the conductive pattern opening 248a, and the second solder mask 260c is filled in the conductive pattern opening 248a and the solder mask opening 262a, covering a portion of the core layer 220 not covered by the first solder mask 260a and sidewalls of the plating process line 246 and the first solder mask 260a at the position. In this way, the substrate 200 has better structural integrity. In the case of a BGA attached to a chip, it is possible to prevent gaps from being generated in the underfill material, thereby having better sealing, moisture-proof, and mechanical properties. As shown in fig. 2A and 2B, in the present embodiment, the second solder mask 260c fills only the solder mask opening 262A in the first solder mask 260a and the conductive pattern opening 248a in the first conductive pattern, and the upper surface of the second solder mask 260c is flush with the upper surface of the first solder mask 260 a. Thus, the surface of the substrate 100 is flat, which is advantageous for the subsequent process.

In some embodiments, optionally, substrate 200 further comprises a second conductive pattern (not shown) on second surface 224 of core layer 220 and solder mask 260b, and solder mask 260b covers second conductive pattern and second surface 224 of core layer 220. In some embodiments, the second conductive pattern on the second surface 224 may be electrically connected to at least a portion of the first conductive pattern 240 by an electrical connection structure such as a conductive via.

In the substrate 200 shown in fig. 2A and 2B, the core layer 220 may be formed of any suitable dielectric material, including organic (polymer) dielectric materials such as, but not limited to, phenolic resins, epoxy resins, BT resins (bismaleimide-triazine resins), polyimides, polytetrafluoroethylene, and the like, as well as inorganic dielectric materials such as, but not limited to, glass, fiberglass, silicon, gallium nitride, and the like, as well as any other suitable dielectric material, or combinations thereof.

The first conductive pattern 240 of the substrate 200, including the

signal lines

244a, 244b and the plating process line 246, may be applied using any suitable technique, such as, but not limited to, printing, spraying, plating, etching, photolithography, and the like, or combinations thereof, and may be formed of any suitable conductive material, including metallic conductive materials, such as, but not limited to, copper, gold, aluminum alloys, and the like, as well as any other suitable conductive material, such as, but not limited to, nano-or micro-conductive particles dispersed in a solvent or medium, polymeric conductive materials, and the like, or combinations thereof. The plating layers 243a, 243b on the

electrical contact portions

242a, 242b of the substrate 200 may be applied using any suitable plating technique and may be formed of any suitable material, including but not limited to Ni, Au, or alloys or combinations thereof.

First solder mask 260a, second solder mask 260c, and optional backside solder mask 260b of substrate 200, which may also be referred to as a layer of green oil, solder mask, etc. in some scenarios, may be applied using any suitable known solder mask process, such as, but not limited to, a liquid photo-imageable solder mask process or a dry film photo-imageable solder mask process, etc. Specifically, the material of the dry film photoimageable solder mask may be selected from, for example, but not limited to, polyimide, acrylate, polyurethane, etc., which are solid films under application conditions, while the material of the liquid photoimageable solder mask may be selected from, for example, but not limited to, acrylic, epoxy, urethane, etc., which are liquid under application conditions and curable under specific conditions (e.g., photocured, such as UV curing).

As described above, in the conventional substrate 100, in order to break the electrical connection between the

signal lines

144a, 144b, it is necessary to form the solder resist mask opening 162a in the first solder resist mask 160 of the substrate 100 at the desired break between the signal lines in order to remove the portion 148a of the plating process line 146 at the conductive pattern opening by applying an etch-back process. As a result, the first surface 122 of the core layer 120 of the conventional substrate 100 is caused to be exposed to the external environment at the opening 162a, thereby reducing the structural integrity of the substrate 100. In contrast, the substrate 200 according to the above-described embodiment of the present invention is filled with the second solder mask 260c in the solder mask opening 262a of the first solder mask 260a and the conductive pattern opening 248a of the first conductive pattern, so that the first and

second solder masks

260a and 260c cover the first surface 222 of the core layer 220 and the first conductive pattern 240 as a whole, exposing only the

electrical contact portions

242a, 242 b. Thus, the substrate 200 according to an embodiment of the present invention has better structural integrity than the prior art substrate 100. In addition, it is possible to prevent a gap from being generated in an underfill material in the case of a Ball Grid Array (BGA) connected to a chip, thereby having better sealing, moisture-proof, and mechanical properties.

In addition, the order of the manufacturing steps of the substrate 200 according to an embodiment of the present invention is similar to the overall process order of the manufacturing steps of the conventional substrate 100, and the second solder mask 260c is additionally formed, so that it may have better compatibility with the conventional manufacturing process.

Fig. 3A is a top view of a substrate according to another embodiment of the present invention; fig. 3B is a cross-sectional view of the substrate shown in fig. 3A along line X-X. Referring to fig. 3A and 3B, a substrate 300 according to another embodiment of the present invention includes features of a core layer 320, signal lines 344a, 344B and plating process line 346 of a first conductive pattern 340, a first solder mask 360a and optionally a backside second conductive pattern and backside solder mask 360B, which are substantially similar to corresponding features in substrate 200 and may be formed by the same process and materials, and thus, will not be described again. Substrate 300 differs from substrate 200 in that second solder mask 360c protrudes from the upper surface of first solder mask 360a and covers a partial area of first solder mask 360a around solder mask opening 362 a. The substrate 300 does not require a planarization process after the application of the material of the second solder mask, which is less costly than the substrate 200. In the case where second solder mask 360c is located at the underfill between the BGA and the electrical contacts, second solder mask 360c protruding from first solder mask 360a may reduce the amount of material used for the underfill and make it easier to achieve a complete fill.

Fig. 4A is a top view of a substrate according to yet another embodiment of the present invention; fig. 4B is a cross-sectional view of the substrate shown in fig. 4A along line X-X. Referring to fig. 4A and 4B, substrate 400 according to yet another embodiment of the present invention includes features of core layer 420, signal lines 444A, 444B and plating process line 446 of first conductive pattern 440, first soldermask 460a and optionally backside second conductive pattern and backside soldermask 460B that are substantially similar to corresponding features in

substrates

200, 300 and may be formed from the same processes and materials and therefore will not be described again. Substrate 400 differs from

substrates

200, 300 in that second solder mask layer 460c entirely covers the upper surface of first solder mask layer 460a, with only an opening at electrical contact opening 464a of first solder mask layer 460a to expose

electrical contact portions

442a, 442 b. The surface of the solder resist mask of the substrate 400 is more flat than the substrate 300, facilitating the subsequent process. In some embodiments, the thickness of second solder mask 460c of substrate 400 may be adjusted as desired, e.g., made thinner, to balance the stress on the two opposing surfaces of substrate 400, along with first solder mask 460a and optional backside solder mask 460b, to reduce or avoid warpage.

In the

substrates

200, 300, 400 according to the present invention, the

first solder mask

260a, 360a, the

second solder mask

260c, 360c and the optional

backside solder mask

260b, 360b may all be formed by a liquid photo-imageable solder mask process or a dry film photo-imageable solder mask process or the like. By way of example, the material of the dry film photoimageable solder mask may be selected from materials such as, but not limited to, polyimides, acrylates, polyurethanes, etc., which are solid films under the conditions of application, while the material of the liquid photoimageable solder mask may be selected from materials such as, but not limited to, acrylics, epoxies, urethanes, etc., which are liquid under the conditions of application and curable under certain conditions (e.g., photocured, such as UV curing). In one embodiment, the first solder mask and the second solder mask are made using the same techniques and materials, e.g., both are liquid photo-imageable solder masks, or both are dry film photo-imageable solder masks. In this case, since the materials of the first and second solder masks are the same, there may or may not be a material interface therebetween, depending on the specific processes for forming the first and second solder masks. It will be appreciated that when no material interface exists between the first and second solder masks, the stress is distributed relatively evenly across the substrate surface. In contrast, when there is a material interface between the first and second solder masks, the stress will be distributed differently at the material interface. In other embodiments, the first solder mask, the second solder mask are made using different materials and/or techniques, for example, one is a liquid photoimageable solder mask and the other is a dry film photoimageable solder mask to provide greater process selection flexibility. Without being bound by any theory, by adjusting the materials, thicknesses, positions and application processes of the first solder mask, the second solder mask and the optional backside solder mask, the stress distribution and balance of the substrate as a whole can be influenced, thereby achieving the effects of improving warpage, strength and the like.

In the embodiment shown in fig. 2A to 4B, the

conductive pattern openings

248a, 348a, and 448a of the first

conductive patterns

240, 340, 440 are located at portions of the plating process lines connected to the

signal lines

244a, 344a, and 444a, respectively, but the substrate according to the present invention is not limited thereto. Alternatively, one or more conductive pattern openings and solder mask openings may be formed at other or additional locations of the plating process lines 246, 346, 446, with the second solder mask also filling these alternative or additional conductive pattern openings and solder mask openings. This allows the other signal lines to be electrically disconnected from the plating process line or additional signal lines, further reducing the antenna effect caused by the electrically connected large area conductive structure, and avoiding structural integrity problems caused by the conductive pattern openings and solder mask openings.

The present invention also relates to a memory device comprising any of the

substrates

200, 300, or 400 according to the present invention, and having the corresponding features and advantages that the above-described substrates have.

The manufacturing flow of the

substrate

200, 300, 400 according to the present invention will be described below with reference to the flow chart of fig. 5 and the schematic diagrams 6A-6I. The materials and methods used to form the various features of the structures and the final products during the manufacturing process are substantially the same as described above with respect to the corresponding structures and, therefore, will not be repeated here.

Fig. 6A is a cross-sectional view illustrating structure 600 in-process after step 510 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. At step 510, a core layer 620 of dielectric material is provided, the core layer 620 comprising opposing first and

second surfaces

622, 624. Then, a first conductive pattern 640 is formed on the first surface 622 of the core layer 620. The first conductive pattern 640 includes a signal line 644a and other signal lines (not shown), and a plating process line 646. The signal line 644a is formed at one end thereof with an electrical contact portion 642a, and the other signal lines are each formed at one end thereof with other electrical contact portions (not shown). Optionally, a backside second conductive pattern (not shown) is formed on the second surface 624 of the core layer 620. The first conductive pattern 640 may be formed of any suitable material using any suitable technique described above.

Fig. 6B is a cross-sectional view illustrating structure 600 in-process after step 520 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. At step 520, a first solder mask 660a is applied over the first surface 622 of the core layer 620 and the first conductive pattern 640, such that the first solder mask 660a covers the first conductive pattern 640 and the first surface 622 of the core layer 620. First solder mask 660a reserves electrical contact opening 664a such that electrical contact 642a and other electrical contacts are exposed through reserved electrical contact opening 664 a. Optionally, a backside solder mask 660b is formed on the second surface 624 of the core layer 620 to cover the second surface 624 of the core layer 620 and an optional backside second conductive pattern (not shown). First solder mask 660a, optional backside solder mask 660b may be formed of any suitable material using any suitable technique described above.

Fig. 6C is a cross-sectional view illustrating structure 600 in-process after step 530 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. At step 530, an external current source required for plating is connected to plating process line 646, plating layer 643a onto electrical contact portion 642a, while plating other plating layers (not shown) onto other electrical contact portions (not shown). As an example, in the case of performing plating with an electrolytic solution of a metal cation compound, the electrolytic solution is applied to the electric contact portion 642a and other electric contact portion locations, and the cathode of an external current source is connected to one end of the plating process line 646, and the anode of the external current source is connected to the electrolytic solution to supply electrons, which are carriers of electric current, to the metal cations in the electrolytic solution via the electric contact portion 642a and other electric contact portions, so that the metal cations are reduced and deposited on the electric contact portion 642a and other electric contact portions, thereby forming a plated layer 643a covering the electric contact portion 642a and other plated layers covering the other electric contact portions.

Fig. 6D is a cross-sectional view illustrating structure 600 in-process after step 540 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. At step 540, a solder mask opening 662a is formed in the first solder mask 660a where the conductive pattern opening 648a is to be formed in the plating process line 646, and an etch-back process is applied to the plating process line 646 through the solder mask opening 662a to form the conductive pattern opening 648 a. In some embodiments, the solder mask opening 662a is first formed in the first solder mask 660a, followed by an etch back process applied through the solder mask opening 662 a. In this case, the solder resist mask opening 662a may be formed at the same time as the application of the first solder resist mask 660a, or may be formed in the first solder resist mask 660a by a process of photolithography, etching, or the like after the application of the first solder resist mask 660 a. In other embodiments, the solder mask opening 662a and the conductive pattern opening 648a may be formed simultaneously through the first solder mask 660a and the plating process line 646 in the same process step. It is understood that the conductive pattern opening 648a may have any suitable shape and size that is at least no smaller than the width of the plating process line 646 at that location so that the plating process line 646 is completely electrically disconnected at the conductive pattern opening 648 a.

Fig. 6E is a cross-sectional view illustrating structure 600 in-process after step 550 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. At step 550, a second solder mask material layer 660 c' is applied to cover the upper surface of the first solder mask 660a and fill the solder mask openings 662a and the conductive pattern openings 648 a. The second solder mask material layer 660 c' may be applied by a dry film process such as vacuum lamination. As an example, in the vacuum lamination process, a material of the second solder mask, which is a dry film, is first applied on a surface of the first solder mask 660a of the in-process structure 600, and then the in-process structure 600 is placed between a pair of carrier films or a pair of carrier rubber layers, and a vacuum is formed and hot-pressed between the pair of carrier films or the pair of carrier rubber layers, so that the material of the second solder mask is bonded to the surface of the first solder mask 660a and the material of the second solder mask is filled into the solder mask openings 662a in the first solder mask 660a and the conductive pattern openings 648a in the first conductive pattern 640, while removing any voids in the material of the second solder mask and any voids between the material of the second solder mask and the first solder mask 660 a. Thereafter, the in-process structure 600 is cooled to obtain the in-process structure 600 covered with the second solder mask material layer 660 c'. In some embodiments, prior to applying second solder mask material layer 660c ', the surfaces of first solder mask 660a, including the exposed sidewalls of the solder mask openings 662a and the conductive pattern openings 648a, are plasma treated to enhance the bonding force of second solder mask material layer 660 c' to these surfaces.

Fig. 6F is a cross-sectional view illustrating structure 600 in-process after optional step 560 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. At optional step 560, second soldermask material layer 660 c' is thinned by a process such as, but not limited to, photolithography, Chemical Mechanical Polishing (CMP), plasma thinning, or the like, to expose at least an upper surface of first soldermask 660 a. As shown in fig. 6F, after the above-described thinning process, the remaining portions of the second solder mask material layer 660 c' include the second solder mask 660c at the conductive pattern opening 648a and the solder mask opening 662a of the first solder mask 660a and the portion 660c ″ covering the electrical contact portion 642a and the other electrical contact portions.

Fig. 6G is a cross-sectional view illustrating structure 600 after step 570 in an embodiment of an exemplary method of forming a substrate in accordance with the present techniques. At step 570, the portion 660c ″ of the thinned second solder mask material layer 660 c' remaining over electrical contact 642a and other electrical contacts is removed by a process such as, but not limited to, photolithography, etching, or the like to expose electrical contact 642a and other electrical contacts. After step 570, the resulting substrate structure 600 as shown in fig. 6G substantially corresponds to the substrate 200 according to the present invention.

It should be understood that step 560 shown in fig. 5 is optional and that after the in-process structure shown in fig. 6E is formed according to step 550, a thinning process of second solder mask material layer 660c 'may not be performed, but portions of second solder mask material layer 660 c' may be directly removed, resulting in substrate 300 and substrate 400 according to embodiments of the present invention. As shown in FIG. 6H, after forming in-process structure 600 as shown in FIG. 6E according to step 550, second soldermask 660c may be formed by directly removing a substantial portion of second soldermask material layer 660c 'by a process such as, but not limited to, photolithography, etching, or the like, leaving only a portion of second soldermask material layer 660 c' around soldermask opening 662a of first soldermask 660a, thereby exposing electrical contact portion 642a and other electrical contact portions. The resulting structure of the substrate 600' as shown in fig. 6H substantially corresponds to the substrate 300 according to the present invention.

Alternatively, as shown in FIG. 6I, after forming the in-process structure as shown in FIG. 6E according to step 550, portions of second solder mask material layer 660 c' at electrical contact openings 664a of first solder mask 660a may be removed directly by a process such as, but not limited to, photolithography, etching, or the like, thereby exposing electrical contact portion 642a and other electrical contact portions, and leaving substantially the entirety of second solder mask 660c overlying first solder mask 660 a. The resulting structure of the substrate 600 "as shown in fig. 6I substantially corresponds to the substrate 400 according to the present invention. In some embodiments, second soldermask 660c of substrate 600 "as shown in FIG. 6I is thin in order to balance stress on two opposing surfaces of the substrate in conjunction with first soldermask 660a and optional backside soldermask 660b to mitigate or avoid warpage.

Fig. 6A-6I illustrate a method of fabrication that is substantially similar to the embodiments of the

substrates

200, 300, 400. It will be appreciated that portions of the substrate may be formed using the methods and materials described above, all of which are within the scope of the method of manufacturing the substrate according to the present description.

Although the foregoing refers to particular implementations, it should be understood that the invention is not so limited. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and are within the scope of the disclosure.

Claims

1. A substrate, comprising:

a core layer formed of a dielectric material and including a first surface and a second surface opposite to the first surface;

a first conductive pattern formed on the first surface of the core layer, the first conductive pattern including at least one signal line and a plating process line, and the at least one signal line each including an electrical contact portion formed at one end thereof, the electrical contact portion having a plating layer, the plating process line being electrically connected to the at least one signal line simultaneously during a plating process of the plating layer of the electrical contact portion, thereby providing a current required for plating, wherein the plating process line further includes a conductive pattern opening at which at least a portion of the at least one signal line is electrically disconnected from the plating process line;

a first solder mask covering the first conductive pattern, the first solder mask including an electrical contact opening exposing the electrical contact portion and a solder mask opening exposing a conductive pattern opening of the plating process line such that the core layer and the first conductive pattern are not covered by the first solder mask at the solder mask opening; and

a second solder mask filling the solder mask opening and the conductive pattern opening.

2. The substrate of claim 1, wherein the second solder mask is filled only in the solder mask opening and the conductive pattern opening, and an upper surface of the second solder mask is flush with an upper surface of the first solder mask.

3. The substrate of claim 1, wherein an upper surface of the second solder mask layer protrudes from an upper surface of the first solder mask layer, and wherein the second solder mask layer covers at least an area of the first solder mask layer around the solder mask opening.

4. The substrate of claim 3, wherein the second solder mask entirely covers an upper surface of the first solder mask.

5. The substrate of claim 1, wherein the material of the first solder mask is one of polyimide, acrylate, polyurethane, epoxy, and urethane, and the material of the second solder mask is one of polyimide, acrylate, polyurethane, epoxy, and urethane.

6. The substrate of claim 5, wherein the second solder mask layer is the same material as the first solder mask layer.

7. The substrate of claim 5, wherein the second solder mask layer is a different material than the first solder mask layer.

8. A substrate according to claim 6 or 7, characterized in that a material interface is present between the first soldermask and the second soldermask.

9. The substrate of claim 6, wherein there is no material interface between the first solder mask and the second solder mask.

10. A memory device comprising the substrate of any one of claims 1-9.