CN214955729U - Display panel and display device - Google Patents

Abstract

The embodiment of the utility model discloses display panel and display device. The display panel comprises a plurality of stages of scanning circuits, and adjacent stages of scanning circuits are connected; the scanning circuit comprises a thin film transistor and a wire connected with the thin film transistor, the wire is positioned in at least two metal layers and comprises a cascade wire, and the initial signal input end of the next scanning circuit is connected with the scanning signal output end of the previous scanning circuit through the cascade wire; the cascade wiring in the first-stage scanning circuit crosses the thin film transistor and/or partial wiring in the scanning circuit of the current stage to connect the adjacent first-stage scanning circuits. When the same type of display panel is utilized to carry out forward scanning driving and reverse scanning driving respectively, the scheme is favorable for reducing the parasitic parameter difference of the cascade wiring of two scanning circuits, thereby reducing the working performance difference of the forward scanning driving and the reverse scanning driving of the same display panel.

Description

Display panel and display device

Technical Field

The embodiment of the utility model provides a relate to and show technical field, especially relate to a display panel and display device.

Background

With the development of display technology, people have higher and higher requirements for the performance of display devices. The display device comprises a display panel, and the scanning directions of the screen bodies required by different users are different aiming at the display panel products with the same size and the same model. At present, for the same type of display panel, the working performance of the forward scanning driving and the reverse scanning driving is different.

SUMMERY OF THE UTILITY MODEL

An embodiment of the utility model provides a display panel and display device to reduce same display panel's forward scanning drive and reverse scanning driven working property difference.

In a first aspect, an embodiment of the present invention provides a display panel, including:

the scanning circuit of the adjacent stage is connected; the scanning circuit comprises a thin film transistor and a wire connected with the thin film transistor, the wire is positioned in at least two metal layers and comprises a cascade wire, and the initial signal input end of the next scanning circuit is connected with the scanning signal output end of the previous scanning circuit through the cascade wire;

the cascade wiring in the scanning circuit of one stage crosses the thin film transistor and/or part of the wiring in the scanning circuit of the current stage, and is connected with the adjacent scanning circuit of one stage.

Optionally, the lengths of the cascaded traces are equal.

Optionally, the cascade trace includes a first trace portion and a second trace portion, an extending direction of the first trace portion is consistent with an extending direction of a scan line in the display panel, and an extending direction of the second trace portion intersects with the extending direction of the first trace portion;

the first wiring part is connected with a scanning signal output end of the scanning circuit, and the second wiring part is connected with an initial signal input end of the scanning circuit; the second routing part strides over the thin film transistor and/or part of the routing in the scanning circuit and is connected with the first routing part; the first routing line part is positioned at the periphery of the area where the thin film transistor and the routing line in the scanning circuit are positioned.

Optionally, the display device further comprises a scanning line and a driving signal line connected with the scanning circuit, wherein the scanning line is connected with at least one thin film transistor in the scanning circuit;

the second routing portion is located in a region between the driving signal line and the thin film transistor connected with the scanning line.

Optionally, each of the second routing portions is located in the same area in the corresponding scan circuit.

Optionally, the driving signal line comprises a potential signal line and a clock signal line, and the extending directions of the potential signal line, the clock signal line and the second routing part are consistent;

the second routing portion is located in the driving signal line closest to the scanning signal output end and in a region between the thin film transistors adjacent to the driving signal line.

Optionally, the display panel includes a substrate and a plurality of metal layers on the substrate; the plurality of metal layers includes a first metal layer, a second metal layer, and a third metal layer;

the scanning circuit further comprises a capacitor, a first polar plate of the capacitor and a grid electrode of the thin film transistor are located on the first metal layer, a second polar plate of the capacitor is located on the second metal layer, and the first routing part, the second routing part, the driving signal line, and the first pole and the second pole of the thin film transistor are all located on the third metal layer.

Optionally, the potential signal lines include a first potential signal line and a second potential signal line, and the clock signal lines include a first clock signal line and a second clock signal line; the scanning circuit comprises an input module, a first output control module, a first output module, a second output module and a voltage division module; the input module comprises a first transistor, the first output control module comprises a second transistor, the first output module comprises a first capacitor and a third transistor, the second output module comprises a second capacitor and a fourth transistor, and the voltage division module comprises a fifth transistor;

a first pole of the first transistor is used as the initial signal input end, and a second pole plate of the second capacitor is used as the scanning signal output end; the grid electrode of the second transistor is connected with the second pole of the first transistor and is connected with the second pole of the fifth transistor through an electrode connecting wire, the first pole of the second transistor is connected with a first clock signal, and the second pole of the second transistor is connected with the grid electrode of the third transistor and the first pole plate of the first capacitor; a first pole of the third transistor is connected with the second pole plate of the first capacitor and is connected with a second potential signal, and a second pole of the third transistor is connected with the second pole plate of the second capacitor and the second pole of the fourth transistor; the grid electrode of the fourth transistor is connected with the first polar plate of the second capacitor and the first pole of the fifth transistor, and the first pole of the fourth transistor is connected with a second clock signal through a second clock signal transfer line; the grid electrode of the fifth transistor is connected to a first potential signal through a first potential signal transfer line;

the vertical projection of the second routing part on the substrate is positioned between the vertical projection of the first potential signal line on the substrate and the vertical projection of the first electrode of the fifth transistor on the substrate, and the vertical projection of the second routing part on the substrate is overlapped with the vertical projection of the first potential signal transfer line, the electrode connecting line, the second clock signal transfer line, the first electrode plate of the first capacitor and the vertical projection of the second electrode plate on the substrate.

Optionally, the scanning circuits are located at two sides of a non-display area of the display panel, and each side of the non-display area includes a plurality of cascade-connected scanning circuits; the transmission directions of scanning signals output by the scanning circuits in all stages of the scanning circuits at two sides of the non-display area are opposite;

the display panel further comprises scanning lines, one end of each scanning line is connected with the scanning signal output end of the scanning circuit positioned on one side of the non-display area through a first switch, the other end of each scanning line is connected with the scanning signal output end of the scanning circuit positioned on the other side of the non-display area through a second switch, the control ends of the first switches are connected with each other, and the control ends of the second switches are connected with each other.

In a second aspect, the present invention further provides a display device, including the display panel according to the first aspect.

The embodiment of the utility model provides a display panel and display device, display panel includes a plurality of cascade connection's scanning circuit, this scanning circuit includes thin film transistor and the line of walking of connecting thin film transistor, this line of walking includes the cascade line of walking, the initial signal input part of the scanning circuit of back level connects the scanning signal output part of preceding level of scanning circuit through the cascade line of walking, so that display panel can support forward scan drive or reverse scan drive, the cascade line of walking in the one level of scanning circuit strides thin film transistor and/or partial line of walking in this level of scanning circuit, connect adjacent one level of scanning circuit, when utilizing the display panel of the same money to carry out forward scan drive and reverse scan drive respectively, this scheme helps reducing the parasitic parameter difference of the cascade line of two kinds of scanning circuit, thereby reduce the working property difference of forward scan drive and reverse scan drive of the same display panel, meanwhile, the scheme does not occupy the space of the frame area of the display panel additionally, and the number of signal ports of the driving chip is not increased, so that the production cost of the display panel is lower.

Drawings

Fig. 1 is a gate driving circuit in the prior art;

FIG. 2 is another prior art gate drive circuit;

fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 4 is a top view of a display panel according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 6 is a top view of another display panel provided in the embodiments of the present invention;

fig. 7 is a schematic structural diagram of a scan circuit according to an embodiment of the present invention;

fig. 8 is a cross-sectional view of a display panel according to an embodiment of the present invention;

fig. 9 is a cross-sectional view of another display panel provided in an embodiment of the present invention;

fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, there is a difference in the operation performance of the forward scan driving and the reverse scan driving for the same type of display panel. Research by the utility model discloses people discovers that the reason that above-mentioned problem appears lies in: for the same type of display panel, the scanning directions of the panels required by different users are different, for example, fig. 1 is a gate driving circuit in the prior art, specifically a gate driving circuit in a display panel supporting forward scanning driving, fig. 2 is another gate driving circuit in the prior art, specifically a gate driving circuit in a display panel supporting reverse scanning driving, and the gate driving circuits shown in fig. 1 and fig. 2 are applicable to the same type of display panel to meet the requirements of different users and realize the driving of the same display panel in different scanning directions. As shown IN fig. 1 and fig. 2, the two gate driving circuits each include a plurality of cascade-connected scanning circuits 11, referring to fig. 1, an input end I of a first-stage scanning circuit 11 is connected to an input signal IN, an output end O of the first-stage scanning circuit 11 is connected to an input end I of a next-stage scanning circuit 11 through a trace 12, a scanning signal output by the previous-stage scanning circuit 11 can be used as an input signal of the next-stage scanning circuit 11, and the scanning signal is sequentially shifted and transmitted step by step from the first-stage scanning circuit 11 to the last-stage scanning circuit 11, so as to realize forward scanning driving of the display panel. Referring to fig. 2, an input end I of the last scanning circuit 11 is connected to an input signal IN, an output end O of the last scanning circuit 11 is connected to the input end I of the last scanning circuit 11 through a trace 13, a scanning signal output by the next scanning circuit 11 can be used as an input signal of the previous scanning circuit 11, and the scanning signal is sequentially shifted and transmitted step by step from the last scanning circuit 11 to the first scanning circuit 11, so as to realize reverse scanning driving of the display panel. In the gate drive circuit of forward scanning drive and reverse scanning drive, the lengths of the wiring 12 and the wiring 13 connecting the adjacent two stages of scanning circuits are different, the setting areas are also different, the lengths of the wirings influence the resistance of the wirings, and the setting areas of the wirings in the display panel influence the parasitic parameters of the wirings.

Based on the above problem, the embodiment of the utility model provides a display panel. Fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention; fig. 4 is a top view of a display panel according to an embodiment of the present invention, which may be a top view of an area a1 in the display panel shown in fig. 3; fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention; fig. 6 is a top view of another display panel according to an embodiment of the present invention, which may be a top view of an area a2 in the display panel shown in fig. 5; fig. 7 is a schematic structural diagram of a scan circuit according to an embodiment of the present invention.

Referring to fig. 3 to 7, a display panel 100 according to an embodiment of the present invention includes: the multistage scanning circuit 10, the adjacent stage scanning circuit 10 links; the scanning circuit 10 includes a thin film transistor and a trace connected to the thin film transistor, the trace is located in at least two metal layers, the trace includes a cascade trace L, and the start signal input terminal I1 of the first-stage scanning circuit 10 is connected to the scanning signal output terminal O1 of the previous-stage scanning circuit 10 through the cascade trace L; the cascade trace L in the next stage of scanning circuit 10 crosses the thin film transistor and/or a part of the trace in the present stage of scanning circuit 10, and connects the adjacent one stage of scanning circuit 10.

Specifically, the scan circuits 10 can shift and output the input signal of the start signal input terminal I1 through the scan signal output terminal O1, the scan signal output terminal O1 of each scan circuit 10 is connected to the corresponding scan line 20, and the scan signal output by the scan signal output terminal O1 can be transmitted to the gate of the switching transistor in the pixel circuit through the scan line 20, so as to drive the switching transistor to operate. The scanning signal may be a scanning signal Scan for driving a data writing transistor for writing a data voltage Vdata into the storage capacitor in the pixel circuit, an initializing transistor for initializing a gate of the driving transistor and/or an anode of the light emitting device, or a light emission control signal EM for driving the light emission control transistor.

The adjacent scanning circuits 10 are connected, the start signal input terminal I1 of the next scanning circuit 10 is connected to the scanning signal output terminal O1 of the previous scanning circuit 10 through the cascade trace L, so that the output signal of the previous scanning circuit 10 can be used as the input signal of the next scanning circuit 10, and the output signal of the previous scanning circuit 10 is shifted and output through the next scanning circuit 10, so that the scanning signal can be shifted and transmitted step by step in the scanning circuit 10 and transmitted line by line on the scanning line 20, thereby driving the pixel circuits in the display panel to work line by line. The "front" and "rear" In the previous scanning circuit 10 and the subsequent scanning circuit 10 refer to the front and rear of the timing sequence of the signals accessed by the scanning circuit 10, for example, the start signal input terminal I1 of the first scanning circuit 10 In fig. 3 is accessed with the start signal In, the output signal of the scanning signal output terminal O1 of the first scanning circuit 10 can be used as the input signal of the second scanning circuit 10, the first scanning circuit 10 is an opposite previous scanning circuit, the second scanning circuit 10 is an opposite subsequent scanning circuit, the scanning signals are sequentially shifted and transmitted step by step from the first scanning circuit 10 to the last scanning circuit 10, and the forward scanning driving can be realized; in fig. 5, a start signal input terminal I1 of the last stage scanning circuit 10 receives a start signal In, and an output signal of a scanning signal output terminal O1 of the last stage scanning circuit 10 can be used as an input signal of the second to last stage scanning circuit 10, where the last stage scanning circuit 10 is an opposite previous stage scanning circuit, the second to last stage scanning circuit 10 is an opposite next stage scanning circuit, and the scanning signals are sequentially shifted and transmitted from the last stage scanning circuit 10 to the first stage scanning circuit 10 step by step, so that reverse scanning driving can be realized.

The scan circuit 10 includes a thin film transistor and a trace connecting the thin film transistor, and exemplarily, taking the scan circuit shown in fig. 7 as an example, the thin film transistor in the scan circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The trace connecting the thin film transistor may include a metal connection line between different transistors, or a trace inputting a signal to an electrode of the transistor, and the trace is located in at least two metal layers, for example, the trace may be located in a metal layer where a gate of the thin film transistor is located, or may be located in a metal layer where a source/drain of the thin film transistor is located.

When the display panel includes n-level scan circuits 10, for example, in conjunction with fig. 3 and 4, the cascade trace L connected to the start signal input terminal I1 of the I-level scan circuit 10 crosses the thin film transistor and/or a part of the trace in the I-level scan circuit 10, and connects the adjacent I-1-level scan circuit 10, where I is 2 ≦ I ≦ n, in conjunction with fig. 5 and 6, the cascade trace L connected to the scan signal output terminal O1 of the m-level scan circuit 10 crosses the thin film transistor and/or a part of the trace in the m-level scan circuit 10, and connects the adjacent m-1-level scan circuit 10, where m is 2 ≦ m ≦ n. The cascade trace L crosses the thin film transistor and/or the partial trace, which means that the cascade trace L spatially overlaps with the portion it crosses (e.g., overlaps in a direction perpendicular to the display panel), but there is no electrical connection. Fig. 4 and fig. 6 both show the case that the cascade trace L crosses the trace connecting the thin film transistors, and in practical application, the cascade trace L may also cross the thin film transistors, for example, the cascade trace L may cross the active layer or the gate of the thin film transistor, or the cascade trace L may also cross both the thin film transistor and the trace. Alternatively, the cascade trace L may also cross the capacitive plates in the scan circuit.

The display panel shown in fig. 3 and 4 can support forward scan driving, the display panel shown in fig. 5 and 6 can support reverse scan driving, when the display panels shown in fig. 3 to 6 are the same type of display panel with the same size, the same number of wires in the scanning circuit 10 are spanned by the cascade wires L in both schemes, and parasitic parameters generated on the cascade wires L in both schemes are approximately the same because parasitic capacitances exist between the cascade wires L and the spanned wires. When the display panels shown in fig. 3 and 4 and the display panels shown in fig. 5 and 6 are used for driving the same display panel in different scanning directions, the scheme not only enables the same display panel to be compatible with two scanning driving modes, but also helps to reduce the parasitic parameter difference of the cascade wiring L of two scanning circuits, thereby reducing the working performance difference of the forward scanning driving and the reverse scanning driving, meanwhile, the scheme does not occupy the space of the frame area of the display panel additionally, does not increase the number of signal ports of the driving chips, and enables the production cost of the display panel to be lower.

The display panel provided by the embodiment of the utility model comprises a plurality of cascade-connected scanning circuits, the scanning circuit comprises a thin film transistor and a wiring connected with the thin film transistor, the wiring comprises a cascade wiring, the initial signal input end of the next stage of scanning circuit is connected with the scanning signal output end of the previous stage of scanning circuit through the cascade wiring, so that the display panel can support forward scanning drive or reverse scanning drive, the cascade wiring in the first stage of scanning circuit strides over the thin film transistor and/or partial wiring in the present stage of scanning circuit to connect the adjacent first stage of scanning circuit, when the same type of display panel is used for respectively performing forward scanning drive and reverse scanning drive, the scheme is helpful for reducing the parasitic parameter difference of the cascade wiring of the two types of scanning circuits, thereby reducing the working performance difference of the forward scanning drive and the reverse scanning drive of the same display panel, meanwhile, the scheme does not occupy the space of the frame area of the display panel additionally, and the number of signal ports of the driving chip is not increased, so that the production cost of the display panel is lower.

Referring to fig. 3 to fig. 6, on the basis of the above scheme, optionally, the lengths of the cascaded traces L are equal. Since the length of the cascade trace L affects the resistance of the cascade trace L, when the display panels shown in fig. 3 and 4 and the display panels shown in fig. 5 and 6 are used to respectively drive the same display panel in different scanning directions, the lengths of the cascade trace L in the two scanning circuits are set to be equal, which is also beneficial to reducing the difference in resistance of the cascade trace L in the two scanning circuits, thereby further reducing the difference in working performance of the forward scanning driving and the reverse scanning driving.

Referring to fig. 3 to 6, optionally, the cascade trace L includes a first trace portion L1 and a second trace portion L2, an extending direction of the first trace portion L1 is consistent with an extending direction of the scan line 20 in the display panel 100, and an extending direction of the second trace portion L2 intersects with an extending direction of the first trace portion L1; the first wire portion L1 is connected to the scan signal output terminal O1 of the scan circuit 10, and the second wire portion L2 is connected to the start signal input terminal I1 of the scan circuit 10; the second wire trace part L2 crosses the thin film transistor and/or partial wire trace in the scanning circuit 10, and is connected with the first wire trace part L1; the first wire trace portion L1 is located at the periphery of the area where the thin film transistor and the wire trace are located in the scanning circuit 10.

Specifically, the first routing portion L1 and the scan line 20 both extend in the first direction X, and the second routing portion L2 extends in the second direction Y, alternatively, the first direction X and the second direction Y may be perpendicular. A first end of the first wire portion L1 is connected to the scan signal output terminal O1 of the one-stage scan circuit 10, a second end is connected to a first end of the second wire portion L2, and a second end of the second wire portion L2 is connected to the start signal input terminal I1 of the other scan circuit 10. Fig. 4 and 6 each show a case where the second routing portions L2 straddle the wirings connecting the thin film transistors, and the number of the wirings straddled by the second routing portions L2 in both schemes is equal, when the display panel shown in fig. 3 and 4 and the display panel shown in fig. 5 and 6 are used to perform driving in different scanning directions of the same display panel, respectively, this scheme helps to reduce the difference in parasitic parameters of the cascade wirings L of both scanning circuits by reducing the difference in parasitic parameters of the second routing portions L2 of both scanning circuits, and helps to avoid parasitic capacitance between the first routing portions L1 and the thin film transistors and the wirings in the scanning circuit 10 by disposing the first routing portions L1 at the periphery of the regions where the thin film transistors and the wirings in the scanning circuit 10 are located, therefore, the parasitic parameter difference of the cascade wiring L of the two scanning circuits can be further reduced, and the working performance difference of the forward scanning drive and the reverse scanning drive of the same display panel is reduced.

Referring to fig. 3 to fig. 7, on the basis of the above scheme, optionally, the display panel 100 further includes a scan line 20 and a driving signal line connected to the scan circuit 10, where the scan line 20 is connected to at least one thin film transistor in the scan circuit 10; the second wire portion L2 is located in a region between the driving signal line and the thin film transistor connected to the scan line 20.

Specifically, the scan line 20 is used to transmit a scan signal to the transistors in the pixel circuit, the scan line 20 is connected to the thin film transistor connected to the scan signal output terminal O1 in the scan circuit 10, and for example, the scan line 20 may be connected to the third transistor T3 and the fourth transistor T4. The driving signal lines connected to the scan circuit 10 may be traces for transmitting a potential signal or a clock signal to the scan circuit 10, such as traces for transmitting a first potential signal VGL to the scan circuit 10, traces for transmitting a second potential signal VGH to the scan circuit 10, traces for transmitting a first clock signal SCK1 to the scan circuit 10, and traces for transmitting a second clock signal SCK2 to the scan circuit 10. Since the thin film transistors and/or the partial traces connected with the thin film transistors exist in the region between the driving signal line of the scanning circuit 10 and the thin film transistors connected with the scanning line 20, the second trace portion L2 can cross the thin film transistors and/or the partial traces in the scanning circuit 10 by arranging the second trace portion L2 in the region between the driving signal line and the thin film transistors connected with the scanning line 20, and when the number of the thin film transistors and/or the traces crossed by the second trace portion L2 in the two schemes of fig. 3 to 6 is the same, the scheme is helpful for reducing the difference of parasitic parameters of the cascade traces L of the two scanning circuits, thereby reducing the difference of the working performance of the forward scanning driving and the reverse scanning driving of the same display panel.

On the basis of the above-described scheme, each of the second wire trace portions L2 is optionally located in the same region in the corresponding scanning circuit 10. Fig. 4 and 6 show that each of the second wire traces L2 is located in the same area of the corresponding scanning circuit 10, which enables the tfts and/or traces spanned by the second wire traces L2 to be the same, for example, each of the second wire traces L2 spans three identical traces in the scanning circuit 10 and two plates of the same capacitor. The advantage of this arrangement is that the second wire trace portions L2 of the forward scan driving scheme and the reverse scan driving scheme of the same display panel can both span the same region of the corresponding scan circuit 10, so that the parasitic parameters generated by the overlapping of the thin film transistors and/or the wires in each second wire trace portion L2 and the scan circuit 10 are close to each other, thereby reducing the parasitic parameter difference of the cascade wires L of the two scan circuits, and reducing the working performance difference of the forward scan driving scheme and the reverse scan driving scheme of the same display panel.

Referring to fig. 3 to 7, alternatively, the driving signal lines include a potential signal line and a clock signal line, and the extending directions of the potential signal line, the clock signal line, and the second routing portion L2 coincide; the second wire portion L2 is located in a region between the driving signal line closest to the scanning signal output terminal O1 and the thin film transistor adjacent to the driving signal line.

Specifically, the potential signal lines include a first potential signal line 30a for transmitting the first potential signal VGL and a second potential signal line 30b for transmitting the second potential signal VGH, and the clock signal lines include a first clock signal line 30c for transmitting the first clock signal SCK1 and a second clock signal line 30d for transmitting the second clock signal SCK 2. The first potential signal line 30a, the second potential signal line 30b, the first clock signal line 30c, the second clock signal line 30d, and the second wire portion L2 all extend in the second direction Y, which is advantageous in that the second wire portion L2 can be prevented from overlapping with each driving signal line to affect the signals transmitted by each driving signal line. Illustratively, the driving signal line closest to the scan signal output terminal O1 may be the first potential signal line 30a, the tft adjacent to the first potential signal line 30a refers to the tft closest to the first potential signal line 30a and located between the first potential signal line 30a and the tft connected to the scan line 20, since there are no other driving signal lines and tfts in the region between the first potential signal line 30a and the adjacent tft, there is a wiring space, which is beneficial for the wiring of the second wire trace portion L2, on the basis of which the second wire trace portion L2 may be arranged to cross the wire connected to the tft in the region, so that the parasitic parameters generated by overlapping each second wire trace portion L2 with the region are close, which is beneficial to reduce the parasitic parameter difference of the cascaded wire L in the two schemes of forward scan driving and reverse scan driving of the same display panel, and further reduce the difference of the working performance of different scanning driving modes of the same display panel.

Fig. 8 is a cross-sectional view of a display panel according to an embodiment of the present invention, which may be a cross-sectional view obtained by cutting the display panel shown in fig. 6 along a cross-sectional line AA', or a cross-sectional view obtained by cutting the display panel shown in fig. 4 along the same position; fig. 9 is a cross-sectional view of another display panel provided in an embodiment of the present invention, which may be a cross-sectional view obtained by cutting the display panel shown in fig. 6 along a cross-sectional line BB', or a cross-sectional view obtained by cutting the display panel shown in fig. 4 along the same position. With reference to fig. 4 and fig. 6 to fig. 9, on the basis of the above scheme, optionally, the display panel 100 includes a substrate 210 and a plurality of metal layers located on the substrate 210; the plurality of metal layers includes a first metal layer M1, a second metal layer M2, and a third metal layer M3; the scan circuit 10 further includes a capacitor, a first plate of the capacitor and a gate of the thin film transistor are located on the first metal layer M1, a second plate of the capacitor is located on the second metal layer M2, and the first wire trace portion L1, the second wire trace portion L2, the driving signal line, and the first pole and the second pole of the thin film transistor are all located on the third metal layer M3.

The substrate 210 may provide buffering, protection, or support for the display panel. The substrate 210 may be a flexible substrate, and the material of the flexible substrate may be Polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or the like, or may be a mixture of the foregoing materials. The substrate 210 may be a hard substrate formed of glass or the like. The scan circuit 10 may include a first capacitor C1 and a second capacitor C2, and the first plate C11 of the first capacitor C1, the first plate C21 of the second capacitor C2 and the gate of each thin film transistor are located on the first metal layer M1. Alternatively, the first plate of the capacitor may be a gate of a thin film transistor, for example, the first plate C11 of the first capacitor C1 may be a gate of the third transistor T3, and the first plate C21 of the second capacitor C2 may be a gate of the fourth transistor T4. The second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are located on the second metal layer M2, and the first routing portion L1, the second routing portion L2, the first potential signal line 30a, the second potential signal line 30b, the first clock signal line 30C, the second clock signal line 30d, and the first and second poles (i.e., source/drain electrodes) of each thin film transistor are located on the third metal layer M3. Since the scanning circuit 10 is disposed in the non-display region, the third metal layer M3 of the non-display region usually only includes the driving signal lines of the scanning circuit 10 and the source/drain electrodes of the thin film transistors, the third metal layer M3 is not used for forming the active layer and the gate electrodes of the thin film transistors or forming the capacitor plates in the scanning circuit 10, the first routing portion L1 and the second routing portion L2 of the cascade routing L are disposed in the third metal layer M3, the cascade routing L is not in the same layer as the active layer, the gate electrodes, and the capacitor plates of the thin film transistors, and does not need to avoid routing, and the extending directions of the driving signal lines and the second routing portion L2 are the same, which is beneficial to routing of the cascade routing L and has little influence on the routing space of the third metal layer M3.

Referring to fig. 4 and fig. 6 to 9, on the basis of the above scheme, optionally, the potential signal lines include a first potential signal line 30a and a second potential signal line 30b, and the clock signal lines include a first clock signal SCK1 line 30c and a second clock signal line 30 d; the scan circuit 10 includes an input module 110, a first output control module 120, a first output module 130, a second output module 140, and a voltage dividing module 150; the input module 110 includes a first transistor T1, the first output control module 120 includes a second transistor T2, the first output module 130 includes a first capacitor C1 and a third transistor T3, the second output module 140 includes a second capacitor C2 and a fourth transistor T4, and the voltage division module 150 includes a fifth transistor T5;

a first electrode of the first transistor T1 is used as a start signal input terminal I1, and a second electrode C22 of the second capacitor C2 is used as a scan signal output terminal O1; the gate of the second transistor T2 is connected to the second pole of the first transistor T1 and to the second pole of the fifth transistor T5 through the electrode connection line 31, the first pole of the second transistor T2 is connected to the first clock signal SCK1, and the second pole of the second transistor T2 is connected to the gate of the third transistor T3 and the first plate C11 of the first capacitor C1; a first pole of the third transistor T3 is connected to the second plate C12 of the first capacitor C1 and receives the second potential signal VGH, and a second pole of the third transistor T3 is connected to the second plate C22 of the second capacitor C2 and the second pole of the fourth transistor T4; the gate of the fourth transistor T4 is connected to the first electrode C21 of the second capacitor C2 and the first electrode of the fifth transistor T5, and the first electrode of the fourth transistor T4 is connected to the second clock signal SCK2 through the second clock signal transfer line 32; the gate of the fifth transistor T5 is connected to the first potential signal VGL through the first potential signal transfer line 33;

the vertical projection of the second wire trace portion L2 on the substrate 210 is located between the vertical projection of the first potential signal line 30a on the substrate 210 and the vertical projection of the first pole of the fifth transistor T5 on the substrate 210, and the vertical projection of the second wire trace portion L2 on the substrate 210 overlaps with the vertical projection of the first potential signal transfer line 33, the electrode connection line 31, the second clock signal transfer line 32, the first plate C11 of the first capacitor C1 and the second plate C12 on the substrate 210.

The first transistor T1 of the input module 110 is used for inputting the start signal In under the control of the first clock signal SCK 1. The second transistor T2 in the first output control module 120 may control a potential of the gate of the third transistor T3 in the first output module 130 through the first clock signal SCK1 in response to a signal of the second pole of the first transistor T1. The first capacitor C1 of the first output module 130 is used for storing the potential of the gate of the third transistor T3, and the third transistor T3 can transmit the second potential signal VGH to the scan signal output terminal O1 in response to the signal of the gate thereof. The second capacitor C2 of the second output module 140 is used for storing the potential of the gate of the fourth transistor T4, and the fourth transistor T4 can transmit the second clock signal SCK2 to the scan signal output terminal O1 in response to the signal of the gate thereof. The fifth transistor T5 in the voltage dividing module 150 is used for dividing the voltage so as to prevent the extremely low voltage appearing at the gate of the fourth transistor T4 from being transmitted to the first transistor T1 and the second transistor T2.

Fig. 4 and 6 schematically show, in the first metal layer M1, an arrangement region of each thin film transistor in the scanning circuit in the display panel, and in conjunction with fig. 4, 6, and 9, a vertical projection of the second wire trace portion L2 on the substrate 210 is located between a vertical projection of the first potential signal line 30a on the substrate 210 and a vertical projection of the first electrode 240 of the fifth transistor T5 on the substrate 210, that is, a vertical projection of the second wire trace portion L2 on the substrate 210, a vertical projection of the first potential signal line 30a on the substrate 210, and a region between a vertical projection of an active layer corresponding to the fifth transistor T5 in the active layer 230 on the substrate 210. In the third metal layer M3 in this region, no driving signal line, no thin film transistor, and no routing line connected to the thin film transistor are provided, which is beneficial to the arrangement of the second routing portion L2, and no winding circumvention is required.

With reference to fig. 4, 6 and 8, the vertical projection of the second routing portion L2 on the substrate 210 overlaps with the vertical projection of the first potential signal patch cord 33, the electrode connection cord 31, the second clock signal patch cord 32, the first plate C11 of the first capacitor C1 and the second plate C12 on the substrate 210, and for the two schemes of forward scan driving and reverse scan driving of the same display panel, each second routing portion L2 crosses the same trace and capacitor plate in the scan circuit and generates parasitic capacitance with the same trace and capacitor plate, which is helpful to reduce the difference of parasitic parameters of the second routing portion L2 in the two schemes to the maximum extent, thereby reducing the difference of working performance of different scan driving modes of the same display panel.

Referring to fig. 4, 6, 8 and 9, in a manufacturing process of the display panel, for example, an active layer 230, a first metal layer M1, a first insulating layer and a second metal layer M2 are sequentially formed on a substrate 210 to form an active layer and a gate electrode of a thin film transistor and a capacitor plate in a scan circuit, then a second insulating layer, a third metal layer M3 and a third insulating layer are formed on the second metal layer M2 to form a cascade trace L, a driving signal line and a source/drain electrode of the thin film transistor in the scan circuit, and finally a planarization layer, an electrode layer of a light emitting device and a pixel defining layer and the like in the display panel are sequentially formed on the third metal layer M3 (the insulation layer, the planarization layer, the electrode layer of the light emitting device and the pixel defining layer are not shown in the figure). Compared with the prior art, the utility model discloses technical scheme need not to change the process of other retes in the display panel except that third metal level M3, corresponding to two kinds of schemes shown in fig. 4 and fig. 6, only improve the process of third metal level M3 respectively can, only need add a third metal level M3's mask version, the preparation technology is comparatively simple, when reducing the working property difference of same display panel's different scanning drive methods, be favorable to reducing manufacturing cost.

Fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 10, optionally, the scanning circuits 10 are located at two sides of the non-display area NAA of the display panel 100, and each side of the non-display area NAA includes a plurality of scanning circuits 10 connected in cascade; the transmission directions of the scanning signals output by the scanning circuits 10 in the scanning circuits 10 at the respective stages at the two sides of the non-display area NAA are opposite; the display panel 100 further includes scan lines 20, one end of each scan line 20 is connected to the scan signal output terminal O1 of the scan circuit 10 located at one side of the non-display area NAA through a first switch K1, and the other end is connected to the scan signal output terminal O1 of the scan circuit 10 located at the other side of the non-display area NAA through a second switch K2, control terminals of the first switches K1 are connected to each other, and control terminals of the second switches K2 are connected to each other (not shown in the figure are traces connected to the control terminals of the first switches K1 and traces connected to the control terminals of the second switches K2).

Illustratively, when each side of the non-display area NAA includes n stages of scanning circuits 10, it may be configured that a start signal input terminal I1 of a first stage of scanning circuit 10 located at one side of the non-display area NAA is connected to a start signal In, a scanning signal output terminal O1 of a p-th stage of scanning circuit 10 is connected to a start signal input terminal I1 of a p + 1-th stage of scanning circuit 10 through a cascade wiring L, where 1. ltoreq. p.ltoreq.n-1, a start signal input terminal I1 of an n-th stage of scanning circuit 10 located at the other side of the non-display area NAA is connected to a start signal In, a scanning signal output terminal O1 of a q-th stage of scanning circuit 10 is connected to a start signal input terminal I1 of a q-1-th stage of scanning circuit 10 through a cascade wiring L, where 2. ltoreq. q.ltoreq.n, so that scanning signals are sequentially shifted and transmitted step by step In the first to the n-th stage of scanning circuit 10 located at one side of the non-display area NAA, forward scanning driving is realized, scanning signals are sequentially shifted and transmitted step by step from the nth-stage scanning circuit 10 to the first-stage scanning circuit 10 which are positioned on the other side of the non-display area NAA, reverse scanning driving is realized, and the transmission directions of the scanning signals output by the scanning circuits 10 in all stages of scanning circuits 10 on the two sides of the non-display area NAA are opposite.

In fig. 10, which schematically shows the case where the first switch K1 and the second switch K2 are both thin film transistors, the first switch K1 and the second switch K2 can be fabricated in the same process flow as the thin film transistors in the scan circuit and the pixel circuit, which helps to simplify the fabrication process of the display panel. If a signal for controlling the first switch K1 to turn on is simultaneously applied to the control terminal (i.e., gate) of each first switch K1, and a signal for controlling the second switch K2 to turn off is simultaneously applied to the control terminal (i.e., gate) of each second switch K2, the plurality of scanning circuits 10 located at the left side of the non-display area NAA can be controlled to operate, so as to realize the forward scanning driving of the display panel; on the contrary, if the signal for turning off the first switch K1 is applied to the control terminal of each first switch K1 and the signal for turning on the second switch K2 is applied to the control terminal of each second switch K2 at the same time, the plurality of scanning circuits 10 located at the right side of the non-display area NAA can be controlled to operate, so as to realize the reverse scanning driving of the display panel. The advantage of this arrangement is that the display panel 100 can support the working modes of the forward scan driving and the reverse scan driving at the same time, and because each of the cascade traces L crosses over the thin film transistor and/or a part of the traces in the scan circuit 10, the parasitic parameters generated on the cascade traces L in the scan circuit corresponding to the two working modes are approximately the same, which is helpful for reducing the working performance difference between the forward scan driving and the reverse scan driving of the display panel. Since only one side of the scan circuit 10 transmits the scan signal to the scan lines 20 when the display panel 100 operates in the forward scan driving mode or the reverse scan driving mode, the scheme is applicable to a display panel with a small size, so as to prevent the display panel from being affected by an excessive voltage drop of the scan signal on the scan lines 20, for example, the display panel is applicable to an intelligent wearable device (e.g., a smart watch).

The embodiment of the utility model provides a still provide a display device, fig. 11 is the embodiment of the utility model provides a display device's schematic structure diagram. The display device may be a mobile phone, a computer, a tablet computer, a smart wearable device, or other electronic devices with a display function, and fig. 11 schematically illustrates a case where the display device 200 is a mobile phone. The embodiment of the utility model provides a display device, include the utility model discloses the display panel that the above-mentioned arbitrary embodiment provided, therefore have the corresponding structure of display panel and beneficial effect, no longer give unnecessary details here.

It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims (10)

1. A display panel, comprising:

the scanning circuit of the adjacent stage is connected; the scanning circuit comprises a thin film transistor and a wire connected with the thin film transistor, the wire is positioned in at least two metal layers and comprises a cascade wire, and the initial signal input end of the next scanning circuit is connected with the scanning signal output end of the previous scanning circuit through the cascade wire;

the cascade wiring in the scanning circuit of one stage crosses the thin film transistor and/or part of the wiring in the scanning circuit of the current stage, and is connected with the adjacent scanning circuit of one stage.

2. The display panel of claim 1, wherein each of the cascaded traces is equal in length.

3. The display panel according to claim 1, wherein the cascade trace comprises a first trace portion and a second trace portion, an extending direction of the first trace portion is consistent with an extending direction of a scan line in the display panel, and an extending direction of the second trace portion intersects with the extending direction of the first trace portion;

the first wiring part is connected with a scanning signal output end of the scanning circuit, and the second wiring part is connected with an initial signal input end of the scanning circuit; the second routing part strides over the thin film transistor and/or part of the routing in the scanning circuit and is connected with the first routing part; the first routing line part is positioned at the periphery of the area where the thin film transistor and the routing line in the scanning circuit are positioned.

4. The display panel according to claim 3, further comprising a scan line and a driving signal line connected to the scan circuit, the scan line being connected to at least one thin film transistor in the scan circuit;

the second routing portion is located in a region between the driving signal line and the thin film transistor connected with the scanning line.

5. The display panel according to claim 4, wherein each of the second trace portions is located in the same area of the corresponding scan circuit.

6. The display panel according to claim 4, wherein the driving signal lines include potential signal lines and clock signal lines, and extending directions of the potential signal lines, the clock signal lines, and the second routing portions are uniform;

the second routing portion is located in the driving signal line closest to the scanning signal output end and in a region between the thin film transistors adjacent to the driving signal line.

7. The display panel according to claim 6, wherein the display panel comprises a substrate and a plurality of metal layers on the substrate; the plurality of metal layers includes a first metal layer, a second metal layer, and a third metal layer;

the scanning circuit further comprises a capacitor, a first polar plate of the capacitor and a grid electrode of the thin film transistor are located on the first metal layer, a second polar plate of the capacitor is located on the second metal layer, and the first routing part, the second routing part, the driving signal line, and the first pole and the second pole of the thin film transistor are all located on the third metal layer.

8. The display panel according to claim 7, wherein the potential signal line includes a first potential signal line and a second potential signal line, and the clock signal line includes a first clock signal line and a second clock signal line; the scanning circuit comprises an input module, a first output control module, a first output module, a second output module and a voltage division module; the input module comprises a first transistor, the first output control module comprises a second transistor, the first output module comprises a first capacitor and a third transistor, the second output module comprises a second capacitor and a fourth transistor, and the voltage division module comprises a fifth transistor;

a first pole of the first transistor is used as the initial signal input end, and a second pole plate of the second capacitor is used as the scanning signal output end; the grid electrode of the second transistor is connected with the second pole of the first transistor and is connected with the second pole of the fifth transistor through an electrode connecting wire, the first pole of the second transistor is connected with a first clock signal, and the second pole of the second transistor is connected with the grid electrode of the third transistor and the first pole plate of the first capacitor; a first pole of the third transistor is connected with the second pole plate of the first capacitor and is connected with a second potential signal, and a second pole of the third transistor is connected with the second pole plate of the second capacitor and the second pole of the fourth transistor; the grid electrode of the fourth transistor is connected with the first polar plate of the second capacitor and the first pole of the fifth transistor, and the first pole of the fourth transistor is connected with a second clock signal through a second clock signal transfer line; the grid electrode of the fifth transistor is connected to a first potential signal through a first potential signal transfer line;

the vertical projection of the second routing part on the substrate is positioned between the vertical projection of the first potential signal line on the substrate and the vertical projection of the first electrode of the fifth transistor on the substrate, and the vertical projection of the second routing part on the substrate is overlapped with the vertical projection of the first potential signal transfer line, the electrode connecting line, the second clock signal transfer line, the first electrode plate of the first capacitor and the vertical projection of the second electrode plate on the substrate.

9. The display panel according to claim 1, wherein the scanning circuits are located on both sides of a non-display area of the display panel, each side of the non-display area including a plurality of the scanning circuits connected in cascade; the transmission directions of scanning signals output by the scanning circuits in all stages of the scanning circuits at two sides of the non-display area are opposite;

the display panel further comprises scanning lines, one end of each scanning line is connected with the scanning signal output end of the scanning circuit positioned on one side of the non-display area through a first switch, the other end of each scanning line is connected with the scanning signal output end of the scanning circuit positioned on the other side of the non-display area through a second switch, the control ends of the first switches are connected with each other, and the control ends of the second switches are connected with each other.

10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.

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