CN214900922U

CN214900922U - Lighting protocol conversion device

Info

Publication number: CN214900922U
Application number: CN202120904454.7U
Authority: CN
Inventors: 陈志清; 马国诗; 谢竞舟; 潘雯; 何奕; 黄逢俊; 钟展华
Original assignee: Guangzhou Jiaotou Ruijun Real Estate Co ltd
Current assignee: Guangzhou Jiaotou Ruijun Real Estate Co ltd
Priority date: 2021-04-28
Filing date: 2021-04-28
Publication date: 2021-11-26
Anticipated expiration: 2031-04-28

Abstract

The utility model relates to an illumination protocol conversion equipment. The method comprises the following steps: the RS485 interface unit is connected with the lighting control equipment and receives an RS485 protocol instruction sent by the lighting control equipment; the WIFI interface unit is connected with the mobile terminal and receives a WIFI protocol instruction sent by the mobile terminal; the Ethernet interface unit is connected with the remote server and receives an Ethernet protocol instruction sent by the remote server; the USB interface unit is connected with the local computer and receives a USB protocol instruction sent by the local computer; the central processing unit is respectively connected with the RS485 unit, the WIFI interface unit, the Ethernet interface unit and the USB interface unit, and converts the RS485 protocol instruction, the WIFI protocol instruction, the Ethernet protocol instruction and the USB protocol instruction into a DALI protocol instruction; the DALI interface unit is connected with the central processing unit and the lighting system and sends DALI protocol instructions to the lighting system. And the control and lighting compatibility is realized.

Description

Lighting protocol conversion device

Technical Field

The utility model relates to a network connection technical field especially relates to a lighting protocol conversion equipment.

Background

DALI (Digital Addressable Lighting Interface) protocol is the most advanced open asynchronous serial Digital communication protocol for Lighting system control in the world at present as the international open standard control technology of smart home Lighting systems.

The DALI technology is mainly characterized in that a single lamp has an independent address, and single or multiple lamps on the same strong current loop or different loops can be independently addressed, so that the accurate control of a single lamp or a lamp group is realized.

However, in the current lighting control market, many products adopt RS485 communication interfaces of a closed protocol, and cannot be compatible with a DALI lighting system, which hinders application and popularization of the smart home lighting system.

SUMMERY OF THE UTILITY MODEL

Based on this, there is a need for a lighting protocol conversion apparatus that enables the control device to be compatible with the lighting system.

A lighting protocol conversion apparatus, the apparatus comprising:

the RS485 interface unit is used for being connected with the lighting control equipment and receiving an RS485 protocol command sent by the lighting control equipment;

the WIFI interface unit is used for being connected with a mobile terminal and receiving a WIFI protocol instruction sent by the mobile terminal;

the Ethernet interface unit is used for connecting with a remote server and receiving an Ethernet protocol instruction sent by the remote server;

the USB interface unit is used for connecting with a local computer and receiving a USB protocol instruction sent by the local computer;

the central processing unit is respectively connected with the RS485 unit, the WIFI interface unit, the Ethernet interface unit and the USB interface unit and is used for converting the RS485 protocol instruction, the WIFI protocol instruction, the Ethernet protocol instruction and the USB protocol instruction into a DALI protocol instruction;

and the DALI interface unit is connected with the central processing unit and is used for being connected with a lighting system and sending the DALI protocol instruction to the lighting system.

In one embodiment, the central processor comprises:

the first protocol converter is respectively connected with the RS485 interface unit and the DALI interface unit and is used for converting the RS485 protocol instruction into a DALI protocol instruction;

the second protocol converter is respectively connected with the WIFI interface unit and the DALI interface unit and is used for converting the WIFI protocol instruction into a DALI protocol instruction;

the third protocol converter is respectively connected with the Ethernet interface unit and the DALI interface unit and is used for converting the Ethernet protocol instruction into a DALI protocol instruction;

and the fourth protocol converter is respectively connected with the USB interface unit and the DALI interface unit and is used for converting the USB protocol instruction into a DALI protocol instruction.

In one embodiment, the central processor further comprises:

a data selector having four data input terminals, one data output terminal and four address input terminals; the four data input ends are respectively connected with the first protocol converter, the second protocol converter, the third protocol converter and the fourth protocol converter, and the data output end is connected with the DALI interface unit, so that the data selector is connected in series among the first protocol converter, the second protocol converter, the third protocol converter, the fourth protocol converter and the DALI interface unit; the four address input ends are respectively connected with the first protocol converter, the second protocol converter, the third protocol converter and the fourth protocol converter.

In one embodiment, the DALI interface unit comprises a read data optocoupler U1, a write data optocoupler U2, a read data resistor R1, a write data resistor R2, a base resistor R3, an emitter resistor R4, a triode Q, a voltage stabilizing circuit, a bridge circuit and a DALI connection terminal P1; two wiring terminals of the DALI wiring terminal P1 are respectively connected with two alternating current input ends of the bridge circuit, an anode output end of the bridge circuit is connected with an anode input end of the read data optocoupler U1 through the voltage stabilizing circuit, and a cathode input end of the read data optocoupler U1 is connected with a cathode output end of the bridge circuit; the positive output end of the read data optical coupler U1 is connected with a DALI reading end of the central processing unit and is connected with a power supply through the read data resistor R1, and the negative output end of the read data optical coupler U1 is grounded; the positive input end of the write data optocoupler U2 is connected with a DALI write-in end of the central processing unit through the write data resistor R2, and the negative input end of the write data optocoupler U2 is grounded; the positive output end of the write data optocoupler U2 and the collector of the triode Q are connected with the positive output end of the bridge circuit, and the negative end of the write data optocoupler is connected with the base of the triode Q through the base resistor R3 and connected with the emitter of the triode Q through the emitter resistor R4.

In one embodiment, the RS485 interface unit includes an SN75176B chip U3, a first output terminal resistor R6, a second output terminal resistor R7, a power terminal resistor R8, a ground terminal resistor R9, and an RS485 connection terminal P2; pin 1 of the SN75176B chip U3 is connected to an RS485 read end of the cpu, pin 4 of the SN75176B chip U3 is connected to an RS485 write end of the cpu, pin 5 of the SN75176B chip U3 is grounded, pin 6 of the SN75176B chip U3 is connected to a second terminal of the RS485 connection terminal P2 through a first output resistor R6, pin 7 of the SN75176B chip U3 is connected to a first terminal of the RS485 connection terminal P2 through a second output resistor R7, and pin of the SN75176B chip U3 is connected to a power supply; the second wiring end of the RS485 wiring terminal P2 is connected with a power supply through a power supply end resistor R8, the first wiring end of the RS485 wiring terminal P2 is grounded through a grounding end resistor R9, and the third grounding end of the RS485 wiring terminal P2 is grounded.

In one embodiment, the WIFI interface unit includes an ESP8266 chip U4, pin 1 of the ESP8266 chip U4 is connected to a power supply, pin 2 of the ESP8266 chip U4 is connected to a WIFI write terminal of the central processing unit, pin 7 of the ESP8266 chip U4 is connected to a WIFI read terminal of the central processing unit, and pin 8 of the ESP8266 chip U4 is connected to a ground.

In one embodiment, the ethernet interface unit includes a LAN8720A chip U5, an RJ45 chip U6, an oscillation circuit, a clock circuit, first to tenth resistors R11 to R20, first to tenth capacitors C1 to C10; a pin 17 and a pin 18 of the LAN8720 chip U are respectively connected to two ethernet write terminals of the central processor, a pin 7 and a pin 8 of the LAN8720 chip U are respectively connected to two ethernet read terminals of the central processor, a pin 15 of the LAN8720 chip U is connected to a second resistor R through a first resistor R, a pin 24 of the LAN8720 chip U is connected to a second resistor R, a pin 3 of the LAN8720 chip U is connected to a seventh resistor R, a pin 2 of the LAN8720 chip U is connected to an eighth resistor R, a pin 19 of the LAN8720 chip U is connected to a first capacitor C, a pin 1 of the LAN8720 chip U is connected to a second capacitor C, a pin 9 of the LAN8720 chip U is connected to a third capacitor C, a pin 6 of the LAN8720 chip U is connected to a fourth capacitor C and a fifth capacitor C in parallel, a pin 25 of the LAN8720 chip U is connected to ground, a pin 21 of the LAN8720 chip U is connected to the third resistor R, a pin 8720 of the LAN8720 chip U is connected to the fourth resistor R through a fourth resistor R, A pin 23 of a chip U5 of the LAN8720A is connected with a first connection end of the oscillating circuit through a fifth resistor R15, a pin 22 of a chip U5 of the LAN8720A is connected with a first connection end of the oscillating circuit through a sixth resistor R16, a pin 19 of a chip U5 of the LAN8720A and a pin 1 of a chip U5 of the LAN8720A, a pin 9 of a chip U5 of the LAN8720A is connected with a second connection end of the oscillating circuit, a pin 5 of a chip U5 of the LAN8720A is connected with one connection end of the clock circuit, and the other connection end of the clock circuit is connected in a pin 4 of a chip U5 of the LAN 8720A; pin 4 and pin 5 of the RJ45 chip U6 are connected to the first connection end of the oscillation circuit, pin 4 and pin 5 of the RJ45 chip U6 are connected to the first connection end of the oscillation circuit through a sixth capacitor C6, pin 1 of the RJ45 chip U6 is connected to the seventh capacitor C7, pin 2 of the RJ45 chip U6 is connected to the ground through an eighth capacitor C8, pin 3 of the RJ45 chip U6 is connected to the ninth capacitor C9, pin 6 of the RJ45 chip U6 is connected to the ground through a tenth capacitor C10, pin 7 of the RJ45 chip U6 is floating, pin 10 of the RJ45 chip U6 is connected to pin 8, pin 13 and pin 14 of the RJ45 chip U6 through a ninth resistor R19, and pin 11 of the RJ45 chip U6 is connected to the tenth resistor R20.

In one embodiment, the USB interface unit includes a USB terminal P3, a positive resistor R23 and a negative resistor R24, the first terminal of the USB terminal P3 is connected to the power supply, the second terminal of the USB terminal P3 is connected to a USB data terminal of the cpu through the positive resistor R23, the third terminal of the USB terminal P3 is connected to another USB data terminal of the cpu through the negative resistor R24, the fourth terminal of the USB terminal P3 is floating, and the fifth terminal of the USB terminal P3 is grounded.

In one embodiment, the apparatus further comprises:

and the indicating lamp circuit is connected with the central processing unit and is used for indicating the working state of the central processing unit.

In one embodiment, the apparatus further comprises:

and the power supply is connected with the central processing unit.

The lighting protocol conversion device comprises an RS485 interface unit, a WIFI interface unit, an Ethernet interface unit, a USB interface unit, a central processing unit and a DALI interface unit. The RS485 interface unit is used for being connected with the lighting control equipment and receiving an RS485 protocol command sent by the lighting control equipment, so that the lighting control equipment can send the RS485 protocol command to the lighting protocol conversion device through the RS485 interface. The WIFI interface unit is used for being connected with the mobile terminal and receiving a WIFI protocol instruction sent by the mobile terminal, so that the mobile terminal can send the WIFI protocol instruction to the lighting protocol conversion device through the WIFI interface unit. The Ethernet interface unit is used for connecting with the remote server and receiving the Ethernet protocol command sent by the remote server, so that the remote server can send the Ethernet protocol command to the lighting protocol conversion device through the Ethernet interface unit. The USB interface unit is used for being connected with the local computer and receiving the USB protocol command sent by the local computer, so that the local computer can send the USB protocol command to the lighting protocol conversion device through the USB interface unit. The central processing unit is respectively connected with the RS485 unit, the WIFI interface unit, the Ethernet interface unit and the USB interface unit and is used for converting the RS485 protocol instruction, the WIFI protocol instruction, the Ethernet protocol instruction and the USB protocol instruction into a DALI protocol instruction, so that various protocol instructions received by the lighting protocol conversion device can be uniformly converted into the DALI protocol instruction through the central processing unit. The DALI interface unit is respectively connected with the central processing unit and the lighting system and used for sending the DALI protocol instruction converted by the central processing unit to the lighting system, so that the control of the lighting system can be realized. The lighting protocol conversion device is compatible with a DALI lighting system by adopting lighting control equipment of various protocols, and can effectively promote application and popularization of the intelligent home lighting system.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an illumination protocol conversion apparatus according to an embodiment;

FIG. 2 is a schematic diagram of a structure of the DALI interface unit of FIG. 1;

FIG. 3 is a schematic diagram of an RS485 interface unit shown in FIG. 1;

fig. 4 is a schematic structural diagram of the WIFI interface unit in fig. 1;

FIG. 5 is a schematic diagram of an Ethernet interface unit of FIG. 1;

FIG. 6 is a schematic diagram of a structure of the USB interface unit of FIG. 1;

FIG. 7 is a schematic diagram of one configuration of the indicator light circuit of FIG. 1;

FIG. 8 is a schematic diagram of a CPU shown in FIG. 1;

fig. 9 is another schematic structural diagram of the cpu in fig. 1.

Description of reference numerals: 10. an RS485 interface unit; 20. a WIFI interface unit; 30. an Ethernet interface unit; 40. a USB interface unit; 50. a central processing unit; 51. a first protocol converter; 52. a second protocol converter; 53. a third protocol converter; 54. a fourth protocol converter; 55. a data selector; 60. a DALI interface unit; 61. a voltage stabilizing circuit; 62. a bridge circuit; 70. an indicator light circuit; 80. a power source.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. The first resistance and the second resistance are both resistances, but they are not the same resistance.

It is to be understood that "connection" in the following embodiments is to be understood as "electrical connection", "communication connection", and the like if the connected circuits, modules, units, and the like have communication of electrical signals or data with each other.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, as used in this specification, the term "and/or" includes any and all combinations of the associated listed items.

In one embodiment, as shown in fig. 1, there is provided a lighting protocol conversion apparatus including an RS485 interface unit 10, a WIFI interface unit 20, an ethernet interface unit 30, a USB interface unit 40, a central processor 50, and a DALI interface unit 60. The RS485 interface unit 10 is used for connecting with the lighting control device and receiving an RS485 protocol command sent by the lighting control device. The WIFI interface unit 20 is used for connecting with the mobile terminal and receiving a WIFI protocol instruction sent by the mobile terminal. The ethernet interface unit 30 is used for connecting with a remote server and receiving ethernet protocol commands sent by the remote server. The USB interface unit 40 is used to connect with a local computer and receive USB protocol commands sent by the local computer. The central processor 50 is connected to the RS485 unit 10, the WIFI interface unit 20, the ethernet interface unit 30, and the USB interface unit 40, and is configured to convert the RS485 protocol instruction, the WIFI protocol instruction, the ethernet protocol instruction, and the USB protocol instruction into a DALI protocol instruction. The DALI interface unit 60 is connected to the central processor 50 and is used to connect to the lighting system and send DALI protocol commands to the lighting system.

The RS485 protocol is a typical serial communication standard, and defines voltage, impedance, and the like, but does not define a software protocol. The RS-485 bus standard specifies the electrical characteristic standard of the bus interface, i.e. the definition of 2 logic states: the positive level is between +2V to +6V, which represents a logic state; a negative level between-2V and-6V represents another logic state; the digital signals adopt a differential transmission mode, so that the interference of noise signals can be effectively reduced. Through the RS485 interface unit 10, can be connected with the lighting control equipment, receive the RS485 agreement instruction that the lighting control equipment sent.

WIFI is a wireless lan technology established in IEEE 802.11 standard, and is also a wireless network transmission technology which is most widely used today. WIFI actually converts wired network signals into wireless signals, and uses wireless routers for receiving by related computers, mobile phones, tablets, etc. supporting its technology. Wi-Fi has the main advantage of not requiring wires and can be routed without restrictions. However, Wi-Fi signals are also provided by wired networks, such as ADSL in homes, cell broadband, etc., and can be converted into Wi-Fi signals by connecting a wireless router. Through the WIFI interface unit 20, the mobile terminal can be connected to receive a WIFI protocol command sent by the mobile terminal.

Ethernet is a computer local area network technology. The IEEE 802.3 standard of the IEEE organization sets out a technical standard of ethernet, which specifies the contents of a link including a physical layer, an electrical signal, and a medium access layer protocol, which is the most commonly used local area network technology at present. The ethernet interface unit 30 can be connected to a remote server to receive ethernet protocol commands sent by the remote server.

USB (Universal Serial Bus) is an external Bus standard for standardizing connection and communication between a computer and external devices, and is an interface technology applied in the field of PCs. Through the USB interface unit 40, the USB device can be connected to a local computer to receive USB protocol commands sent by the local computer.

The lighting protocol conversion device comprises an RS485 interface unit, a WIFI interface unit, an Ethernet interface unit, a USB interface unit, a central processing unit and a DALI interface unit. The RS485 interface unit is used for being connected with the lighting control equipment and receiving an RS485 protocol command sent by the lighting control equipment, so that the lighting control equipment can send the RS485 protocol command to the lighting protocol conversion device through the RS485 interface. The WIFI interface unit is used for being connected with the mobile terminal and receiving a WIFI protocol instruction sent by the mobile terminal, so that the mobile terminal can send the WIFI protocol instruction to the lighting protocol conversion device through the WIFI interface unit. The Ethernet interface unit is used for connecting with the remote server and receiving the Ethernet protocol command sent by the remote server, so that the remote server can send the Ethernet protocol command to the lighting protocol conversion device through the Ethernet interface unit. The USB interface unit is used for being connected with the local computer and receiving the USB protocol command sent by the local computer, so that the local computer can send the USB protocol command to the lighting protocol conversion device through the USB interface unit. The central processing unit is respectively connected with the RS485 unit, the WIFI interface unit, the Ethernet interface unit and the USB interface unit and is used for converting the RS485 protocol instruction, the WIFI protocol instruction, the Ethernet protocol instruction and the USB protocol instruction into a DALI protocol instruction, so that various protocol instructions received by the lighting protocol conversion device can be uniformly converted into the DALI protocol instruction through the central processing unit. The DALI interface unit is respectively connected with the central processing unit and the lighting system and used for sending the DALI protocol instruction converted by the central processing unit to the lighting system, so that the control of the lighting system can be realized. The lighting protocol conversion device is compatible with a DALI lighting system by adopting control equipment of various protocols, and can effectively promote application and popularization of the intelligent home lighting system.

In addition, the RS485 interface unit is used for being connected with the lighting control equipment and receiving an RS485 protocol instruction sent by the lighting control equipment, the WIFI interface unit is used for being connected with the mobile terminal and receiving a WIFI protocol instruction sent by the mobile terminal, the Ethernet interface unit is used for being connected with the remote server and receiving an Ethernet protocol instruction sent by the remote server, and the USB interface unit is used for being connected with the local computer and receiving a USB protocol instruction sent by the local computer, so that the control instructions sent by various control equipment can be compatible to a DALI lighting system through the lighting protocol conversion device, and popularization and application of the lighting control technology and reduction of implementation cost are facilitated.

In one embodiment, as shown in fig. 2, the DALI interface unit 60 includes a read data optocoupler U1, a write data optocoupler U2, a read data resistor R1, a write data resistor R2, a base resistor R3, an emitter resistor R4, a transistor Q, a voltage regulator circuit 61, a bridge circuit 62, and a DALI terminal P1. Two terminals of the DALI wiring terminal P1 are respectively connected with two alternating current input ends of the bridge circuit 62, an anode output end of the bridge circuit 62 is connected with an anode input end of the read data optocoupler U1 through the voltage stabilizing circuit 61, and a cathode input end of the read data optocoupler U1 is connected with a cathode output end of the bridge circuit 62. The positive output end of the read data optical coupler U1 is connected with a DALI reading end of the central processing unit 50 and is connected with a power supply through a read data resistor R1, and the negative output end of the read data optical coupler U1 is grounded. The positive input end of the write data optocoupler U2 is connected with the DALI write-in end of the central processing unit 50 through a write data resistor R2, and the negative input end of the write data optocoupler U2 is grounded. The positive output end of the data writing optical coupler U2 and the collector of the triode Q are connected with the positive output end of the bridge circuit 62, the negative end of the data writing optical coupler is connected with the base of the triode Q through a base resistor R3 and the emitter of the triode Q through an emitter resistor R4, and the emitter of the triode Q is connected with the negative output end of the bridge circuit 62.

In this embodiment, the DALI interface unit 60 includes a read data optocoupler U1, a write data optocoupler U2, a read data resistor R1, a write data resistor R2, a base resistor R3, an emitter resistor R4, a transistor Q, a voltage stabilizing circuit 61, a bridge circuit 62, and a DALI connection terminal P1, where the bridge circuit 62 can ensure that read-write data of the central processing unit 50 are both direct current signals, the voltage stabilizing circuit 61 is favorable for stability of reading data, the combination of the base resistor R3, the emitter resistor R4, and the transistor Q is favorable for transmission of the write-write data, and the read data optocoupler U1 and the write data optocoupler U2 can achieve optoelectronic isolation of the read-write data.

Alternatively, as shown in fig. 2, the bridge circuit 62 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The anode of the first diode D1 is connected to the cathode of the fourth diode D4, the cathode of the first diode D1 is connected to the cathode of the second diode D2, the anode of the second diode D2 is connected to the cathode of the third diode D3, and the anode of the third diode D3 is connected to the anode of the fourth diode D4. A connection point of the anode of the first diode D1 and the cathode of the fourth diode D4, which serves as an alternating current input terminal of the bridge circuit 62, is connected to one terminal of a DALI connection terminal P1; the junction of the anode of the second diode D2 and the cathode of the third diode D3, which serves as the other ac input terminal of the bridge circuit 62, is connected to the other terminal of the DALI connection terminal P1. The connection point of the negative electrode of the first diode D1 and the negative electrode of the second diode D2 is used as the positive electrode output end of the bridge circuit 62, is connected with the positive electrode input end of the read data optocoupler U1 through the voltage stabilizing circuit 61, and is connected with the positive electrode output end of the write data optocoupler U2 and the collector of the triode Q; the connection point of the anode of the third diode D3 and the anode of the fourth diode D4 is used as the cathode output end of the bridge circuit 62, is connected with the cathode input end of the read data optocoupler U1, and is connected with the emitter of the triode Q.

Specifically, as shown in fig. 2, pin 1 of the DALI terminal P1 is connected to a connection point of the anode of the first diode D1 and the cathode of the fourth diode D4, and pin 2 of the DALI terminal P1 is connected to a connection point of the anode of the second diode D2 and the cathode of the third diode D3.

Alternatively, as shown in fig. 2, the voltage regulation circuit 61 includes a zener diode D5 and a voltage regulation resistor R5. The voltage-stabilizing diode D5 and the voltage-stabilizing resistor R5 are connected in series between the anode output end of the bridge circuit 62 and the anode input end of the read data optocoupler U1.

In one embodiment, as shown in fig. 3, the RS485 interface unit 10 includes an SN75176B chip U3, a first output terminal resistor R6, a second output terminal resistor R7, a power terminal resistor R8, a ground terminal resistor R9, and an RS485 connection terminal P2. Pin 1 of the SN75176B chip U3 is connected to an RS485 read terminal of the cpu 50, pin 4 of the SN75176B chip U3 is connected to an RS485 write terminal of the cpu 50, pin 5 of the SN75176B chip U3 is grounded, pin 6 of the SN75176B chip U3 is connected to a second terminal of the RS485 connection terminal P2 through a first output resistor R6, pin 7 of the SN75176B chip U3 is connected to a first terminal of the RS485 connection terminal P2 through a second output resistor R7, and pin of the SN75176B chip U3 is connected to a power supply. The second wiring end of the RS485 wiring terminal P2 is connected with a power supply through a power supply end resistor R8, the first wiring end of the RS485 wiring terminal P2 is grounded through a grounding end resistor R9, and the third grounding end of the RS485 wiring terminal P2 is grounded.

In this embodiment, the RS485 interface unit 10 includes an SN75176B chip U3, a first output end resistor R6, a second output end resistor R7, a power supply end resistor R8, a ground end resistor R9, and an RS485 connection terminal P2, pin 1 of the SN75176B chip U3 is connected to an RS485 read end of the cpu 50, pin 4 of the SN75176B chip U3 is connected to an RS485 write end of the cpu 50, pin 6 of the SN75176B chip U3 is connected to a second connection terminal of the RS485 connection terminal P2 through the first output end resistor R6, pin 7 of the SN75176B chip U3 is connected to a first connection terminal of the RS485 connection terminal P2 through the second output end resistor R7, so as to implement reading and writing of RS485 data.

In one embodiment, as shown in fig. 4, the WIFI interface unit 20 includes an ESP8266 chip U4, pin 1 of an ESP8266 chip U4 is connected to the power supply, pin 2 of an ESP8266 chip U4 is connected to the WIFI write terminal of the central processor 50, pin 7 of an ESP8266 chip U4 is connected to the WIFI read terminal of the central processor 50, and pin 8 of an ESP8266 chip U4 is connected to the ground.

In this embodiment, ESP8266 is a serial WiFi module, and the MCU can be integrated inside to realize serial communication between the single-chip microcomputers. WIFI interface unit 20 includes ESP8266 chip U4, and ESP8266 chip U4's pin 2 is connected with central processing unit 50's WIFI write-in end, and ESP8266 chip U4's pin 7 is connected with central processing unit 50's WIFI read-in end, can realize the reading and writing of wiFi data.

Specifically, as shown in fig. 4, pin 4 and pin 5 of ESP8266 chip U4 are connected to the write clear terminal of the cpu 50, pin 4 and pin 5 of ESP8266 chip U4 are connected to the general input/output terminal of the cpu 50, and pin 6 of ESP8266 chip U4 is connected to the write enable terminal of the cpu 50.

In one embodiment, as shown in fig. 5, the ethernet interface unit 30 includes a LAN8720A chip U5, an RJ45 chip U6, an oscillation circuit, a clock circuit, first to tenth resistors R11 to R20, and first to tenth capacitors C1 to C10.

The pin 17 and the pin 18 of the LAN8720A chip U5 are respectively connected to two ethernet write terminals of the central processor 50, the pin 7 and the pin 8 of the LAN8720A chip U5 are respectively connected to two ethernet read terminals of the central processor 50, the pin 15 of the LAN8720A chip U5 is connected to the first resistor R11, the pin 24 of the LAN8720A chip U5 is connected to the second resistor R12, the pin 3 of the LAN8720A chip U5 is connected to the seventh resistor R17, the pin 2 of the LAN8720A chip U5 is connected to the eighth resistor R18, the pin 19 of the LAN8720A chip U5 is connected to the first capacitor C1, the pin 1 of the LAN8720A chip U A is connected to the second capacitor C A, the pin 9 of the LAN8720 chip U A is connected to the third capacitor C A, the pin 6 of the LAN8720 chip U A is connected to the ground, the fourth capacitor C A, the pin A of the LAN 8772 is connected to the fourth capacitor C A, the third capacitor C A, the pin A of the LAN 8720R A, the LAN 8772, the pin A is connected to the fourth capacitor C A, the pin A of the LAN 8772, the LAN A and the fourth resistor A, Pin 22 of the chip U5 of the LAN8720A is connected to a first connection terminal of the oscillation circuit through a sixth resistor R16, pin 19 of the chip U5 of the LAN8720A, and pin 1 of the chip U5 of the LAN8720A, pin 9 of the chip U5 of the LAN8720A is connected to a second connection terminal of the oscillation circuit, pin 5 of the chip U5 of the LAN8720A is connected to one connection terminal of the clock circuit, and pin 4 of the chip U5 of the LAN8720A is connected to the other connection terminal of the clock circuit.

Pin 4 and pin 5 of the RJ45 chip U6 are connected to the first connection terminal of the oscillation circuit, pin 4 and pin 5 of the RJ45 chip U6 are connected to the first connection terminal of the oscillation circuit through the sixth capacitor C6, pin 1 of the RJ45 chip U6 is connected to the ground through the seventh capacitor C7, pin 2 of the RJ45 chip U6 is connected to the ground through the eighth capacitor C8, pin 3 of the RJ45 chip U6 is connected to the ground through the ninth capacitor C9, pin 6 of the RJ45 chip U6 is connected to the ground through the tenth capacitor C10, pin 7 of the RJ45 chip U6 is floating, and pin 10 of the RJ 6 chip U6 is connected to pin 8, pin 13 and pin 14 of the RJ 6 chip U6 through the ninth resistor R6 and pin 11 of the RJ 6 chip U6 through the tenth resistor R6.

The first resistor R11 to the tenth resistor R20 include a first resistor R11, a second resistor R12, a third resistor R13, a fourth resistor R14, a fifth resistor R15, a sixth resistor R16, a seventh resistor R17, an eighth resistor R18, a ninth resistor R19 and a tenth resistor R20, and the first capacitor C1 to the tenth capacitor C10 include a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9 and a tenth capacitor C10.

In this embodiment, the ethernet interface unit 30 includes a LAN8720A chip U5, an RJ45 chip U6, an oscillation circuit, a clock circuit, a first resistor R11 to a tenth resistor R20, and a first capacitor C1 to a tenth capacitor C10, where the LAN8720A chip is a network module, and the RJ45 chip is an ethernet interface, and the read/write of ethernet data can be realized through the cooperation of the network module and the RJ45 chip.

Specifically, the pin 12 of the chip U5 of the LAN8720A is connected to one interface configuration terminal of the cpu 50 through the eleventh resistor R21, and the pin 13 of the chip U5 of the LAN8720A is connected to the other interface configuration terminal of the cpu 50. Pin 16 of the LAN8720A chip U5 is connected to the write enable terminal of the central processor 50. Pin 11 of the chip U5 of the LAN8720A is connected to a reference signal terminal of the cpu 50, and pin 14 of the chip U5 of the LAN8720A is connected to a clock signal terminal of the cpu 50.

Optionally, as shown in fig. 5, the oscillating circuit includes an inductor L, an eleventh capacitor C11, and a twelfth capacitor C12. The inductor L is connected in series between the first connection end and the second connection end of the oscillating circuit, the eleventh capacitor C11 is connected in series between the first connection end of the oscillating circuit and the ground, and the twelfth capacitor C12 is connected in series between the second connection end of the oscillating circuit and the ground.

Alternatively, as shown in fig. 5, the clock circuit includes a crystal oscillator X, a twelfth resistor R22, a thirteenth capacitor C13, and a fourteenth capacitor C14. The crystal oscillator X and the twelfth resistor R22 are connected in parallel between two connection terminals of the clock circuit, the thirteenth capacitor C13 is connected in series between one connection terminal of the clock circuit and the ground, and the fourteenth capacitor C14 is connected in series between the other connection terminal of the clock circuit and the ground.

In one embodiment, as shown in fig. 6, the USB interface unit 40 includes a USB connection terminal P3, a positive resistor R23, and a negative resistor R24, wherein a first terminal of the USB connection terminal P3 is connected to the power supply, a second terminal of the USB connection terminal P3 is connected to one USB data terminal of the cpu 50 through a positive resistor R23, a third terminal of the USB connection terminal P3 is connected to the other USB data terminal of the cpu 50 through a negative resistor R24, a fourth terminal of the USB connection terminal P3 is floating, and a fifth terminal of the USB connection terminal P3 is grounded.

In this embodiment, the USB interface unit 40 includes a USB connection terminal P3, a positive resistor R23, and a negative resistor R24, a second connection terminal of the USB connection terminal P3 is connected to one USB data end of the central processing unit 50 through a positive resistor R23, and a third connection terminal of the USB connection terminal P3 is connected to the other USB data end of the central processing unit 50 through a negative resistor R24, so that the USB data can be read and written.

In one embodiment, as shown in FIG. 1, the device further includes an indicator light circuit 70. The indicator circuit 70 is connected to the central processing unit 50 and is used for indicating the operating state of the central processing unit 50.

In this embodiment, the apparatus further includes an indicator light circuit 70, which can indicate the working status of the central processing unit 50, so as to facilitate timely understanding of the data transmission condition.

Alternatively, as shown in fig. 7, the indicator light circuit 70 includes first to fifth light emitting diodes LED1 to LED5, and first to fifth matching resistors R25 to R29. The first light emitting diode LED1 and the first matching resistor R25 are connected in series between the CPU 50 and the power supply, the second light emitting diode LED2 and the second matching resistor R26 are connected in series between the CPU 50 and the power supply, the third light emitting diode LED3 and the third matching resistor R27 are connected in series between the CPU 50 and the power supply, the fourth light emitting diode LED4 and the first matching resistor R28 are connected in series between the CPU 50 and the power supply, and the fifth light emitting diode LED5 and the first matching resistor R29 are connected in series between the CPU 50 and the power supply.

Among them, the first to fifth light emitting diodes LED1 to LED5 include a first light emitting diode LED1, a second light emitting diode LED2, a third light emitting diode LED3, a fourth light emitting diode LED4, and a fifth light emitting diode LED 5. The first matching resistor R25 to the fifth matching resistor R29 include a first matching resistor R25, a second matching resistor R26, a third matching resistor R27, a fourth matching resistor R28 and a fifth matching resistor R29.

In one embodiment, as shown in FIG. 1, the device further includes a power source 80. The power supply 80 is connected to the cpu 50.

In this embodiment, the device further comprises a power supply 80, which can supply power to the entire device.

In one embodiment, as shown in FIG. 8, the CPU 50 includes an STM32F407 chip U7, the VDD terminal, the VDD _1 terminal, the VDD _2 terminal, the VDD _3 terminal, and the VDD _4 terminal of the STM32F407 chip U7 are connected to a power supply, and the VSS terminal, the VSS _1 terminal, the VSS _2 terminal, the VSS _3 terminal, and the VSS _4 terminal of the STM32F407 chip U7 are connected to ground.

The UART1_ RX end of the STM32F407 chip U7 is connected with a pin 7 of an ESP8266 chip U4 in the WIFI interface unit 20, the UART1_ TX end of the STM32F407 chip U7 is connected with a pin 2 of an ESP8266 chip U4 in the WIFI interface unit 20, the PIO9 end of the STM32F407 chip U7 is connected with a pin 3 of the ESP8266 chip U4 in the WIFI interface unit 20, the PIO10 end of the STM32F407 chip U7 is connected with a pin 6 of an ESP8266 chip U4 in the WIFI interface unit 20, the PIO11 end of the STM32F407 chip U7 is connected with a pin 4 of an ESP8266 chip U4 in the WIFI interface unit 20, and the PIO12 end of the STM32F407 chip U7 is connected with a pin 5 of an ESP8266 chip U4 in the WIFI interface unit 20.

An ETH _ MDIO terminal of the STM32F407 chip U7 is connected to the pin 12 of the LAN8720A chip U5 in the Ethernet interface unit 30 through an eleventh resistor R21, an ETH _ MDC terminal of the STM32F407 chip U5 is connected to the pin 13 of the LAN8720 5 chip U5 in the Ethernet interface unit 30, an RMII _ TXD 5 terminal of the STM32F407 chip U5 is connected to the pin 17 of the LAN8720 chip U5 in the Ethernet interface unit 30, an RMII _ TXD 5 terminal of the STM32F407 chip U5 is connected to the pin 18 of the LAN8720 chip U5 in the Ethernet interface unit 30, an RMII _ TX _ EN terminal of the STM32F chip U5 is connected to the pin 16 of the LAN8720 chip U5 in the Ethernet interface unit 30, an RMII _ RXD 5 terminal of the STM32F407 chip U5 is connected to the pin 8772 of the LAN8720 chip U5 in the LAN interface unit 30, an RMII _ TX _ RD 3 of the LAN 8772 in the LAN interface unit 5, an RMII _ TX _ RD 3 of the STM32F407 chip U5 in the LAN interface unit 5, an RMII _ RD 5 terminal of the LAN 8772 in the LAN interface unit 5, an RMII _ TX _ RD 7 of the LAN interface unit 5 is connected to the LAN8720 chip U5 in the LAN interface unit 5, an RMII interface unit 5 of the LAN 8772 in the LAN 8772, an RMII interface unit 5 of the LAN 8772, an RMII 5 of the LAN 8772, an RMII interface unit 5 of the LAN 8772 in the LAN 8772 of the LAN 8772, an RMII 5 in the LAN 8772, an RMII unit 5, an RMI unit 5, an RMII 5 of the LAN 8772, an RMII 5, an RMII unit 5 of the LAN interface unit 5 of the LAN 8772, an RMI unit 5 of the LAN 8772, an RMII unit 5 of the LAN 8772 in the LAN 8772, an RMII 5 of the LAN 5, an RMII 5, an RMI unit 5, an RMII 5, the PIO13 terminal of the STM32F407 chip U7 is connected to pin 15 of the LAN8720A chip U5 in the Ethernet interface unit 30.

The DM end of the STM32F407 chip U7 is connected with the positive resistor R23 in the USB interface unit 40, and the DP end of the STM32F407 chip U7 is connected with the negative resistor R24 in the USB interface unit 40.

The PIO1 end of the STM32F407 chip U7 is connected with a DALI reading end in the DALI interface unit 60, and the PIO2 end of the STM32F407 chip U7 is connected with a DALI writing end in the DALI interface unit 60.

The UART0_ RX end of the STM32F407 chip U7 is connected with pin 1 of the SN75176B chip U3 in the DALI interface unit 60, the UART0_ TX end of the STM32F407 chip U7 is connected with pin 4 of the SN75176B chip U3 in the DALI interface unit 60, and the PIO3 end of the STM32F407 chip U7 is connected with pin 2 and pin 3 of the SN75176B chip U3 in the DALI interface unit 60.

The PIO4 end of the STM32F407 chip U7 is connected with a first matching resistor R25 in the indicator light circuit 70, the PIO5 end of the STM32F407 chip U7 is connected with a second matching resistor R26 in the indicator light circuit 70, the PIO6 end of the STM32F407 chip U7 is connected with a third matching resistor R27 in the indicator light circuit 70, the PIO7 end of the STM32F407 chip U7 is connected with a fourth matching resistor R28 in the indicator light circuit 70, and the PIO8 end of the STM32F407 chip U7 is connected with a fifth matching resistor R29 in the indicator light circuit 70.

In another embodiment, as shown in fig. 9, the central processor 50 includes a first protocol converter 51, a second protocol converter 52, a third protocol converter 53 and a fourth protocol converter 54. The first protocol converter 51 is connected to the RS485 interface unit 10 and the DALI interface unit 60, respectively, and is configured to convert the RS485 protocol command into a DALI protocol command. The second protocol converter 52 is connected to the WIFI interface unit 20 and the DALI interface unit 60, respectively, and is configured to convert the WIFI protocol instruction into a DALI protocol instruction. The third protocol converter 53 is connected to the ethernet interface unit 30 and the DALI interface unit 60, respectively, for converting ethernet protocol commands into DALI protocol commands. The fourth protocol converter 54 is connected to the USB interface unit 40 and the DALI interface unit 60, respectively, and is configured to convert the USB protocol commands into DALI protocol commands.

The protocol converter is also called interface converter, which can make the hosts in communication network adopting different high-level protocols still cooperate with each other to complete various distributed applications. Specifically, protocol conversion is a mapping that maps a sequence of information (or events) sent and received by one protocol to a sequence of information sent and received by another protocol.

In this embodiment, the central processing unit 50 includes a first protocol converter 51, a second protocol converter 52, a third protocol converter 53 and a fourth protocol converter 54, and may convert the RS485 protocol instruction, the WIFI protocol instruction, the ethernet protocol instruction and the USB protocol instruction into the DALI protocol instruction, so as to implement uniform conversion of different protocol instructions into the DALI protocol instruction.

Optionally, as shown in fig. 9, the central processor 50 further includes a data selector 55. The data selector 55 has four data input terminals, one data output terminal, and four address input terminals. The four data input terminals are connected to the first protocol converter 51, the second protocol converter 52, the third protocol converter 53 and the fourth protocol converter 54, respectively, and the data output terminal is connected to the DALI interface unit 60, so that the data selector 55 is connected in series between the first protocol converter 51, the second protocol converter 52, the third protocol converter 53, the fourth protocol converter 54 and the DALI interface unit 60. The four address inputs are connected to a first protocol converter 51, a second protocol converter 52, a third protocol converter 53 and a fourth protocol converter 54, respectively.

In this embodiment, the central processing unit 50 further includes a data selector 55, four data input terminals are respectively connected to the first protocol converter 51, the second protocol converter 52, the third protocol converter 53 and the fourth protocol converter 54, and a data output terminal is connected to the DALI interface unit 60, so that the data selector 55 is connected in series between the first protocol converter 51, the second protocol converter 52, the third protocol converter 53, the fourth protocol converter 54 and the DALI interface unit 60, and one converted DALI protocol command can be selected from the first protocol converter 51, the second protocol converter 52, the third protocol converter 53 and the fourth protocol converter 54 and output.

In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. An illumination protocol conversion apparatus, characterized in that the apparatus comprises:

the RS485 interface unit (10) is used for being connected with the lighting control equipment and receiving an RS485 protocol command sent by the lighting control equipment;

the WIFI interface unit (20) is used for being connected with the mobile terminal and receiving a WIFI protocol instruction sent by the mobile terminal;

the Ethernet interface unit (30) is used for connecting with a remote server and receiving an Ethernet protocol instruction sent by the remote server;

the USB interface unit (40) is used for connecting with a local computer and receiving a USB protocol instruction sent by the local computer;

the central processing unit (50) is respectively connected with the RS485 unit (10), the WIFI interface unit (20), the Ethernet interface unit (30) and the USB interface unit (40) and is used for converting the RS485 protocol instruction, the WIFI protocol instruction, the Ethernet protocol instruction and the USB protocol instruction into a DALI protocol instruction;

a DALI interface unit (60) connected to the central processor (50) and adapted to connect to a lighting system and send the DALI protocol instructions to the lighting system.

2. The apparatus according to claim 1, wherein said central processor (50) comprises:

the first protocol converter (51) is respectively connected with the RS485 interface unit (10) and the DALI interface unit (60) and is used for converting the RS485 protocol instruction into a DALI protocol instruction;

the second protocol converter (52) is respectively connected with the WIFI interface unit (20) and the DALI interface unit (60) and is used for converting the WIFI protocol instruction into a DALI protocol instruction;

a third protocol converter (53) connected to the ethernet interface unit (30) and the DALI interface unit (60), respectively, for converting the ethernet protocol commands into DALI protocol commands;

a fourth protocol converter (54) connected to the USB interface unit (40) and the DALI interface unit (60), respectively, for converting the USB protocol commands into DALI protocol commands.

3. The apparatus of claim 2, wherein said central processor (50) further comprises:

a data selector (55) having four data inputs, one data output and four address inputs; -said four data inputs are connected to said first protocol converter (51), said second protocol converter (52), said third protocol converter (53) and said fourth protocol converter (54), respectively, -said data outputs are connected to said DALI interface unit (60), with said data selector (55) connected in series between said first protocol converter (51), said second protocol converter (52), said third protocol converter (53), said fourth protocol converter (54) and said DALI interface unit (60); the four address inputs are connected to the first protocol converter (51), the second protocol converter (52), the third protocol converter (53) and the fourth protocol converter (54), respectively.

4. The device according to any of the claims 1 to 3, characterized in that the DALI interface unit (60) comprises a read data opto-coupler U1, a write data opto-coupler U2, a read data resistor R1, a write data resistor R2, a base resistor R3, an emitter resistor R4, a transistor Q, a voltage stabilizing circuit (61), a bridge circuit (62) and a DALI terminal P1; two terminals of the DALI wiring terminal P1 are respectively connected with two alternating current input ends of the bridge circuit (62), an anode output end of the bridge circuit (62) is connected with an anode input end of the read data optocoupler U1 through the voltage stabilizing circuit (61), and a cathode input end of the read data optocoupler U1 is connected with a cathode output end of the bridge circuit (62); the positive output end of the read data optical coupler U1 is connected with a DALI reading end of the central processing unit (50) and is connected with a power supply through the read data resistor R1, and the negative output end of the read data optical coupler U1 is grounded; the positive input end of the write data optocoupler U2 is connected with the DALI write-in end of the central processing unit (50) through the write data resistor R2, and the negative input end of the write data optocoupler U2 is grounded; the positive output end of the write data optocoupler U2 and the collector of the triode Q are connected with the positive output end of the bridge circuit (62), and the negative end of the write data optocoupler is connected with the base of the triode Q through the base resistor R3 and connected with the emitter of the triode Q through the emitter resistor R4.

5. The apparatus according to any one of claims 1 to 3, wherein the RS485 interface unit (10) comprises an SN75176B chip U3, a first output terminal resistor R6, a second output terminal resistor R7, a power terminal resistor R8, a ground terminal resistor R9, and an RS485 terminal P2; pin 1 of the SN75176B chip U3 is connected to an RS485 read terminal of the cpu (50), pin 4 of the SN75176B chip U3 is connected to an RS485 write terminal of the cpu (50), pin 5 of the SN75176B chip U3 is grounded, pin 6 of the SN75176B chip U3 is connected to a second terminal of the RS485 connection terminal P2 through a first output resistor R6, pin 7 of the SN75176B chip U3 is connected to a first terminal of the RS485 connection terminal P2 through a second output resistor R7, and pin of the SN75176B chip U3 is connected to a power supply; the second wiring end of the RS485 wiring terminal P2 is connected with a power supply through a power supply end resistor R8, the first wiring end of the RS485 wiring terminal P2 is grounded through a grounding end resistor R9, and the third grounding end of the RS485 wiring terminal P2 is grounded.

6. The device according to any one of claims 1 to 3, wherein the WIFI interface unit (20) comprises an ESP8266 chip U4, wherein pin 1 of the ESP8266 chip U4 is connected with a power supply, pin 2 of the ESP8266 chip U4 is connected with a WIFI write terminal of the central processor (50), pin 7 of the ESP8266 chip U4 is connected with a WIFI read terminal of the central processor (50), and pin 8 of the ESP8266 chip U4 is grounded.

7. The apparatus according to any of claims 1 to 3, wherein the Ethernet interface unit (30) comprises a LAN8720A chip U5, an RJ45 chip U6, an oscillation circuit, a clock circuit, a first resistor R11 to a tenth resistor R20, a first capacitor C1 to a tenth capacitor C10; the pin 17 and the pin 18 of the LAN8720 chip U are respectively connected with two ethernet write terminals of the central processing unit (50), the pin 7 and the pin 8 of the LAN8720 chip U are respectively connected with two ethernet read terminals of the central processing unit (50), the pin 15 of the LAN8720 chip U is connected with a second resistor R through a first resistor R, the pin 24 of the LAN8720 chip U is connected with a second resistor R, the pin 3 of the LAN8720 chip U is connected with a seventh resistor R, the pin 2 of the LAN8720 chip U is connected with an eighth resistor R, the pin 19 of the LAN8720 chip U is connected with a first capacitor C, the pin 1 of the LAN8720 chip U is connected with a second capacitor C, the pin 9 of the LAN8720 chip U is connected with a third capacitor C, the pin 6 of the LAN8720 chip U is connected with a fourth capacitor C and a fifth capacitor C in parallel, the pin 25 of the LAN8720 chip U is connected with ground, and the pin 21 of the LAN8720 chip U is connected with a third resistor R, A pin 20 of a chip U5 of the LAN8720A is connected with a first connecting end of the oscillating circuit through a fourth resistor R14, a pin 23 of a chip U5 of the LAN8720A is connected with a first connecting end of the oscillating circuit through a fifth resistor R15, a pin 22 of a chip U5 of the LAN8720A is connected with a sixth resistor R16, a pin 19 of a chip U5 of the LAN8720A and a pin 1 of a chip U5 of the LAN8720A, a pin 9 of a chip U5 of the LAN8720A is connected with a second connecting end of the oscillating circuit, a pin 5 of a chip U5 of the LAN8720A is connected with one connecting end of the clock circuit, and the other connecting end of the clock circuit is connected into a pin 4 of a chip U5 of the LAN 8720A; pin 4 and pin 5 of the RJ45 chip U6 are connected to the first connection end of the oscillation circuit, pin 4 and pin 5 of the RJ45 chip U6 are connected to the first connection end of the oscillation circuit through a sixth capacitor C6, pin 1 of the RJ45 chip U6 is connected to the seventh capacitor C7, pin 2 of the RJ45 chip U6 is connected to the ground through an eighth capacitor C8, pin 3 of the RJ45 chip U6 is connected to the ninth capacitor C9, pin 6 of the RJ45 chip U6 is connected to the ground through a tenth capacitor C10, pin 7 of the RJ45 chip U6 is floating, pin 10 of the RJ45 chip U6 is connected to pin 8, pin 13 and pin 14 of the RJ45 chip U6 through a ninth resistor R19, and pin 11 of the RJ45 chip U6 is connected to the tenth resistor R20.

8. A device according to any one of claims 1 to 3, wherein said USB interface unit (40) comprises a USB terminal P3, a positive resistor R23 and a negative resistor R24, said USB terminal P3 being connected to a power supply at a first terminal, said USB terminal P3 being connected to one USB data terminal of said central processor (50) via said positive resistor R23 at a second terminal, said USB terminal P3 being connected to another USB data terminal of said central processor (50) via said negative resistor R24 at a third terminal, said USB terminal P3 being floating at a fourth terminal and said USB terminal P3 being grounded at a fifth terminal.

9. The apparatus of any one of claims 1 to 3, further comprising:

and the indicating lamp circuit (70) is connected with the central processing unit (50) and is used for indicating the working state of the central processing unit (50).

10. The apparatus of any one of claims 1 to 3, further comprising:

and the power supply (80) is connected with the central processing unit (50).