CN214850544U

CN214850544U - Battery module equalization circuit with hardware control logic priority

Info

Publication number: CN214850544U
Application number: CN202120567732.4U
Authority: CN
Inventors: 张明艳
Original assignee: Lishen Power Battery System Co Ltd
Current assignee: Lishen Qingdao New Energy Co Ltd
Priority date: 2021-03-19
Filing date: 2021-03-19
Publication date: 2021-11-23
Anticipated expiration: 2031-03-19

Abstract

The utility model discloses a battery module equalizing circuit with priority of hardware control logic, which comprises a plurality of serially connected single batteries B; the equalization circuit comprises a plurality of equalization loops (100) and a battery front end detection chip (200); each single battery B is correspondingly connected with one equalizing loop (100) respectively; the battery front end detection chip (200) is connected with the plurality of equalization loops; the utility model has scientific design, increases the external balance switch and the balance loop according to the working principle of the battery front end detection chip, reduces the current flowing through the balance switch integrated inside the battery front end detection chip, and controls the on and off of the external balance switch through the balance switch and the balance loop integrated inside the battery front end detection chip; meanwhile, by designing hardware control logic that any adjacent equalization loop can not be started, the phenomenon that the equalization switch is broken down by high voltage is avoided, and the reliability of the equalization function is improved.

Description

Battery module equalization circuit with hardware control logic priority

Technical Field

The utility model relates to a battery management technology field especially relates to a prior battery module equalizer circuit of hardware control logic.

Background

In the field of new energy application, lithium batteries are increasingly used in electronic and electrical products, such as electric vehicles, electric bicycles, electric tools, communication base stations, robots, and the like. In order to enable the lithium battery to be safely and reliably used, a Battery Management System (BMS) is required to monitor the use state of the lithium battery and implement protection functions such as overcharge, overdischarge, and over-temperature.

In practical applications, a battery module or a battery system formed by connecting a plurality of single batteries in series is generally used to supply power to a load, however, since the performance of the single batteries is not absolutely consistent, a difference in the electric quantity between each single battery may occur, if the difference is serious, the single battery with a lower electric quantity may not be fully charged or always enters an overdischarge state first, and the single battery with a higher electric quantity may always enter an overcharge state first, which not only reduces the cycle life of the battery module, but also may cause a safety accident because the single batteries with a larger difference are frequently overcharged and overdischarged, and therefore, the balancing circuit in the battery management system is used to reduce the difference between the single batteries or maintain the difference not to increase any more, so as to prolong the cycle life of the battery module as much as possible, the occurrence probability of safety accidents is reduced.

In the existing passive equalization technical scheme, a special battery front-end detection chip and an external equalization resistor are generally adopted to realize equalization of single batteries. The battery front end detection chip is an integrated detection chip, is mainly used for detecting the voltage and the temperature of a single battery and also has a balancing function; some integrated detection chips only provide a balance control signal to control the on and off of an external balance switch; and some integrated detection chips integrate the equalization switch in the chip and internally control the on and off of the equalization switch.

For a battery front-end detection chip integrating equalization switches inside, the maximum value of the allowed equalization current is generally about several hundred milliamperes, so when the equalization switches inside the chip are switched on, the heat productivity of the battery front-end detection chip is extremely large, the switching-on time of each equalization switch needs to be extremely short, the switching-on time of the equalization switches is extremely short, the equalization effect is reduced, and the potential failure of the chip can be caused by the excessive heat productivity until the chip is completely failed.

In addition, when the capacity of the battery module is large, the equalization current needs to be correspondingly increased, and the equalization effect is reduced by the equalization current of hundreds of milliamperes due to the limitation of the maximum equalization current allowed in the battery front-end detection chip;

in addition, in the conventional balancing technical scheme, a phenomenon that the balancing switch is broken down by voltage often occurs, because when a plurality of adjacent single batteries are balanced simultaneously, the balancing switch corresponding to the single battery close to the negative end of the battery module or the battery system bears the sum of voltages of several single batteries which are adjacent in sequence and close to the positive end of the battery module or the battery system, and when the sum of the voltages exceeds the maximum specification value of the balancing switch, the balancing switch is broken down.

Therefore, there is an urgent need to develop a new technology that can further improve the reliability of the equalization circuit and the equalization effect on the battery, and reduce the occurrence probability of safety accidents.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a prior battery module equalizer circuit of hardware control logic to the technical defect who prior art exists.

Therefore, the utility model provides a battery module equalization circuit with priority of hardware control logic, wherein the battery module comprises a plurality of single batteries B connected in series;

the equalization circuit comprises a plurality of equalization loops and a battery front end detection chip;

each single battery B is correspondingly connected with one equalizing loop;

the battery front end detection chip is connected with the plurality of equalization loops;

for any battery module, an input end 1 of a balancing loop of any single battery Bm which is not connected with the positive end and the negative end of the battery module is respectively connected with a positive end Bm + of the corresponding single battery Bm and used for receiving the voltage and the current of the single battery B;

wherein m is any natural number which is more than or equal to 2 and less than n, and n is the number of the single batteries in the battery module in series connection;

the input end 2 of the equalizing loop of the single battery Bm is respectively connected with the negative electrode end Bm-of the single battery Bm and is used for receiving the voltage and the current of the single battery Bm;

the input end 3 of the equalizing loop of the single battery Bm is connected with the output end Am-1 of the adjacent equalizing loop of the high-phase of the equalizing loop and is used for receiving an equalizing control signal Am-1 output by the adjacent equalizing loop of the high-phase of the equalizing loop;

the input end 4 of the equalizing loop of the single battery Bm is connected with one output end BCm1 of the battery front end detection chip and is used for receiving an equalizing control signal BCm1 sent by the battery front end detection chip to the equalizing loop;

the input end 5 of the equalizing loop of the single battery Bm is connected with the other output end BCn2 of the battery front end detection chip and is used for receiving another equalizing control signal BCn2 sent by the battery front end detection chip to the equalizing loop;

the output end Am of the equalizing loop of the single battery Bm is connected with the input end 3 of the lower phase adjacent equalizing loop of the equalizing loop and is used for outputting an equalizing control signal Am to the lower phase adjacent equalizing loop of the equalizing loop;

for the equalization loop correspondingly connected with each single battery in one battery module, an adjacent equalization loop closer to the positive end of the battery module is defined as an adjacent equalization loop at a high phase of the equalization loop;

for the equalization loop correspondingly connected with each single battery in a battery module, an adjacent equalization loop closer to the negative electrode end of the battery module is defined as a lower-phase adjacent equalization loop of the equalization loop.

Preferably, for the single battery B1 connected with the positive terminal of the battery module, the input terminal 1 of the 1 st equalizing loop correspondingly connected with the positive terminal B1+ of the single battery B1 is used for receiving the voltage and the current of the single battery B1;

the 1 st equalizing loop, the input end 2 of which is connected with the negative end B1-of the battery cell B1 and is used for receiving the voltage and the current of the battery cell B1;

the input end 3 of the 1 st equalizing loop is connected with the output end Bn of the nth equalizing loop in the high-phase adjacent battery module of the battery module where the equalizing loop is located and is used for receiving the equalizing control signal Bn output by the nth equalizing loop in the high-phase adjacent battery module;

the nth equalizing loop in the high-phase adjacent battery module is the equalizing loop closest to the negative end of the high-phase adjacent battery module;

the input end 4 of the 1 st equalizing loop is connected with an output end BC11 of the battery front end detection chip and is used for receiving an equalizing control signal BC11 sent by the battery front end detection chip to the equalizing loop;

the input end 5 of the 1 st equalizing loop is connected with the other output end BC12 of the battery front end detection chip and is used for receiving another equalizing control signal BC12 sent by the battery front end detection chip to the equalizing loop;

the output end a1 of the 1 st equalizing loop is connected to the input end 3 of the lower adjacent equalizing loop of the equalizing loop, and is used for outputting an equalizing control signal a1 to the lower adjacent equalizing loop of the equalizing loop.

Preferably, for the cell Bn connected to the negative terminal of the battery module, the input terminal 1 of the nth equalizing loop correspondingly connected to the cell Bn is connected to the positive terminal Bn + of the cell Bn for receiving the voltage and current of the cell Bn;

the input end 2 of the nth equalizing loop is connected with the negative electrode end Bn-of the single battery Bn and is used for receiving the voltage and the current of the single battery Bn;

the input end 3 of the nth equalizing loop is connected with the output end An-1 of the lower phase adjacent equalizing loop of the equalizing loop and is used for receiving the equalizing control signal An-1 output by the lower phase adjacent equalizing loop of the equalizing loop;

the nth equalizing loop, the input end 4 of which is connected with an output end BCn1 of the battery front end detection chip, is used for receiving an equalizing control signal BCn1 sent by the battery front end detection chip to the equalizing loop;

the input end 5 of the nth equalizing loop is connected with the other output end BCn2 of the battery front end detection chip and is used for receiving another equalizing control signal BCn2 sent by the battery front end detection chip to the equalizing loop;

the output end An of the nth equalization loop is connected with the input end 3 of the 1 st equalization loop in the lower-phase adjacent battery module of the battery module where the equalization loop is located and used for outputting An equalization control signal An to the 1 st equalization loop in the lower-phase adjacent battery module;

the 1 st equalizing loop in the lower-phase adjacent battery module is the equalizing loop closest to the positive end of the lower-phase adjacent battery module;

for any battery module which is not connected with the positive end of the power battery system, the adjacent battery module which is closer to the positive end of the power battery system is defined as the adjacent high-phase battery module of the battery module;

for any battery module which is not connected with the negative electrode end of the power battery system, the adjacent battery module which is closer to the negative electrode end of the power battery system is defined as a low-phase adjacent battery module of the battery module;

the power battery system comprises a plurality of battery modules which are connected in series.

Preferably, for any one of the unit batteries Bm not connected with the positive terminal and the negative terminal of the battery module, the balancing circuit includes a balancing resistor RB, a balancing switch QB, resistors R1-R14, a capacitor C1, switching tubes Q1-Q6 and a diode D1, wherein:

the 1 st pin of the balancing resistor RB is used as an input end 1 of a balancing loop of the single battery Bm, is connected with a positive terminal Bm + of the single battery Bm, and is used for receiving the voltage and the balancing current of the single battery Bm;

the 2 nd pin of the balance resistor RB is connected with the T4 end;

the T4 end is respectively connected with the drain D of the equalizing switch QB and the 1 st pin of the resistor R13;

the source S of the balance switch QB is used as the input end 2 of a balance loop of the single battery Bm, is connected with the negative electrode end Bm-of the single battery Bm, and is used for receiving the voltage and the balance current of the single battery Bm;

source S of equalization switch QB, also connected to the cathode of diode D1;

the grid G of the equalizing switch QB is connected with the T3 end;

the T3 end is respectively connected with the 1 st pin of the resistor R10, the drain D of the switch tube Q1 and the drain D of the switch tube Q3;

the 2 nd pin of the resistor R13 is connected with the base B of the switch tube Q4;

the collector C of the switch tube Q4 is connected with the 2 nd pin of the resistor R12;

an emitter E of the switching tube Q4 connected to an anode of the diode D1;

the anode of the diode D1 is further connected to the 2 nd pin of the resistor R10, the source S of the switching tube Q1, the source S of the switching tube Q2, the 2 nd pin of the capacitor C1, the 2 nd pin of the resistor R3, the 2 nd pin of the resistor R14, and the source S of the switching tube Q6;

the 1 st pin of the resistor R12 is connected with the base B of the switch tube Q5;

an emitter E of the switching tube Q5, which is used as an input terminal 1 of an equalizing loop of the battery cell Bm, is further connected to the positive terminal Bm + of the battery cell Bm, the 1 st pin of the resistor R9, and the 1 st pin of the resistor R1, respectively, and is configured to receive the voltage and current of the battery cell Bm;

the collector C of the switch tube Q5 is connected with the 1 st pin of the resistor R11;

a2 nd pin of the resistor R11, which is an output end Am of an equalization loop of the single battery Bm, is respectively connected to an input end 3 of the equalization loop of the adjacent low-order single battery of the single battery Bm and is used for outputting an equalization control signal Am;

the 2 nd pin of the resistor R9 is respectively connected with the source S of the switch tube Q3 and the 1 st pin of the resistor R8;

a gate G of the switching tube Q3, which is respectively connected with the 2 nd pin of the resistor R8 and the 1 st pin of the resistor R7;

the 2 nd pin of the resistor R7 is connected with the drain D of the switch tube Q2;

a gate G of the switching tube Q2, which is respectively connected with the 1 st pin of the resistor R6 and the 1 st pin of the capacitor C1;

the 2 nd pin of the resistor R6 is connected with the T1 end;

a terminal T1 connected to the 2 nd pin of the resistor R1 and the 1 st pin of the resistor R2, respectively;

the 2 nd pin of the resistor R2 is connected with the T2 end;

a terminal T2 connected to the 1 st pin of the resistor R4, the 2 nd pin of the resistor R5 and the 1 st pin of the resistor R3, respectively;

the grid G of the switching tube Q1 is connected with the 1 st pin of the resistor R5;

a pin 2 of the resistor R4, which is an input terminal 4 of an equalizing loop of the battery cell Bm, is connected to an output terminal BCm1 of the battery front-end detecting chip, and is configured to receive an equalizing control signal BCm1 sent by the battery front-end detecting chip, where the signal state includes a high level and a low level;

the drain D of the switching tube Q6, which is the input terminal 5 of the balancing loop of the single battery Bm, is connected to the other output terminal BCm2 of the battery front-end detection chip, and is used for receiving the other balancing control signal BCm2 sent by the battery front-end detection chip, and the signal state of the balancing control signal BCm2 is fixed to a low level;

a grid G of the switching tube Q6 is used as an input end 3 of an equalizing loop of the single battery Bm, and is connected with an output end Am-1 of the equalizing loop of the adjacent high-phase single battery of the single battery Bm and used for receiving an equalizing control signal Am-1 sent by the equalizing loop of the adjacent high-phase single battery of the single battery Bm;

the grid G of the switching tube Q6 is also connected with the 1 st pin of the resistor R14;

for each single battery which is not connected with the positive terminal of the battery module, the adjacent single battery which is closer to the positive terminal of the battery module is defined as the adjacent single battery with high phase of the single battery;

for each single battery which is not connected with the negative end of the battery module, the adjacent single battery which is closer to the negative end of the battery module is defined as the lower adjacent single battery of the single battery.

Preferably, for the battery cell B1 connected to the positive terminal of the battery module, the equalizing loop has substantially the same structure as the equalizing loop of the battery cell Bm, except that the gate G of the switching tube Q6 as the input terminal 3 of the equalizing loop is connected to the output terminal Bn of the nth equalizing loop in the adjacent battery module in the higher position of the battery module where the equalizing loop is located.

Preferably, for the single battery Bn connected to the negative terminal of the battery module, the structure of the balancing loop is substantially the same as that of the balancing loop of the single battery Bm, except that the 2 nd pin of the resistor R11, which is used as the output terminal An of the balancing loop, is connected to the input terminal 3 of the 1 st balancing loop in the lower adjacent battery module of the battery module where the balancing loop is located.

According to the technical scheme provided by the utility model, compared with the prior art, the utility model provides a battery module equalizing circuit with priority of hardware control logic, the design science thereof, according to the theory of operation of battery front end detection chip, increases external equalizing switch and equalizing loop, reduces the current flowing through the equalizing switch integrated inside the battery front end detection chip, and controls the on and off of the external equalizing switch through the equalizing switch and the equalizing loop integrated inside the battery front end detection chip; meanwhile, by designing hardware control logic that any adjacent equalization loop can not be started, the phenomenon that the equalization switch is broken down by high voltage is avoided, the reliability of the equalization function is improved, and the method has great practical significance.

Drawings

Fig. 1 is a block diagram of a battery module equalization circuit with hardware control logic priority according to the present invention;

fig. 2 is a schematic diagram of a circuit connection between a balancing loop and an adjacent high-order cell Bm-1 in a battery module balancing circuit with hardware control logic priority, wherein the balancing loop is formed by any cell Bm of the battery module, which is not connected to the positive terminal and the negative terminal of the battery module;

fig. 3 is the utility model provides an among the prior battery module equalizer circuit of hardware control logic, the 1 st equalizer circuit that battery cell B1 has and the 2 nd equalizer circuit's that battery cell B2 has circuit connection schematic diagram, and this moment, m is 2.

Detailed Description

In order to make the technical means of the present invention easier to understand, the present application will be further described in detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the present application are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

It should be noted that in the description of the present application, the terms of direction or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, which are merely for convenience of description, and do not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.

In addition, it should be noted that, in the description of the present application, unless otherwise explicitly specified and limited, the term "mounted" and the like should be interpreted broadly, and may be, for example, either fixedly mounted or detachably mounted.

The specific meaning of the above terms in the present application can be understood by those skilled in the art as the case may be.

Referring to fig. 1 and 2, the present invention provides a battery module balancing circuit with hardware control logic priority, wherein the battery module includes a plurality of serially connected single batteries B;

the equalization circuit comprises a plurality of equalization loops 100 and a battery front end detection chip 200;

each of the single batteries B is correspondingly connected to one of the equalizing loops 100.

The battery front end detection chip 200 is connected to the plurality of equalization circuits 100.

In the present invention, in fig. 1, the battery module includes n single batteries, and n is a natural number greater than or equal to 1.

In fig. 1, n is the number of the unit cells in the battery module connected in series for the unit cells B in the battery module, and there are n balancing circuits 100 correspondingly.

n is a natural number of 2 or more, and the maximum value of n is determined according to the specification of the battery front end detection chip 200, for example, if the battery front end detection chip 200 can detect 12 strings of batteries at most, the maximum value of n is 12;

the utility model discloses in, n's numerical value is big more, explains that battery cell's position in battery module is lower more, just is close to battery module's negative pole end Bn-more, otherwise, and the position in battery module is high more, just also is close to battery module's positive terminal B + more.

It should be noted that each single battery B has one equalizing loop 100, that is, there are n single batteries and there are n equalizing loops 100; therefore, for each single battery B, the battery front-end detection chip 200 has two output terminals (a pair of output terminals) connected to the equalization loop 100 of the single battery, and is used for controlling the equalization state of the equalization loop 100, including three equalization states, namely equalization on, equalization off, and equalization invalid.

It should be noted that, the power battery system generally includes a plurality of battery modules, and specifically may include a plurality of battery modules connected in series, referring to fig. 1, the battery module Z1, the battery module Z2, and the battery module Z3 are connected in series to form a power battery system, the battery module Z2 is close to the positive terminal of the power battery system, the battery module Z3 is close to the negative terminal of the power battery system, and the battery module Z1 is located in the middle of the power battery system;

the same as the equalizing circuit in the battery module Z1 and the connection method thereof, the battery module Z2 and the battery module Z3 also respectively adopt n equalizing loops 100 to equalize n single batteries in the battery module.

Of course, the equalizing circuits and the connection modes of any plurality of battery modules of the power battery system are the same.

It should be noted that one battery front end detection chip 200 may control n equalization loops 100, and the value of n cannot exceed the maximum value specified by the battery front end detection chip 200.

In the present invention, for any battery module Z1 not connected to the positive terminal of the power battery system, the adjacent battery module (for example, battery module Z2) closer to the positive terminal of the power battery system is defined as the adjacent high-phase battery module of battery module Z1;

for any battery module Z1 that is not connected to the negative end of the power battery system, the adjacent battery module (e.g., battery module Z3) closer to the negative end of the power battery system is defined as the lower adjacent battery module of battery module Z1.

In the present invention, for each battery cell B that is not connected to the positive terminal of the battery module (e.g., not at the tail end of the battery module shown in fig. 1), the adjacent battery cell that is closer to the positive terminal B + of the battery module is defined as the adjacent battery cell of the high-phase battery cell of the battery cell B;

for each cell B not connected to the negative end B of the battery module (e.g., not at the head end of the battery module shown in fig. 1), the adjacent cell B closer to the negative end of the battery module is defined as the lower adjacent cell of the cell B.

In the present invention, for the equalization loop 100 correspondingly connected to each single battery in a battery module, an equalization loop adjacent to the equalization loop 100 and closer to the positive terminal of the battery module is defined as an adjacent equalization loop in the high phase of the equalization loop 100;

for the balancing circuit 100 correspondingly connected to each single battery in a battery module, an adjacent balancing circuit closer to the negative end of the battery module is defined as a lower adjacent balancing circuit of the balancing circuit 100.

The utility model discloses in, because equalizer circuit and the connected mode in every battery module are the same, battery module Z1, battery module Z2 and battery module Z3's equalizer circuit and connected mode are the same promptly, so only show the equalizer circuit of battery module Z1 and connected mode in fig. 1.

The utility model discloses in, to the arbitrary battery module Z1 that does not connect power battery system's positive terminal and, specifically explain below for the example that battery cell B1 (be connected battery cell of battery module positive terminal promptly) corresponds 1 st equalizing loop 100 of connecting:

in fig. 1, the 1 st equalizing loop 100 connected to the cell B1 is connected to the input terminal 1 of the cell B1, and is connected to the positive terminal B1+ of the cell B1 for receiving the voltage and current of the cell B1, so as to equalize the cell B1;

the 1 st equalizing loop 100, the input end 2 of which is connected with the negative end B1-of the battery cell B1, is used for receiving the voltage and current of the battery cell B1 and can equalize the battery cell B1;

the input end 3 of the 1 st equalizing loop 100 is connected to the output end Bn of the nth equalizing loop (i.e., the equalizing loop with the lowest position, that is, the equalizing loop closest to the negative end of the battery module) in the battery module Z2 (i.e., the battery module adjacent to the high position of the battery module Z1 where the equalizing loop is located), and is configured to receive the equalizing control signal Bn output by the nth equalizing loop in the battery module Z2 (i.e., the battery module adjacent to the high position of the battery module Z1), where the control signal may control the equalizing state of the 1 st equalizing loop 100 in the battery module Z1;

the input end 4 of the 1 st equalizing loop 100 is connected to an output end BC11 of the battery front-end detecting chip 200, and is configured to receive an equalizing control signal BC11 sent by the battery front-end detecting chip 200 to the equalizing loop 100, and is configured to control the opening and closing of the equalizing loop 100;

the input end 5 of the 1 st equalizing loop 100 is connected to the other output end BC12 of the battery front-end detecting chip 200, and is configured to receive another equalizing control signal BC12 sent by the battery front-end detecting chip 200 to the equalizing loop 100, and is configured to control the on and off of the equalizing loop 100;

the output end a1 of the 1 st equalization loop 100 is connected to the input end 3 of the 2 nd equalization loop 100 (i.e., the lower adjacent equalization loop of the present equalization loop 100), and is used for outputting an equalization control signal a1 to the 2 nd equalization loop 100 (i.e., the lower adjacent equalization loop of the present equalization loop 100), and the start and stop of the 2 nd equalization loop 100 (i.e., the lower adjacent equalization loop) are controlled by the equalization control signal a 1.

In the present invention, similarly, for any one of the battery modules, the structure of the equalizing loop 100 (i.e. the mth equalizing loop 100, m is any natural number greater than or equal to 2 and less than n, n is the number of the series-connected battery cells in the battery module) of any one of the battery cells Bm (i.e. the battery cell located in the middle) which is not connected to the positive terminal and the negative terminal of the battery module is the same, and the input terminal 1 thereof is connected to the positive terminal Bm + of the corresponding battery cell Bm respectively for receiving the voltage and the current of the battery cell B, and balancing the battery cell Bm;

the input end 2 of the mth equalizing loop 100 (i.e., the equalizing loop 100 of the single battery Bm) is respectively connected to the negative electrode end Bm-of the corresponding single battery Bm, and is configured to receive the voltage and current of the single battery Bm and balance the single battery Bm;

an input end 3 of the mth equalization loop 100 is connected to an output end Am-1 of the (m-1) th equalization loop (i.e., an upper adjacent equalization loop of the present equalization loop 100), and is configured to receive an equalization control signal Am-1 output by the (m-1) th equalization loop (i.e., an upper adjacent equalization loop of the present equalization loop 100), where the control signal may control an equalization state of the mth equalization loop 100;

the input end 4 of the mth equalization loop 100 is connected to one output end BCm1 of the battery front-end detection chip 200, and is configured to receive the equalization control signal BCm1 sent by the battery front-end detection chip 200 to the mth equalization loop 100, where the equalization control signal BCm1 is configured to control the opening and closing of the mth equalization loop;

the input end 5 of the mth equalization loop 100 is connected to the other output end BCn2 of the battery front-end detection chip 200, and is configured to receive another equalization control signal BCn2 sent by the battery front-end detection chip 200 to the mth equalization loop 100, where the equalization control signal BCn2 is configured to control the opening and closing of the mth equalization loop;

an output end Am of the mth equalization loop 100 is connected to an input end 3 of the (m + 1) th equalization loop 100 (i.e., a lower adjacent equalization loop of the present equalization loop 100), and is configured to output an equalization control signal Am to the (m + 1) th equalization loop 100, where the equalization control signal Am is used to control the (m + 1) th equalization loop 100 to be turned on and off.

The utility model discloses in, in the concrete realization, to the arbitrary battery module Z1 that does not connect power battery system's positive terminal and, the corresponding nth equalization loop 100 who connects of the battery cell Bn (be the battery cell who connects battery module negative terminal promptly) in it specifically explains for the example:

in fig. 1, the nth equalizing loop 100 correspondingly connected to the cell Bn has an input terminal 1 connected to the positive terminal Bn + of the cell Bn for receiving the voltage and current of the cell Bn, so as to equalize the cell Bn;

the input end 2 of the nth equalizing loop 100 is connected with the negative electrode end Bn-of the single battery Bn, and is used for receiving the voltage and current of the single battery Bn and equalizing the single battery Bn;

an nth equalization loop 100, the input end 3 of which is connected to the output end An-1 of the (n-1) th equalization loop (the lower adjacent equalization loop of the present equalization loop 100), for receiving the equalization control signal An-1 output by the (n-1) th equalization loop, wherein the control signal can control the equalization state of the nth equalization loop 100;

an nth equalization loop 100, having an input terminal 4 connected to an output terminal BCn1 of the battery front-end detection chip 200, for receiving an equalization control signal BCn1 sent by the battery front-end detection chip 200 to the present equalization loop 100, and for controlling the start and stop of the present equalization loop 100;

an nth equalization loop 100, an input terminal 5 of which is connected to another output terminal BCn2 of the battery front-end detection chip 200, for receiving another equalization control signal BCn2 sent by the battery front-end detection chip 200 to the present equalization loop 100, and for controlling the start and stop of the present equalization loop 100;

the output end An of the nth equalization loop 100 is connected to the input end 3 of the 1 st equalization loop (i.e., the highest equalization loop, that is, the equalization loop closest to the positive terminal of the battery module, that is, the equalization loop connected to the B1 in the battery module) in the battery module Z3 (i.e., the lower adjacent battery module of the battery module Z1 in which the present equalization loop is located), and is configured to output An equalization control signal An to the 1 st equalization loop in the battery module Z3 (i.e., the lower adjacent battery module of the battery module Z1), where the control signal is used to control the start and stop of the 1 st equalization loop in the battery module Z3.

In the present invention, in the implementation, for the 1 st equalizing loop 100 (i.e. in the battery module Z1, the equalizing loop 100 correspondingly connected to the battery cell B1 connected to the positive terminal of the battery module), the battery front end detecting chip 200, the output end BC11 thereof is connected to the input end 4 of the 1 st equalizing loop 100, and is used for sending the equalizing control signal BC11, and is used for controlling the opening and closing of the 1 st equalizing loop 100 corresponding to the battery cell B1;

the battery front end detection chip 200 has an output end BC12 connected to the input end 5 of the 1 st equalization loop 100, and is configured to send an equalization control signal BC12 for controlling the start and stop of the 1 st equalization loop 100 corresponding to the battery cell B1;

in the implementation, similarly, for the mth equalization loop 100, the output end BCm1 of the battery front-end detection chip 200 is connected to the input end 4 of the mth equalization loop 100, and is configured to send an equalization control signal BCm1 for controlling the opening and closing of the mth equalization loop 100 corresponding to the cell Bm;

for the mth equalizing loop 100, the output end BCm2 of the battery front end detecting chip 200 is connected to the input end 5 of the mth equalizing loop 100, and is configured to send an equalizing control signal BCm2 for controlling the on and off of the mth equalizing loop 100 corresponding to the battery cell Bm.

In the implementation, similarly, for the nth equalization loop 100, the output end BCn1 of the battery front end detection chip 200 is connected to the input end 4 of the nth equalization loop 100, and is configured to send an equalization control signal BCn1 for controlling the on and off of the nth equalization loop 100 corresponding to the cell Bn;

for the nth equalizing loop 100, the output end BCn2 of the battery front end detecting chip 200 is connected to the input end 5 of the nth equalizing loop 100, and is configured to send an equalizing control signal BCn2 for controlling the on and off of the nth equalizing loop 100 corresponding to the battery cell Bn.

It should be noted that the battery front end detection chip 200 is an integrated chip with an internal equalization switch, and internally controls the on/off of the equalization switch.

It should be noted that the utility model discloses in, the electric current that flows in the inside integrated equalizer switch of battery front end detection chip 200, not equalizing current, its current value is less than equalizing current far away, has greatly reduced battery front end detection chip 200's calorific capacity to battery front end detection chip 200's failure rate has been reduced.

The utility model discloses in, the hardware control logic to be realized is that any two adjacent equalization loops 100 can not be opened simultaneously, and the equalization priority of the equalization loop 100 with the sequence number n-1(n is a natural number more than or equal to 2) in any two adjacent equalization loops 100 is higher than the equalization priority of the equalization loop 100 with the sequence number n (that is, the closer to the equalization loop 100 at the negative end of the battery module, the higher the priority is), if the n-1 equalization loop 100 is opened for equalization, the nth equalization loop 100 is controlled to stop equalization or can not be opened for equalization;

that is, referring to fig. 1, for the equalization circuit of the battery module Z1, which has the equalization priority of the 1 st equalization loop higher than the equalization priority of the 2 nd equalization loop 100, the 1 st equalization loop 100 will control the 2 nd equalization loop 100 to stop equalization or fail to start equalization while equalization is started;

similarly, the equalization priority of the 2 nd equalization loop is higher than that of the 3 rd equalization loop 100, and when the 2 nd equalization loop 100 starts equalization, the 3 rd equalization loop 100 is controlled to stop equalization or cannot start equalization;

in this way, the equalization priority of the (n-1) th equalization loop is higher than that of the (n) th equalization loop 100, and the (n-1) th equalization loop 100 is controlled to stop equalization or not start equalization while the equalization loop 100 starts equalization.

It should be noted that the equalization states of two non-adjacent equalization loops 100 do not affect each other, for example, while the 1 st equalization loop 100 is turned on, the 3 rd equalization loop 100 may also be turned on.

It should be noted that, referring to fig. 1, the nth equalizing loop (i.e., the equalizing loop closest to the negative terminal of the battery module) in the battery module Z2 and the 1 st equalizing loop 100 (i.e., the equalizing loop closest to the positive terminal of the battery module) in the battery module Z1 must be adjacent to each other, and the battery module Z2 as the higher adjacent battery module has a higher equalizing priority than the 1 st equalizing loop 100 in the battery module Z1.

It should be noted that, referring to fig. 1, the 1 st equalization loop in the battery module Z3 (i.e., the equalization loop closest to the positive terminal of the battery module) and the nth equalization loop 100 in the battery module Z1 (i.e., the equalization loop closest to the negative terminal of the battery module) must be adjacent to each other, and the equalization priority of the nth equalization loop in the battery module Z1 is higher than that of the 1 st equalization loop 100 in the battery module Z3.

The utility model discloses in, to every battery module Z1, the equilibrium state of every equalizing loop 100 wherein is the same, including balanced three kinds of equilibrium states such as ending, balanced opening and balanced ineffectiveness, use 1

st equalizing loop

100, 2 nd equalizing loop 100 and the nth equalizing loop as the example below, do concrete explanation:

for the 1 st equalization loop 100:

1, equilibrium cut-off: the equalization control signal Bn sent by the nth equalization loop 100 in the high-phase adjacent battery module Z2 is at a high level, the equalization control signal BC11 output by the battery front-end detection chip 200 is at a high level, the equalization control signal BC12 output by the battery front-end detection chip 200 is at a low level, the output end a1 of the 1 st equalization loop 100 is at a high level, the 1 st equalization loop 100 is in an equalization cutoff state, at this time, the single battery B1 is not equalized, and no equalization current flows through the 1 st equalization loop 100;

2, balance starting: the equalization control signal Bn sent by the nth equalization loop 100 in the high-phase adjacent battery module Z2 is at a high level, the equalization control signal BC11 output by the battery front-end detection chip 200 is at a low level, the equalization control signal BC12 is at a low level, the output end a1 of the 1 st equalization loop 100 is at a low level, the 1 st equalization loop 100 is in an equalization on state, at this time, the single battery B1 is equalized, and an equalization current flows through the 1 st equalization loop 100;

3, equalization is invalid: the equalization control signal Bn sent by the nth equalization loop 100 in the high-phase adjacent battery module Z2 is at a low level, the equalization control signal BC11 output by the battery front-end detection chip 200 is at a high level, the equalization control signal BC12 is at a high level, the output end a1 of the 1 st equalization loop 100 is at a high level, the 1 st equalization loop 100 is in an equalization invalid state, no equalization is performed on the battery cell B1 at this time, and no equalization current flows through the 1 st equalization loop 100;

for the 2 nd equalization loop 100:

1, equilibrium cut-off: the equalization control signal a1 output by the 1 st equalization loop 100 is at a high level, the equalization control signal BC21 output by the battery front-end detection chip 200 is at a high level, the equalization control signal BC22 is at a low level, the output end a2 of the 2 nd equalization loop 100 is at a high level, the 2 nd equalization loop 100 is in an equalization cutoff state, no equalization is performed on the battery cell B2 at this time, and no equalization current flows through the 2 nd equalization loop 100;

2, balance starting: the equalization control signal a1 output by the 1 st equalization loop 100 is at a high level, the equalization control signal BC21 output by the battery front-end detection chip 200 is at a low level, the equalization control signal BC22 is at a low level, the output end a2 of the 2 nd equalization loop 100 is at a low level, the 2 nd equalization loop 100 is in an equalization open state, at this time, the single battery B2 is equalized, and an equalization current flows through the 2 nd equalization loop 100;

3, equalization is invalid: the equalization control signal a1 output by the 1 st equalization loop 100 is at a low level, the equalization control signal BC21 output by the battery front-end detection chip 200 is at a high level, the equalization control signal BC22 is at a high level, the output end a2 of the 2 nd equalization loop 100 is at a high level, the 2 nd equalization loop 100 is in an equalization invalid state, no equalization is performed on the battery cell B2 at this time, and no equalization current flows through the 2 nd equalization loop 100;

for the mth equalization loop 100:

1, equilibrium cut-off: the equalization control signal Am-1 output by the m-1 th equalization loop 100 is at a high level, the equalization control signal BCm1 is at a high level, the equalization control signal BCm2 is at a low level, the output Am of the m-1 th equalization loop 100 is at a high level, the equalization loop 100 is in an equalization cut-off state, at this time, the single battery Bm is not equalized, and no equalization current flows through the equalization loop 100;

2, balance starting: the equalization control signals Am-1 output by the m-1 equalization loops 100 are high level, the equalization control signals BCm1 are low level, the equalization control signals BCm2 are low level, the output end Am of the mth equalization loop 100 is low level, the equalization loop 100 is in an equalization opening state, at the moment, the single batteries Bm are equalized, and equalization current flows through the equalization loop 100;

3, equalization is invalid: the equalization control signal Am-1 output by the m-1 equalization loops 100 is at a low level, the equalization control signal BCm1 is at a high level, the equalization control signal BCm2 is at a high level, the output Am of the mth equalization loop 100 is at a high level, the equalization loop 100 is in an equalization invalid state, at this time, the single battery Bm is not equalized, and no equalization current flows through the equalization loop 100;

for the nth equalization loop 100:

1, equilibrium cut-off: the equalization control signal Bn-1 sent from the nth equalization loop 100 is at a high level, the equalization control signal BCn1 output by the battery front-end detection chip 200 is at a high level, the equalization control signal BCn2 output by the battery front-end detection chip 200 is at a low level, the output An of the nth equalization loop 100 is at a high level, the nth equalization loop 100 is in An equalization cutoff state, at this time, the cell Bn is not equalized, and no equalization current flows through the nth equalization loop 100;

2, balance starting: the equalization control signal Bn-1 sent from the nth equalization loop 100 is at a high level, the equalization control signal BCn1 output by the battery front-end detection chip 200 is at a low level, the equalization control signal BCn2 is at a low level, the output end An of the nth equalization loop 100 is at a low level, the nth equalization loop 100 is in An equalization on state, at this time, the battery cell Bn is equalized, and An equalization current flows through the nth equalization loop 100;

3, equalization is invalid: the equalization control signal Bn-1 sent from the nth equalization loop 100 is at a low level, the equalization control signal BCn1 output by the battery front-end detection chip 200 is at a high level, the equalization control signal BCn2 is at a high level, the output end An of the nth equalization loop 100 is at a high level, the nth equalization loop 100 is in An equalization disabled state, no equalization is performed on the battery cell Bn at this time, and no equalization current flows through the nth equalization loop 100.

In the present invention, the operation principle of each equalizing loop 100 is the same, and as shown in fig. 1, the 1 st equalizing circuit 100 and the 2 nd equalizing loop 100 in the battery module Z1 are specifically explained below:

firstly, balance cutoff: since the equalizing priority of the nth equalizing loop in the battery module Z2 (i.e., the adjacent battery module Z2 in the high position of the battery module Z1) is higher than the equalizing priority of the 1 st equalizing loop in the battery module Z1, if the nth equalizing loop is in the equalizing stop state at this time, the output end Bn is at the high level;

when the output end BC11 of the battery front-end detection chip 200 is at a high level and the output end BC12 is at a low level, the 1 st equalizing loop 100 is in an equalizing cut-off state, and cannot equalize the battery cell B1, that is, no equalizing current flows into the equalizing loop 100, and at this time, the output end a1 of the 1 st equalizing loop 100 is at a high level;

the equalization control signal Bn at a high level, the equalization control signal BC11 at a high level, and the equalization control signal BC12 at a low level put the 1 st equalization loop in an equalization off state.

It should be noted that, since the equalization priority of the 1 st equalization loop 100 is higher than the equalization priority of the 2 nd equalization loop 100, and the 1 st equalization loop 100 is in the equalization off state, the output of the equalization control signal a1 with a high level enables the 2 nd equalization loop 100 to start equalization.

Secondly, balanced opening: because the balancing priority of the nth balancing loop in the battery module Z2 (as an adjacent battery module in a high position) is higher than the balancing priority of the 1 st balancing loop in the battery module Z1, if the nth balancing loop is in a balancing cut-off state at the moment, the output end Bn is at a high level, so that the adjacent 1 st balancing loop 100 can start balancing;

when the output end BC11 of the battery front-end detection chip 200 is at a low level and the output end BC12 is at a low level, the 1 st equalization loop 100 is in an equalization open state, so that the single battery B1 can be equalized, an equalization current flows into the equalization loop 100, and at this time, the output end a1 of the 1 st equalization loop 100 is at a low level;

the equalization control signal Bn of high level, the equalization control signal BC11 of low level, and the equalization control signal BC12 of low level put the 1 st equalization loop in an equalization on state.

It should be noted that, since the equalization priority of the 1 st equalization loop 100 is higher than the equalization priority of the 2 nd equalization loop 100, and the 1 st equalization loop 100 is in the equalization on state, the output of the equalization control signal a1 with low level controls the 2 nd equalization loop 100 to stop equalization or not to start equalization.

When the 1 st equalizing loop 100 is in the equalizing-on state, the currents flowing through the output terminals BC11 and BC12 of the battery front-end detecting chip 200 are not equalizing currents, and the current value thereof is much smaller than the equalizing currents, so as to reduce the heat generation amount of the battery front-end detecting chip 200.

Thirdly, balance invalidation: because the equalization priority of the nth equalization loop in the battery module Z2 is higher than the equalization priority of the 1 st equalization loop in the battery module Z1, if the nth equalization loop is in an equalization cutoff state at this time, the output end Bn is at a high level, so that the adjacent 1 st equalization loop 100 can start equalization;

since the equalization priority of the 1 st equalization loop 100 is higher than that of the 2 nd equalization loop 100, when the 1 st equalization loop 100 is in an equalization on state, the output end a1 thereof is at a low level, and the 2 nd equalization loop 100 is controlled to stop equalization or cannot start equalization, so that the 2 nd equalization loop 100 cannot equalize the cell B2;

under this condition, the state of the 2 nd equalization loop 100 is an equalization disabled state, and at this time, the battery front end detection chip 200 internally sends out the control signal for controlling the output terminal BC21 to be at the low level (when BC21 is at the low level, equalization is turned on), but the low level equalization control signal a1 output by the 1 st equalization loop with the higher equalization priority causes the 2 nd equalization loop 100 to stop equalization or fail to start equalization, so the 2 nd equalization loop 100 is in the equalization disabled state.

In the present invention, the operating principle and the circuit structure of each equalizing loop 100 are the same for the power battery system.

Referring to fig. 2, in the power battery system, taking an equalizing loop of any battery cell Bm in the battery module Z1 and an equalizing loop 100 of a battery cell Bm-1 as an example, the operating principle and the implemented control logic are specifically explained for any battery module Z1 not connected to the positive terminal and the negative terminal of the power battery system.

Referring to fig. 2, the balancing circuit 100 of any one of the unit batteries Bm of the battery module, which is not connected to the positive terminal and the negative terminal of the battery module, includes a balancing resistor RB, a balancing switch QB, resistors R1 to R14, a capacitor C1, switching tubes Q1 to Q6, and a diode D1, wherein:

the 1 st pin of the balancing resistor RB, which is an input terminal 1 of a balancing loop 100 (i.e., the mth balancing loop 100) of the single battery Bm, is connected to the positive terminal Bm + of the single battery Bm and is configured to receive the voltage and the balancing current of the single battery Bm;

the 2 nd pin of the balance resistor RB is connected with the T4 end;

it should be noted that the required balance current is obtained by adjusting the resistance value of the balance resistor RB;

the source S of the balancing switch QB is used as the input end 2 of the balancing loop 100 of the single battery Bm, is connected with the negative electrode end Bm-of the single battery Bm, and is used for receiving the voltage and the balancing current of the single battery Bm;

source S of equalization switch QB, also connected to the cathode of diode D1;

the grid G of the equalizing switch QB is connected with the T3 end;

an emitter E of the switching tube Q4 connected to an anode of the diode D1;

an emitter E of the switching tube Q5, which is used as an input terminal 1 of the equalization loop 100 provided in the cell Bm, is further connected to the positive terminal Bm of the cell Bm, the 1 st pin of the resistor R9, and the 1 st pin of the resistor R1, respectively, and is configured to receive the voltage and the current of the cell Bm;

the 2 nd pin of the resistor R11, which is the output end Am of the balancing loop 100 provided by the battery cell Bm, is respectively connected to the 1 st pin of the resistor R14 and the gate G (i.e., the input end 3) of the switching tube Q6 in the balancing loop 100 (i.e., the m +1 st balancing loop 100) of the battery cell Bm +1 (i.e., the lower adjacent battery cell of the battery cell Bm), and is used for outputting a balancing control signal Am to control the on and off of the switching tube Q6 in the balancing loop 100 (i.e., the m +1 st balancing loop 100) of the battery cell Bm + 1;

the 2 nd pin of the resistor R6 is connected with the T1 end;

the 2 nd pin of the resistor R2 is connected with the T2 end;

a pin 2 of the resistor R4, which is an input terminal 4 of the balancing loop 100 of the battery cell Bm, is connected to an output terminal BCm1 of the battery front-end detecting chip 200, and is configured to receive a balancing control signal BCm1 sent by the battery front-end detecting chip 200, where the signal states include a high level and a low level;

the drain D of the switching tube Q6, which is the input terminal 5 of the balancing loop 100 of the single battery Bm, is connected to the other output terminal BCm2 of the battery front-end detecting chip 200, and is used for receiving the other balancing control signal BCm2 sent by the battery front-end detecting chip 200, and the signal state of the balancing control signal BCm2 is fixed to a low level;

a gate G of the switching tube Q6, which is used as the input end 3 of the equalizing loop 100 of the single battery Bm, is connected to the output end Am-1 of the equalizing loop 100 of the adjacent high-order single battery of the single battery Bm, and is used for receiving an equalizing control signal Am-1 sent by the equalizing loop 100 of the adjacent high-order single battery of the single battery Bm, and the signal can control the on and off of the switching tube Q6;

it should be noted that the difference between the 1 st equalization loop 100 and the 2 nd equalization loop 100 is: the input end 3 of the 1 st equalizing loop 100 is connected with the output end Bn (see fig. 1) of the nth equalizing loop in the battery module Z2, and the input end 3 of the 2 nd equalizing loop 100 is connected with the output end a1 of the 1 st equalizing loop 100; similarly, input 3 of the 3 rd equalization loop 100 is connected to output a2 of the 2 nd equalization loop 100, and so on, and input 3 of the nth equalization loop 100 is connected to output An-1 of the (n-1) th equalization loop 100 (see fig. 1).

In the present invention, in the concrete implementation, for the battery cell B1 connected to the positive terminal of the battery module Z1, the equalizing loop 100 is the same as the equalizing loop 100 of the battery cell Bm, and only the gate G of the switch Q6 as the input terminal 3 of the equalizing loop 100 is connected to the output Bn (output equalizing control signal Bn) of the nth equalizing loop 100 (i.e. the equalizing loop located at the lowest position and closest to the negative terminal of the battery module) in the battery module Z2 (the adjacent battery module in the high-phase of the battery module Z1 where the equalizing loop is located);

for the battery module connected with the positive end of the power battery system (i.e. the highest battery module), the structure of each equalization loop is the same as that of each equalization loop in the battery module Z1 except for the 1 st equalization loop of the highest single battery (close to the positive end of the battery module) in the highest battery module (close to the positive end of the power battery system).

For the 1 st equalizing loop of the highest battery module (i.e. the equalizing loop with the battery cell B1), a resistor R15 is welded between the gate G of the switching tube G6 and the 1 st pin of the resistor R1.

The utility model discloses in, specifically realize, to the battery cell Bn of connecting battery module Z1 negative pole end, its equalizing loop 100 is the same with the equalizing loop 100's of battery cell Bm structure, just as the 2 nd pin of resistance R11 of equalizing loop 100's output An, what connect is the input 3 of the 1 st equalizing loop (the position is the highest, is closest to the equalizing loop of the battery module positive terminal of place promptly) in the battery module Z3 (the adjacent battery module of low phase of this equalizing loop place battery module Z1).

Note that, the 1 st equalizing loop in the battery module Z3 has the same configuration as the equalizing loop 100 of the battery cell Bm, and the output terminal a1 connected to the 2 nd pin of the resistor R11 is connected to the 1 st pin of the resistor R14 in the 2 nd equalizing loop in the battery module Z3.

Note that the welding resistor R15 is not required for all the equalization loops in the battery module Z3.

In the present invention, referring to fig. 2, the operation principle and the implemented control logic of the equalization loop 100 are as follows:

in the present invention, in the specific implementation, referring to fig. 2, the equalization state of each equalization loop 100 has three kinds:

1, equilibrium cut-off: the switching tube Q6 is turned on, the equalizing start signal BCm1 is at a high level, the equalizing switch QB is turned off, and no equalizing current flows;

2, balance starting: the switching tube Q6 is conducted, the equalizing starting signal BCm1 is at a low level, the equalizing switch QB is conducted, and equalizing current exists;

3, equalization is invalid: the switching tube Q6 is cut off, the equalization starting signal BCm1 is invalid, the equalization switch QB is cut off, and no equalization current exists;

in the present invention, in the specific implementation, the working principle of each equalizing loop 100 is the same, and the equalizing state is also the same, as shown in fig. 3, so that the working principle is specifically explained by taking the 1 st equalizing loop and the 2 nd equalizing loop as an example:

firstly, balance cutoff: for the 2 nd equalizing loop, when the equalizing control signal BC21 output by the output end BC11 of the battery front-end detecting chip 200 is at a high level and the equalizing control signal a1 output by the output end a1 of the 1 st equalizing loop is at a high level, the terminals T1 and T2 both maintain at the high level after voltage division by the resistors R1 to R3, the high-level T2 turns on the switching tube Q1 first, and then under the time delay action of the capacitor C1, the high-level T1 turns on the switching tubes Q2 and Q3 again; the turned-on switch tube Q1 enables the end T3 to be at a low level, so that the equalizing switch QB is turned off, and at the moment, no equalizing current exists in the equalizing resistor RB and the equalizing switch QB, and the single battery B2 cannot be equalized; the switch Q6 is kept in a conducting state by a high level a1, the output terminal BC22 of the battery front end detection chip 200 is connected to the negative terminal B1-of the battery cell B1 through the diode D1, and the terminal BC22 is pulled down to a low level state.

A high BC21 and a high A1 to make the 2 nd equalizing loop in an equalizing cut-off state;

because the equalizing switch QB in the 2 nd equalizing loop is turned off, the terminal T4 is at a high level, the voltage value of the terminal T is equal to the voltage of the cell B2, and the switching tubes Q4 and Q5 are turned on, so that the output terminal a2 of the 2 nd equalizing loop is at a high level, the voltage value of the output terminal a2 of the 2 nd equalizing loop is equal to the voltage of the cell B2, and the switching tube Q6 in the 3 rd equalizing loop can be turned on;

it should be noted that when the output BC11 of the battery front-end detecting chip 200 is at a high level, it indicates that the equalization switch integrated inside the battery front-end detecting chip 200 is in an off state.

It should be noted that the output terminal a1 of the 1 st equalization loop is at a high level, which indicates that the equalization switch QB in the 1 st equalization loop is turned off, no equalization current flows, and is in an equalization off state or an equalization inactive state, and the principle thereof is the same as that of the output terminal a2 of the 2 nd equalization loop being at a high level.

Secondly, balanced opening: for the 2 nd equalizing loop, when the equalizing control signal BC21 output by the output terminal BC21 of the battery front-end detecting chip 200 is at a low level and the equalizing control signal a1 output by the output terminal a1 of the 1 st equalizing loop is at a high level, the BC21 terminal and the BC22 terminal are turned on inside the battery front-end detecting chip 200 at this time, and the T2 terminal is pulled down to a low level by the parallel-connected resistor R4, so that the switching tube Q1 is turned off from on; however, the terminal T1 is still kept at a high level through the voltage dividing action of the resistor R1, the resistor R2 and the resistor R4, the switching tubes Q2 and Q3 are kept on, and the terminal T3 is changed from a low level to a high level through the voltage dividing action of the resistor R9 and the resistor R10, so that the balancing switch QB is turned on, and at this time, balancing current flows through the balancing resistor RB and the balancing switch QB, and balancing of the battery cell B2 is started;

the high BC21 and the high A1 make the 2 nd equalizing loop in an equalizing opening state;

since the equalizing switch QB in the 2 nd equalizing loop is turned on, and the terminal T4 is pulled down to the negative terminal B1 "of the battery cell, the terminal T4 is changed from high level to low level, so that the switching tubes Q4 and Q5 are changed from on to off, and therefore the output terminal a2 of the 2 nd equalizing loop is also changed from high level to low level, so that the switching tube Q6 in the 3 rd equalizing loop is changed from on to off;

it should be noted that when the output BC21 of the battery front-end detecting chip 200 is at a low level, it indicates that the equalization switch integrated inside the battery front-end detecting chip 200 is in a conducting state.

It should be noted that, when the output end BC21 of the battery front-end detection chip 200 is at a low level, the current flowing through the output end BC21 is not an equalizing current, and the current value is much smaller than the value of the equalizing current, so that the heat generation amount of the battery front-end detection chip 200 is greatly reduced, and the failure rate of the battery front-end detection chip 200 is reduced;

it should be noted that, by adjusting the sizes of the resistor R1, the resistor R2, and the resistor R4, the current value flowing through the output BC21 of the battery front end detecting chip 200 is adjusted to ensure that the battery front end detecting chip 200 can normally operate, and the range of the current value can be obtained from the specification of the battery front end detecting chip 200;

it should be noted that the resistance of the resistor R4 is much smaller than that of the resistor R3, so as to ensure that the T2 can reliably cut off the switch Q1.

It should be noted that the principle of the 1 st equalizing loop output terminal a1 being at a high level indicates that the 1 st equalizing loop equalizing switch QB is turned off, no equalizing current flows, and is in an equalizing off state or an equalizing inactive state, which is the same as the principle of the 2 nd equalizing loop output terminal a2 being at a high level.

The balance cut-off and balance open states of the 1 st balance loop and the 2 nd balance loop need to satisfy the following conditions:

any two adjacent equalization loops cannot be started at the same time, the equalization priority of the equalization loop with the sequence number m-1 in any two adjacent equalization loops is higher than that of the equalization loop with the sequence number m, and if the m-1 th equalization loop 100 starts equalization, the mth equalization loop 100 is controlled to stop equalization or cannot start equalization;

in this embodiment, the equalization priority of the 1 st equalization loop is higher than the equalization priority of the 2 nd equalization loop, and when the 1 st equalization loop starts equalization, the 2 nd equalization loop is controlled to stop equalization or cannot start equalization, that is, only when the 1 st equalization loop is cut off, the 2 nd equalization loop can start equalization;

similarly, the equalization priority of the 2 nd equalization loop is higher than that of the 3 rd equalization loop, and the 3 rd equalization loop can be started only when the 2 nd equalization loop is cut off;

in analogy, the balance priority of the (m-1) th balance loop is higher than that of the (m) th balance loop, and the (m) th balance loop can be opened only when the (m-1) th balance loop is cut off;

the equalizing priority of the nth equalizing loop is higher than that of the nth equalizing loop.

Thirdly, balance invalidation: when the 1 st equalization loop is in an off state and the 2 nd equalization loop is in an equalization on state, the equalization control signal BC11 input by the 1 st equalization loop is at a high level, the equalization control signal BC12 is at a low level, the equalization control signal Bn is at a high level, the equalization control signal a1 output by the 1 st equalization loop is at a high level, the equalization control signals BC21 and BC22 input by the 2 nd equalization loop are both at a low level, and the equalization control signal a2 output by the 2 nd equalization loop is at a low level;

if the 1 st equalization loop is changed from equalization cutoff to equalization on, the equalization priority of the 1 st equalization loop is higher than that of the 2 nd equalization loop, and then the 2 nd equalization loop stops the equalization of the battery cell B2 under the control of the 1 st equalization loop;

that is, when the equalization control signal BC11 input to the 1 st equalization loop is changed from high level to low level, the terminal T2 is changed from high level to low level, the switch tube Q1 is changed from on to off, the T1 keeping high level unchanged continues to turn on the switch tubes Q2 and Q3, the terminal T3 is changed from low level to high level, the equalization switch QB is changed from off to on, the equalization of the battery cell B1 is started, at the same time, the terminal T4 is changed from high level to low level, the switch tubes Q4 and Q5 are changed from on to off, then the terminal a1 of the 1 st equalization loop is changed from high level to low level, the switch tube Q6 in the 2 nd equalization loop is changed from on to off, at this time, the equalization control signals BC21 and BC22 input to the 2 nd equalization loop are changed from low level to high level, the terminal T2 is changed from low level to high level, the switch tube Q1 is turned on, so that the equalization switch tube Q22 is changed from on to off, stopping the equalization of the unit cell B2;

under this condition, the state of the 2 nd equalizing loop is an equalizing invalid state, because at this time, although the equalizing control signals BC21 and BC22 input by the 2 nd equalizing loop are both high level, and the 2 nd equalizing loop is in an off state, the control signal state of the output terminal BC21 of the battery front end detecting chip 200 is still in a low level inside, the equalizing control signal a1 output by the 1 st equalizing loop turns off the switching tube Q6, the connection between the output terminal BC22 of the battery front end detecting chip 200 and the negative terminal B2-of the battery cell B2 is disconnected, the resistor R4 pulls up the output terminal BC21 and the output terminal BC22 to high level, so that the control signal of the output terminal BC21 inside the battery front end detecting chip 200 is in an invalid state, and therefore, the 2 nd equalizing loop is changed from an equalizing on state to an equalizing invalid state, the balancing of the unit cell B2 cannot be continued.

It should be noted that when the output BC21 of the battery front-end detecting chip 200 is at a high level, it indicates that the equalization switch integrated inside the battery front-end detecting chip 200 is in an off state.

It should be noted that the nth equalization loop output end Bn of the battery module Z2 is at a high level, which indicates that the nth equalization loop is in an equalization off state or an equalization invalid state, and the principle of the nth equalization loop output end Bn is at a high level in the same manner as the principle of the 2 nd equalization loop output end a2 in fig. 2; the 1 st equalization loop in fig. 3 can only start equalization if the nth equalization loop is in an equalization off state or an equalization inactive state.

It should be noted that, referring to fig. 2, for the resistor R15 in the 1 st equalizing loop (i.e. the equalizing loop of the battery cell B1 connected to the positive terminal of the battery module) in one battery module, in practical application, if the 1 st equalizing loop has no equalizing control signal Bn access (i.e. it is the battery module close to the highest position of the positive terminal of the power battery system), then another resistor R15 needs to be welded, specifically: in the 1 st equalizing loop, a resistor R15 is welded between the grid G of the switching tube G6 and the 1 st pin of the resistor R1 and is used for controlling the conduction of the switching tube Q6 in the 1 st equalizing loop; however, the welding resistance R15 is not present in any of the 2 nd to nth equalizing circuits. That is to say, the technical scheme of the utility model among, when a plurality of modules establish ties into power battery system, except the 1 st equalizing loop of the highest position battery cell (being close to the positive terminal of battery module) among the battery module of highest position (being close to the positive terminal of power battery system), other battery cell B's in the battery module equalizing loop structure all the same, this 1 special equalizing loop is with the difference in other equalizing loops: the weld resistance R15 is required, while the other equalization loops do not require the weld resistance R15.

It should be noted that, in the present invention, in the specific implementation, the battery front end detecting chip 200 can be applied to the currently commonly used brand, series and model in the BMS technical solution, such as the MC33771 battery controller integrated circuit chip of NXP (engzhipu). The model and the internal working principle and the control logic of the battery front end detection chip are not in the protection scope of the utility model.

Compared with the prior art, the utility model provides a preferential battery module equalizer circuit of hardware control logic has following beneficial effect:

1. the equalizing circuit of the utility model is added with the external equalizing switch, which can obtain the required equalizing current without being limited by the specification of the integrated chip;

2. the utility model can prolong the conduction time of the external equalization switch and improve the equalization effect;

3. in addition, the utility model changes the equalizing switch integrated in the battery front end detection chip into the control switch, thereby reducing the current flowing through the equalizing switch integrated in the battery front end detection chip, greatly reducing the heat productivity of the integrated chip and improving the reliability of the integrated chip;

4. the utility model avoids the phenomenon that the balance switch is broken down by high voltage through the control logic that any two adjacent balance loops can not be opened simultaneously, and further improves the reliability of the balance function;

5. for the technical scheme of the utility model, the hardware circuit design is scientific, the electronic components are of universal application models, the model selection is easy, and the components are low in price;

6. because the utility model discloses a hardware circuit consumption is lower, so can adopt the surface mounted type miniwatt electronic components, therefore circuit board occupation space is little, has greatly reduced material cost. Therefore, the technical scheme of the utility model has very strong practical value and market spreading value.

In conclusion, compared with the prior art, the utility model provides a battery module equalization circuit with priority of hardware control logic, its design science, according to the theory of operation of battery front end detection chip, increases external equalization switch and equalization loop, reduces the electric current that flows through the equalization switch of battery front end detection chip internal integration to through the equalization switch and the equalization loop of battery front end detection chip internal integration, control external equalization switch's switching on and off; meanwhile, by designing hardware control logic that any adjacent equalization loop can not be started, the phenomenon that the equalization switch is broken down by high voltage is avoided, the reliability of the equalization function is improved, and the method has great practical significance.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A battery module equalizing circuit with priority of hardware control logic is characterized in that the battery module comprises a plurality of single batteries B connected in series;

the equalization circuit comprises a plurality of equalization loops (100) and a battery front end detection chip (200);

each single battery B is correspondingly connected with one equalizing loop (100) respectively;

the battery front end detection chip (200) is connected with the plurality of equalization loops (100);

for any battery module, an input end 1 of a balancing loop (100) of any single battery Bm which is not connected with the positive end and the negative end of the battery module is respectively connected with the positive end Bm + of the corresponding single battery Bm and is used for receiving the voltage and the current of the single battery B;

the input end 2 of the equalizing loop (100) of the single battery Bm is respectively connected with the negative electrode end Bm-of the single battery Bm and is used for receiving the voltage and the current of the single battery Bm;

the input end 3 of the equalizing loop (100) of the single battery Bm is connected with the output end Am-1 of the adjacent equalizing loop of the high phase of the equalizing loop (100) and is used for receiving the equalizing control signal Am-1 output by the adjacent equalizing loop of the high phase of the equalizing loop (100);

the equalizing circuit (100) of the single battery Bm has an input end 4 connected with one output end BCm1 of the battery front end detection chip (200) and is used for receiving an equalizing control signal BCm1 sent by the battery front end detection chip (200) to the equalizing circuit (100);

the equalizing loop (100) of the single battery Bm has an input end 5 connected with the other output end BCn2 of the battery front-end detection chip (200) and is used for receiving the other equalizing control signal BCn2 sent by the battery front-end detection chip (200) to the equalizing loop (100);

the output end Am of the equalizing loop (100) of the single battery Bm is connected with the input end 3 of the lower phase adjacent equalizing loop of the equalizing loop (100) and is used for outputting an equalizing control signal Am to the lower phase adjacent equalizing loop of the equalizing loop (100);

for the equalization loop (100) correspondingly connected with each single battery in one battery module, an adjacent equalization loop which is closer to the positive terminal of the battery module is defined as an adjacent equalization loop at a higher position of the equalization loop (100);

for the equalization loop (100) correspondingly connected with each single battery in a battery module, an adjacent equalization loop closer to the negative end of the battery module is defined as a lower adjacent equalization loop of the equalization loop (100).

2. The hardware control logic priority battery module balancing circuit according to claim 1, characterized in that, for the battery cell B1 connected to the positive terminal of the battery module, the 1 st balancing loop (100) is correspondingly connected, the input terminal 1 of which is connected to the positive terminal B1+ of the battery cell B1, and is used for receiving the voltage and current of the battery cell B1;

the 1 st equalizing loop (100) is connected with the negative terminal B1-of the battery cell B1 at the input terminal 2 and is used for receiving the voltage and the current of the battery cell B1;

the input end 3 of the 1 st equalizing loop (100) is connected with the output end Bn of the nth equalizing loop in the high-phase adjacent battery module of the battery module where the equalizing loop is located and is used for receiving the equalizing control signal Bn output by the nth equalizing loop in the high-phase adjacent battery module;

the 1 st equalizing loop (100) has an input end 4 connected to an output end BC11 of the battery front-end detecting chip (200), and is configured to receive an equalizing control signal BC11 sent by the battery front-end detecting chip (200) to the equalizing loop (100);

the 1 st equalizing loop (100) has an input end 5 connected to the other output end BC12 of the battery front-end detecting chip (200), and is configured to receive another equalizing control signal BC12 sent by the battery front-end detecting chip (200) to the equalizing loop (100);

the output end a1 of the 1 st equalizing loop (100) is connected to the input end 3 of the lower adjacent equalizing loop of the equalizing loop (100) and is used for outputting an equalizing control signal a1 to the lower adjacent equalizing loop of the equalizing loop (100).

3. The hardware control logic-prioritized battery module balancing circuit according to claim 1, wherein, for the cell Bn connected to the negative terminal of the battery module, the corresponding nth balancing loop (100) has an input terminal 1 connected to the positive terminal Bn + of the cell Bn for receiving the voltage and current of the cell Bn;

the nth equalizing loop (100) is connected with the input end 2 of the nth equalizing loop and the negative electrode end Bn-of the single battery Bn and is used for receiving the voltage and the current of the single battery Bn;

the input end 3 of the nth equalizing loop (100) is connected with the output end An-1 of the lower phase adjacent equalizing loop of the equalizing loop (100) and is used for receiving the equalizing control signal An-1 output by the lower phase adjacent equalizing loop of the equalizing loop (100);

an nth equalization loop (100), having an input terminal 4 connected to an output terminal BCn1 of the battery front-end detection chip (200), for receiving an equalization control signal BCn1 sent by the battery front-end detection chip (200) to the equalization loop (100);

an nth equalization loop (100), having an input terminal 5 connected to the other output terminal BCn2 of the battery front-end detection chip (200), for receiving another equalization control signal BCn2 sent by the battery front-end detection chip (200) to the present equalization loop (100);

the output end An of the nth equalizing loop (100) is connected with the input end 3 of the 1 st equalizing loop in the lower-phase adjacent battery module of the battery module where the equalizing loop is located and is used for outputting An equalizing control signal An to the 1 st equalizing loop in the lower-phase adjacent battery module;

4. The hardware control logic priority battery module balancing circuit according to claim 1, wherein, for any one of the battery cells Bm not connected with the positive terminal and the negative terminal of the battery module, the balancing circuit (100) comprises a balancing resistor RB, a balancing switch QB, resistors R1-R14, a capacitor C1, switching tubes Q1-Q6 and a diode D1, wherein:

the 1 st pin of the balancing resistor RB is used as an input end 1 of a balancing loop (100) of the single battery Bm, is connected with a positive terminal Bm + of the single battery Bm, and is used for receiving the voltage and the balancing current of the single battery Bm;

the 2 nd pin of the balance resistor RB is connected with the T4 end;

the source S of the balance switch QB is used as the input end 2 of a balance loop (100) of the single battery Bm, is connected with the negative electrode end Bm-of the single battery Bm, and is used for receiving the voltage and the balance current of the single battery Bm;

source S of equalization switch QB, also connected to the cathode of diode D1;

the grid G of the equalizing switch QB is connected with the T3 end;

an emitter E of the switching tube Q4 connected to an anode of the diode D1;

an emitter E of the switching tube Q5, which is used as an input end 1 of an equalizing loop (100) of the single battery Bm, is also respectively connected with a positive terminal Bm + of the single battery Bm, a1 st pin of a resistor R9 and a1 st pin of a resistor R1, and is used for receiving the voltage and the current of the single battery Bm;

a2 nd pin of the resistor R11, which is used as an output end Am of an equalization loop (100) of the single battery Bm, is respectively connected with an input end 3 of the equalization loop (100) of the adjacent single battery with the lower phase of the single battery Bm and is used for outputting an equalization control signal Am;

the 2 nd pin of the resistor R6 is connected with the T1 end;

the 2 nd pin of the resistor R2 is connected with the T2 end;

a pin 2 of the resistor R4, which is an input terminal 4 of an equalization loop (100) provided by the battery cell Bm, is connected to an output terminal BCm1 of the battery front-end detection chip (200), and is configured to receive an equalization control signal BCm1 sent by the battery front-end detection chip (200), where the signal states include a high level and a low level;

the drain D of the switching tube Q6, which is the input terminal 5 of the balancing loop (100) of the single battery Bm, is connected to the other output terminal BCm2 of the battery front-end detection chip (200) for receiving the other balancing control signal BCm2 sent by the battery front-end detection chip (200), and the signal state of the balancing control signal BCm2 is fixed to a low level;

a grid G of the switching tube Q6 is used as an input end 3 of an equalizing loop (100) of the single battery Bm, and is connected with an output end Am-1 of the equalizing loop (100) of the adjacent high-order single battery of the single battery Bm and used for receiving an equalizing control signal Am-1 sent by the equalizing loop (100) of the adjacent high-order single battery of the single battery Bm;

5. The hardware control logic-prioritized battery module balancing circuit according to claim 4, wherein, for the cell B1 connected to the positive terminal of the battery module, the balancing circuit (100) has substantially the same structure as the balancing circuit (100) of the cell Bm, except that the gate G of the switching tube Q6, which is used as the input terminal 3 of the balancing circuit (100), is connected to the output terminal Bn of the nth balancing circuit (100) in the higher adjacent battery module of the battery module where the balancing circuit is located.

6. The battery module equalization circuit with priority on hardware control logic according to claim 4, characterized in that, for the cell Bn connected to the negative terminal of the battery module, the equalization loop (100) has substantially the same structure as the equalization loop (100) of the cell Bm, except that the 2 nd pin of the resistor R11 as the output terminal An of the equalization loop (100) is connected to the input terminal 3 of the 1 st equalization loop in the lower adjacent battery module of the battery module where the equalization loop is located.