CN214799907U - Clock offset compensation system for improving TDOA positioning accuracy - Google Patents
Clock offset compensation system for improving TDOA positioning accuracy Download PDFInfo
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Abstract
The clock offset compensation system for improving the TDOA positioning accuracy comprises a microcontroller MCU, wherein the microcontroller MCU is respectively in bidirectional connection with a digital phase discriminator and a reference clock source through a digital phase discriminator control and data bus and a reference clock source control and data bus, the microcontroller MCU is also respectively in bidirectional connection with a first UWB receiver and a second UWB receiver through a UWB receiver data bus, a first phase-locked loop and a second phase-locked loop are respectively arranged in the first UWB receiver and the second UWB receiver, the first phase-locked loop and the second phase-locked loop are respectively connected with a reference clock source through a first clock signal line and a second clock signal line, and the digital phase discriminator is respectively connected with the first clock signal line and the second clock signal line through a first phase measurement line and a second phase measurement line; the system has the advantages of low implementation cost, low calculation resource consumption, sub-nanosecond synchronization precision, high positioning precision and the like.
Description
Technical Field
The utility model relates to a thing networking location technical field especially relates to a clock skew compensating system for improving TDOA positioning accuracy.
Background
The position information acquisition is one of basic technologies for realizing the connection of everything in the internet of things, and an Ultra Wide Band (UWB) signal is used as a high-precision positioning signal, has the advantages of high time resolution, strong penetrability, insensitivity to channel fading, low signal energy spectrum density, low system complexity and the like, can be widely applied to scenes such as staff, material, vehicle positioning and the like in various indoor and outdoor environments without satellite navigation positioning, and has a very Wide application prospect.
A positioning method based on Time Difference of Arrival (TDOA) is also called hyperbolic positioning, and the principle is that a hyperbola of possible positions of a tag is obtained by measuring differences of propagation times of UWB signals transmitted by the tag respectively arriving at a group of UWB receivers; the accurate position of the tag can be obtained using multiple sets of UWB receivers. Since the time when the UWB signal reaches the receiver is obtained by measuring the time of the receiver itself, according to the TDOA positioning principle, in order to obtain a high-precision time difference of arrival, a group of UWB receivers must maintain a high clock synchronization precision, thereby ensuring the positioning precision.
The existing wired clock synchronization technology with higher synchronization precision replaces respective internal crystal oscillator clocks of two UWB receivers by using the same reference clock source so as to eliminate the influence caused by frequency drift and frequency deviation of different crystal oscillators and realize higher-quality clock synchronization. Ideally, a same source clock and equal-length clock signal lines are used, clock signals reaching two receivers should keep the same frequency and the same phase, but clock signals reaching two UWB receivers have clock skew, namely phase difference, due to inevitable transmission path difference and load characteristic difference in an actual circuit; for an ultra-wideband measurement system, nanosecond clock synchronization errors can bring 30cm measurement errors, and if the phase difference is not considered, the best synchronization precision which can be achieved by clock synchronization is the value of the phase difference; in the TDOA method, the phase error is not a common-mode error, and is not eliminated by the differential operation, and is mixed into the finally obtained arrival time difference, thereby causing a positioning error. In order to improve the positioning accuracy of the ultra-wideband positioning module based on the TDOA algorithm, a system for compensating clock offset needs to be designed.
Disclosure of Invention
The utility model discloses the purpose is exactly to not enough among the prior art, provides a clock skew compensating system for improving TDOA positioning accuracy to solve current ultra wide band measurement system and have the technical defect that phase difference and positioning error etc. brought, improve the positioning accuracy and the synchronous precision based on the ultra wide band orientation module of TDOA algorithm, for purpose more than realizing, the utility model discloses a following technical scheme realizes:
a clock skew compensating system for improving TDOA positioning accuracy, including microcontroller MCU, microcontroller MCU establishes two-way connection through digital phase detector control and data bus and reference clock source control and data bus and digital phase detector and reference clock source respectively, microcontroller MCU still establishes two-way connection with first UWB receiver and second UWB receiver respectively through UWB receiver data bus, first UWB receiver and second UWB receiver are inside to be provided with first phase-locked loop and second phase-locked loop respectively, first phase-locked loop and second phase-locked loop link to each other with the reference clock source through first clock signal line and second clock signal line respectively, digital phase detector links to each other with first clock signal line and second clock signal line through first phase-locked line and second phase-locked line respectively.
Preferably, the reference clock source is a single clock source and provides clock driving.
Preferably, the reference clock source provides synchronous clock drive for the first UWB receiver and the second UWB receiver, and superimposes and outputs a synchronization signal SYNC to the first UWB receiver and the second UWB receiver synchronous reset timer under the control of the microcontroller MCU.
Preferably, the first clock signal line and the first phase measurement line are designed to be arranged in a serpentine shape with equal length, and the second clock signal line and the second phase measurement line are also designed to be arranged in a serpentine shape with equal length.
Preferably, the internal timers of the first UWB receiver and the second UWB receiver are driven by means of a clock signal referenced to a clock source.
Preferably, the first UWB receiver and the second UWB receiver both use a DW1000 UWB module from decapave corporation.
Preferably, the reference clock source includes an OCXO constant temperature crystal oscillator and a CPLD logic control circuit.
The utility model has the advantages that:
in order to improve the error that current wired clock synchronization technology compensation clock skew introduced in ultra wide band module TDOA measuring method, the utility model discloses a clock skew compensating system introduces reference clock source and digital phase discriminator and is used for improving the prior art defect to carry out special technical wiring design to clock signal line and phase place measuring line, have and realize with low costs, calculation resource consumption is little, and positioning accuracy is high, and synchronous precision reaches advantages such as subnanosecond level.
Drawings
Fig. 1 is a schematic circuit diagram of the clock skew compensation system of the present invention;
FIG. 2 is a flow chart illustrating a clock skew compensation method;
fig. 3 is a clock offset analysis diagram of a reference clock source and first and second UWB receivers according to the present invention;
fig. 4 is a clock skew analysis diagram of the first and second UWB receivers and the digital phase discriminator according to the present invention.
In the figure: 1. a microcontroller MCU; 2. a digital phase discriminator; 3. a reference clock source; 4. a first UWB receiver; 5. a second UWB receiver; 6. a digital phase discriminator control and data bus; 7. a reference clock source control and data bus; 8. a UWB receiver data bus; 9. a first clock signal line; 10. a second clock signal line; 11. a first phase measurement line; 12. a second phase measurement line.
Detailed Description
The invention will be further described with reference to the accompanying drawings and specific embodiments:
in order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention will be further described with reference to the accompanying drawings and examples.
Example 1:
as shown in fig. 1, a clock skew compensation system for improving TDOA positioning accuracy, including microcontroller MCU 1, wherein, the utility model discloses microcontroller MCU 1 that clock skew compensation system set up establishes two-way connection with digital phase discriminator 2 and reference clock source 3 through digital phase discriminator control and data bus 6 and reference clock source control and data bus 7 respectively, need to use reference clock source 3 as single clock source, and provide clock drive, and reference clock source 3 can provide synchronous clock drive for first UWB receiver 4 and second UWB receiver 5, and superpose output synchronizing signal SYNC under microcontroller MCU 1's control and give first UWB receiver 4 and second UWB receiver 5 synchronous reset timer; the internal timers of the first UWB receiver 4 and the second UWB receiver 5 are driven by means of a clock signal referenced to the clock source 3.
The utility model discloses a microcontroller MCU 1 that sets up still establishes both way junction with first UWB receiver 4 and second UWB receiver 5 respectively through UWB receiver data bus 8, the utility model discloses an inside first phase-locked loop and the second phase-locked loop of being provided with respectively of first UWB receiver 4 and second UWB receiver 5, first phase-locked loop and second phase-locked loop are connected with reference clock source 3 through first clock signal line 9 and second clock signal line 10 respectively again, digital phase discriminator 2 then links to each other with first clock signal line 9 and second clock signal line 10 through first phase measurement line 11 and second phase measurement line 12 respectively, first phase measurement line 11 forms CLK1 node with first clock signal line 9 cross-linking, second phase measurement line 12 forms CLK2 node with second clock signal line 10 cross-linking; the first clock signal line 9, namely the CLK 0-CLK 1 node, the second clock signal line 10, namely the CLK 0-CLK 2 node, the first phase measurement line 11, namely the CLK 1-CLK 1 'node, and the second phase measurement line 12, namely the CLK 2-CLK 2' node, wherein the first clock signal line 9 and the first phase measurement line 11 need to be designed by isometric serpentine wiring, and the second clock signal line 10 and the second phase measurement line 12 are also designed by isometric serpentine wiring.
For a better understanding of the embodiments of the compensation system of the present invention, the following statements are made on the clock skew compensation system of example 1.
As shown in fig. 2, the clock skew compensation method using the clock skew compensation system in embodiment 1 includes the steps of:
s1, powering on the clock offset compensation system, and generating a clock signal by referring to a clock source 3;
s2, superimposing a synchronous signal SYNC on the clock signal by referring to the clock source 3 under the control of the microcontroller MCU 1;
after the S3, the first UWB receiver 4 and the second UWB receiver 5 receive the synchronization signal SYNC, the respective internal counters reset to zero and start timing respectively;
s4, the digital phase discriminator 2 measures the clock phase difference Ts' in real time;
s5, the microcontroller MCU 1 waits for receiving the label positioning signal and judges whether the label positioning signal arrives; if yes, step S6 is executed in sequence; if not, continuing to wait for receiving the label positioning signal and judging whether the label positioning signal arrives;
s6, the microcontroller MCU 1 reads the time when the label positioning signal reaches the internal timers of the first UWB receiver 4 and the second UWB receiver 5, calculates the obtained arrival time difference Delta T ', reads the real-time measurement clock phase difference Ts' of the digital phase discriminator 2 at that time, and calculates the obtained estimated real arrival time difference according to a formula I
S7, judging whether a measurement stopping instruction is received by the microcontroller MCU 1; if yes, directly ending the program; otherwise, the step S8 is executed in sequence;
s8, judging whether the clock phase difference Ts' in the step S6 is larger than an error threshold value; if yes, the process returns to re-execute step S2; otherwise, the process returns to step S5.
In particular, the present invention is further explained in order to better understand the above-mentioned measuring method.
Because the internal timer of the UWB receiver is driven by the clock signal of the reference clock source 3, when the UWB receiver receives the synchronous signal SYNC superposed in the clock signal, the internal timer of the UWB receiver resets to zero and starts to time; due to the difference of the propagation paths of the clock signals, etc., the time when the synchronization signal SYNC reaches the first UWB receiver 4 and the second UWB receiver 5 is different, thereby affecting the starting point of the UWB internal timer.
As shown in fig. 3, with T0 as the time zero point of the system, T1 and T2 respectively represent the timing start points of the first and second UWB receivers, the clock offsets between the two UWB receivers and the reference clock source 3 are respectively counted as dT1 and dT2, and the time difference between the two is denoted as Ts, which is equal to dT2-dT1, i.e., the phase difference between the two nodes CLK1 and CLK 2.
Assuming that the times at which the issued tag locating signals arrive at the first UWB receiver 4 and the second UWB receiver 5 are ST1 and ST2, respectively, the time obtained by the first UWB receiver 4 from the internal timer should be ST1+ dT1, and similarly, the time obtained by the second UWB receiver 5 from the internal timer should be ST2+ dT 2.
Assuming that the true arrival time difference is Δ T-ST 2-ST1, the obtained arrival time difference is Δ T' ═ ST2+ dT2- (ST1+ dT1) ═ Δ T + Ts.
By the above relation, compensation for the measured arrival time can be obtained, thereby giving a formula closer to the true arrival time difference.
Since the digital phase detector 2 needs to measure the clock skew of the positioning signal propagating through the phase measurement line between the first UWB receiver 4 and the second UWB receiver 5, even if the arrangement positions are close to each other, the influence of the measurement line on the clock signal propagation still exists, and the time difference Ts cannot be directly measured.
As shown in fig. 3, it is assumed that the clock offset at which the clock signal emanating from the reference clock source 3 propagates through the CLK0 node to the CLK1 node of the first UWB receiver 4 is dT1 and the clock offset from the CLK1 node to the digital phase detector 2 interface CLK1 'node is dT 11'; assuming that the clock offset of the clock signal propagating through the CLK0 node to the CLK2 node of the second UWB receiver 5 is dT2 and the clock offset propagating from the CLK2 node to the CLK2 'node of the digital phase detector 2 interface is dT 22', in practice, the phase difference of the clock measured by the digital phase detector 2 is:
ts ' ═ dT2+ dT22 ' -dT1-dT11 ' equation 2.
The method for estimating the time difference Ts is to require the isometric and symmetrical wiring design of a first clock signal line 9 and a first phase measurement line 11, and the isometric and symmetrical wiring design of a second clock signal line 10 and a second phase measurement line 12; thus dT1 is approximately equal to dT11 ' and dT2 is approximately equal to dT22 ', the real time difference estimation formula is converted into Ts '/2, i.e. the real time difference of arrival is estimated
In order to better implement the system, as shown in fig. 1, the DW1000 UWB chip designed by Decawave corporation is used as an example by continuing to use the clock skew compensation system built in embodiment 1, and the DW1000 UWB module is used as a specific description of the UWB receiver of the present invention, thereby implementing the clock skew compensation system of the present invention.
The digital subsystem of the DW1000 UWB module operates at 38.4MHz frequency, i.e. the clock period of the reference clock source 3 is 26 ns; although a phase-locked loop is provided to lock the frequency and phase, the clocks input to the two DW1000 modules are not guaranteed to be phase aligned, i.e., there is an unknown clock offset within 26 ns. The duty cycle of the counter inside the DW1000 UWB module is 15.6ps, which is much higher than the driving clock cycle, so the clock skew is the main cause of the measurement error reaching the time difference.
The digital phase discriminator 2 is formed by the AD8302+ ADC module, so that the phase difference between the clock inputs of the two DW1000 modules is measured to improve the precision, and the phase difference is compensated in software to reach the precision lower than 0.2 ns.
The microcontroller MCU 1 can adopt the MCU of the STM32F411 Cortex-M core, reads the data of the DW1000 UWB module and the AD8302 through the digital phase discriminator control and data bus 6 and the reference clock source control and data bus 7, and controls the work of the AD8302 and the reference clock source 3. The reference clock source 3 is composed of an OCXO constant temperature crystal oscillator of 38.4Mhz and a CPLD logic control circuit, and provides a clock drive and simultaneously superposes a synchronous signal SYNC to the DW1000 UWB module. Two DW1000 UWB modules are arranged on one PCB circuit board, with a base length of 120 mm.
The utility model discloses working process and technical principle of method:
through the aforesaid connection and setting, microcontroller MCU 1 can read the moment of reacing first, second UWB receiver respectively, and time phase difference and control reference clock source 3 between CLK1 'and CLK 2' two nodes that obtain through two time period digital phase discriminator 2 measurement send synchronizing signal SYNC, microcontroller MCU 1 accessible the utility model discloses a measuring method calculates the true time difference of reaching DeltaT that label positioning signal reachd first UWB receiver 4 and second UWB receiver 5.
Various other modifications and changes may be made by those skilled in the art based on the above-described technical solutions and concepts, and all such modifications and changes are intended to fall within the scope of the claims.
Claims (7)
1. A clock skew compensating system for improving TDOA positioning accuracy, including microcontroller MCU, its characterized in that, microcontroller MCU establishes two-way connection with digital phase discriminator and reference clock source through digital phase discriminator control and data bus and reference clock source control and data bus respectively, microcontroller MCU still establishes two-way connection with first UWB receiver and second UWB receiver respectively through UWB receiver data bus, first UWB receiver and the inside first phase-locked loop and the second phase-locked loop of being provided with respectively of second UWB receiver, first phase-locked loop and second phase-locked loop link to each other with the reference clock source through first clock signal line and second clock signal line respectively, digital phase discriminator links to each other with first clock signal line and second clock signal line through first phase measurement line and second phase measurement line respectively.
2. The clock-offset compensation system for improving TDOA location accuracy of claim 1, wherein said reference clock source is a single clock source and provides clock drive.
3. The clock offset compensation system for improving the accuracy of TDOA position location according to claim 2, wherein said reference clock source provides synchronized clock driving for the first UWB receiver and the second UWB receiver and superimposes and outputs synchronization signals SYNC to the first UWB receiver and the second UWB receiver synchronization reset timer under the control of the microcontroller MCU.
4. The clock offset compensation system for improving the accuracy of TDOA locations according to claim 1, wherein said first clock signal line and first phase measurement line are laid in equal length serpentine patterns, and said second clock signal line and second phase measurement line are also laid in equal length serpentine pairs.
5. The clock offset compensation system for improving TDOA location accuracy of claim 1, wherein internal timers of said first UWB receiver and said second UWB receiver are driven by a clock signal of a reference clock source.
6. A clock offset compensation system for improving TDOA location accuracy as recited in claim 1, wherein said first UWB receiver and said second UWB receiver each employ a dcawave DW1000 UWB module.
7. The clock offset compensation system for improving TDOA location accuracy of claim 1, wherein said reference clock source comprises an OCXO oven crystal oscillator and a CPLD logic control circuit.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113411879A (en) * | 2021-05-26 | 2021-09-17 | 佛山市南海区广工大数控装备协同创新研究院 | Clock offset compensation system and method for improving TDOA (time difference of arrival) positioning accuracy |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113411879A (en) * | 2021-05-26 | 2021-09-17 | 佛山市南海区广工大数控装备协同创新研究院 | Clock offset compensation system and method for improving TDOA (time difference of arrival) positioning accuracy |
| CN113411879B (en) * | 2021-05-26 | 2022-12-16 | 佛山市南海区广工大数控装备协同创新研究院 | Clock offset compensation system and method for improving TDOA (time difference of arrival) positioning accuracy |
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