CN214541520U

CN214541520U - Display panel and display device

Info

Publication number: CN214541520U
Application number: CN202023334967.3U
Authority: CN
Inventors: 袁永
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-10-29
Anticipated expiration: 2030-12-31

Abstract

The utility model discloses a display panel and display device. The drive circuit comprises N cascaded stages of shift registers, and each shift register comprises a first control unit, a second control unit, a third control unit and a fourth control unit. The first control unit receives a signal of an input signal for controlling the first node in response to a first clock signal; the second control unit receives the first voltage signal and the second voltage signal, and controls the signal of the second node in response to the signal of the first node, the first clock signal and the second clock signal; the third control unit receives the first voltage signal responding to the signal of the third node, or the second voltage signal responding to the signal of the second node, and generates an output signal; the fourth control unit is connected to the third node, and controls the potential of the third node to be a first low-level signal in at least a first time period when the first node is a low-level signal, wherein the potential of the first low-level signal is lower than that of the first voltage signal.

Description

Display panel and display device

Technical Field

The utility model relates to a display panel field especially relates to a display panel and display device.

Background

In the display field, a shift register is often required to implement a scan display or other functions. However, when the shift register works, the voltage of the internal control node of the shift register inevitably has threshold loss, so that the transistor in the corresponding shift register cannot be fully turned on, the level of the output end of the shift register cannot reach the target voltage, a tailing phenomenon is generated, and the display effect is influenced.

When the output signal of the PMOS transistor in the shift register jumps from high level to low level, the gate potential of the PMOS transistor is Vgl potential, and the source potential of the PMOS transistor is also Vgl potential, i.e. the gate and the source of the PMOS transistor are both Vgl potential, the PMOS transistor works in an unsaturated state, which results in that the voltage output by the drain is | -Vth |, wherein Vth is the threshold voltage of the PMOS transistor.

Since the voltage output from the drain of the PMOS transistor does not reach the effect of the predetermined output Vgl, the output pulse signal of the present shift register has a tailing phenomenon when the high level jumps to the low level.

SUMMERY OF THE UTILITY MODEL

An embodiment of the utility model provides a display panel and display device to solve shift register output signal trailing problem.

In a first aspect, an embodiment of the present invention provides a display panel, including:

the driving circuit comprises N stages of shift registers which are mutually cascaded, wherein N is more than or equal to 2;

the shift register includes:

a first control unit for receiving an input signal and controlling a signal of a first node in response to a first clock signal;

a second control unit for receiving a first voltage signal and a second voltage signal and controlling a signal of a second node in response to a signal of the first node, the first clock signal, and a second clock signal;

a third control unit, configured to receive the first voltage signal and respond to a signal of a third node, or receive the second voltage signal and respond to a signal of the second node to generate an output signal, where the third node is connected to the first node, the first voltage signal is a low-level signal, and the second voltage signal is a high-level signal;

and the fourth control unit is connected to the third node and is used for controlling the potential of the third node to be a first low-level signal in at least a first time period when the first node is a low-level signal, wherein the potential of the first low-level signal is lower than that of the first voltage signal.

In a second aspect, an embodiment of the present invention further provides a display device, including the display panel of the first aspect.

The embodiment of the utility model provides a display panel includes drive circuit, and this drive circuit includes N grades of shift register that cascade each other to shift register includes first the control unit, second the control unit, third the control unit and fourth the control unit. The third control unit is used for receiving the first voltage signal and responding to a signal of a third node, or receiving the second voltage signal and responding to a signal of a second node to generate an output signal. The fourth control unit is connected to the third node, and can control the potential of the third node to be the first low-level signal in at least the first time period when the first node is the low-level signal, and the potential of the first low-level signal is lower than that of the first voltage signal, that is, the potential of the third node is lower than that of the first voltage signal, so that the transistor in the third control unit rapidly approaches to a saturation state, and the first voltage signal is output, thereby avoiding the tailing problem.

Drawings

FIG. 1 is a diagram illustrating a shift register according to the prior art;

FIG. 2 is a timing diagram of the shift register shown in FIG. 1;

fig. 3 is a schematic structural diagram of a shift register of a display panel according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

FIG. 14 is a timing diagram of the circuit configuration shown in FIG. 13;

fig. 15 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

FIG. 16 is a timing diagram of the circuit configuration shown in FIG. 15;

fig. 17 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

FIG. 18 is a timing diagram of the circuit configuration shown in FIG. 17;

fig. 19 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

FIG. 20 is a timing diagram of the circuit configuration shown in FIG. 19;

fig. 21 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

FIG. 22 is a timing diagram of the circuit configuration shown in FIG. 21;

fig. 23 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

FIG. 24 is a timing diagram of the circuit configuration shown in FIG. 23;

fig. 25 is a schematic structural diagram of a shift register of another display panel according to an embodiment of the present invention;

fig. 26 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of a shift register in the prior art, and fig. 2 is a timing diagram of the shift register shown in fig. 1. Referring to fig. 1 and 2, when the shift register needs to jump from high to low, the transistor P1 needs to be turned off, and the transistor P2 needs to be turned on. At this time, the gate potential of the transistor P2 is Vgl potential, and the source potential of the transistor P2 is also Vgl potential, i.e. both the gate and the source of the transistor P2 are Vgl potential, the transistor P2 is in an unsaturated state, which results in the output voltage of the drain of the transistor P2 being | Vgl | -Vth |, where Vth is the threshold voltage of the transistor P2. Since the voltage output from the drain of the transistor P2 does not reach the effect of the predetermined output Vgl, as shown in fig. 2, the output pulse signal of the shift register at present has a tailing phenomenon (as shown by the arrow in fig. 2) when the high level jumps to the low level.

In view of this, an embodiment of the present invention provides a display panel, which includes a driving circuit including N stages of shift registers cascaded with each other. N is a positive integer greater than or equal to 2. The driving circuit is used for outputting pulse signals to the display panel line by line. For example, a scanning pulse signal is output to each scanning line of the display panel, or a light emission control pulse signal is output to each row of light emission control signal lines of the display panel. Fig. 3 is a schematic structural diagram of a shift register of a display panel according to an embodiment of the present invention, as shown in fig. 3, the shift register of the display panel according to an embodiment of the present invention includes a first control unit 01, a second control unit 02, a third control unit 03, and a fourth control unit 04. The first control unit 01 is configured to receive an input signal IN and control a signal of a first node N1 IN response to a first clock signal CK 1. The second control unit 02 is for receiving the first voltage signal Vgl and the second voltage signal Vgh, and controlling the signal of the second node N2 in response to the signal of the first node N1, the first clock signal CK1, and the second clock signal CK 2. The third control unit 03 is configured to receive the first voltage signal Vgl and generate an output signal OUT in response to a signal of the third node N3, or receive the second voltage signal Vgh and generate an output signal OUT in response to a signal of the second node N2. The third node N3 is connected to the first node N1, the first voltage signal Vgl is a low level signal, and the second voltage signal Vgh is a high level signal. The embodiment of the utility model provides a still be provided with fourth the control unit 04, fourth the control unit 04 is connected in third node N3. The fourth control unit 04 may control the potential of the third node N3 to be the first low level signal V1 in at least a first period when the first node N1 is a low level signal, in which the potential of the first low level signal V1 is lower than the potential of the first voltage signal Vgl. Therefore, the gate potential of the transistor for controlling the output signal OUT in the third control unit 03 to be generated is less than the potential of the first voltage signal Vgl, and the source potential is the potential of the first voltage signal Vgl, so that the transistor for controlling the output signal OUT in the third control unit 03 to be generated quickly tends to a saturation state, the source voltage and the drain voltage of the transistor for controlling the output signal OUT in the third control unit 03 to be generated tend to be equal, and thus the tailing phenomenon can be reduced.

Optionally, on the basis of the foregoing embodiment, the fourth control unit may further include a first capacitor, a first plate of the first capacitor is connected to the third node, and the second plate receives the first control signal; in the first time period, the first control signal is a low level signal. For example, referring to fig. 4, a first capacitor C1 is disposed in the fourth control unit 04, a first plate of the first capacitor C1 is connected to the third node N3, and a second plate receives the first control signal a 1. In the first period, the first node N1 is at a low level, the first control signal a1 is at a low level, and the first capacitor C1 is charged quickly, so that the potential of the third node N3 drops rapidly and is lower than the potential of the first voltage signal Vgl.

Optionally, for example, referring to fig. 5, the fourth control unit 04 may further include a first transistor M1, a source of the first transistor M1 receives the first control signal a1, a drain of the first transistor M1 is connected to the second plate of the first capacitor C1, and a gate of the first transistor M1 receives the second control signal a 2; during the first period, the second control signal a2 controls the first transistor M1 to turn on, and the first control signal a1 is transmitted to the first capacitor C1, where the first node N1 is at a low voltage level. Under the low level control of the first capacitor C1 and the first control signal a1, the potential of the third node N3 rapidly drops below the first voltage signal Vgl. Since the third node N3 is required to be kept at a high level all the time when the third control unit 03 receives the second voltage signal Vgh and generates the output signal OUT in response to the signal of the second node N2. That is, the fourth control module 04 is not required to control the node N3 to be lower than the potential of the first voltage signal Vgl at any time. Therefore, the embodiment of the present invention provides the first transistor M1, which can make the first transistor M1 turn on in the first time period, control the potential of the third node N3 node smaller than the first voltage signal Vgl, and in other time periods, the first transistor M1 can be turned off, so as to avoid causing interference to the potential of the third node N3, and affect the output signal of the shift register.

Optionally, the first control signal and the second control signal may be the same signal. For example, as shown in fig. 6, the source and the gate of the first transistor M1 are electrically connected and both receive the first control signal a1 (or the second control signal a 2). This arrangement can reduce the number of signal lines in the display panel.

Optionally, the first clock signal CK1 and the first control signal a1 may be the same signal. As shown in fig. 7, embodiments of the present invention can further reduce the number of signal lines in the display panel. By adjusting the timing of the shift register, the first clock signal CK1 is ensured to be a low level signal in the first time period, so that the fourth control unit can control the potential of the third node to be the first low level signal, that is, the potential of the third node is lower than the potential of the first voltage signal Vgl.

Optionally, the second control signal may be set as a signal of the first node. As shown in fig. 8, the gate of the first transistor M1 is connected to the first node N1, and thus the second control signal a2 is the signal of the first node N1. When the first node N1 is at a low level, the first transistor M1 is turned on, and the first control signal a1 is transmitted to the first capacitor C1, so as to control the voltage level of the third node N3 to be lower than the voltage level of the first voltage signal Vgl during the first period.

Optionally, the fourth control unit in the embodiment of the present invention may further include a second capacitor, a first plate of the second capacitor is connected to the gate of the first transistor, and the second plate receives the second voltage signal. For example, as shown in fig. 9, the fourth control unit 04 includes a second capacitor C2, a first plate of the second capacitor C2 is connected to the gate of the first transistor M1, and a second plate receives the second voltage signal Vgh. When the second control signal a2 is the signal of first node N1 node, the utility model discloses the implementation can stabilize the electric potential of first node N1 node through second voltage signal Vgh and second electric capacity C2, avoids floating of first node N1 electric potential to influence the electric potential of third node N3.

Optionally, the capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor. Since the first capacitor C1 is used to control the pull-down of the third node potential, and the relationship U between the capacitor C, the charge Q, and the voltage U is Q/C, it can be seen that, in the case of the same charge, if the voltage is to be dropped rapidly, a smaller capacitance value is required, and the smaller the capacitance is, the faster the pull-down speed of the third node potential is, the easier the effect of reducing the tailing phenomenon is to be enhanced. The first capacitor C1 requires a smaller capacitance value. The second capacitor C2 is mainly used to stabilize the potentials of the first node N1 and the third node N3, and therefore, the second capacitor C2 needs a larger capacitance value to avoid the potential of the first node N1 from changing too much during the charging and discharging processes of the capacitor, thereby improving the stability of the node potential. Therefore, the embodiment of the present invention provides a capacitance value that sets up first electric capacity is less than the capacitance value of second electric capacity.

Optionally, the fourth control unit may further include a second transistor, a source of the second transistor is connected to the first node, a drain of the second transistor is connected to the third node, and a gate of the second transistor receives the first control signal; and the first control signal controls the second transistor to be switched on in the first time period. As shown in fig. 10, the fourth control unit 04 includes a first capacitor C1, a first transistor M1, and a second transistor M2. The source of the first transistor M1 receives the first control signal a1, the drain is connected to the third node N3, and the gate receives the second control signal a 2; the first capacitor is located between the drain of the first transistor M1 and the third node N3. The second control signal a2 controls the first transistor M1 to turn on during the first period, and the first control signal a1 is a low level signal during the first period. The source of the second transistor M2 is connected to the first node N1, the drain is connected to the third node N3, and the gate receives the first control signal a 1; wherein the first control signal a1 controls the second transistor M2 to be turned on during the first period.

If the first control signal a1 has not yet dropped to a low level, the potential of the first node N1 is transmitted to the third node N3, and the tailing problem of the shift register cannot be avoided. The embodiment of the utility model provides a set up second transistor M2 between first node N1 and third node N3, because first control signal A1 is received to the grid of second transistor M2, only be low level at first control signal A1, and when first transistor M1 switches on, second transistor M2 switches on simultaneously, thereby realize the drop-down of third node N3 potential, can prevent not having the pull-down effect of fourth the control unit 04, first node N1's potential direct transmission to third the control unit 03, thereby produce the trailing problem of output signal.

Optionally, the fourth control unit may further include a third transistor, a source of the third transistor receives the second voltage signal, a drain of the third transistor is connected to the third node, and a gate of the third transistor is connected to the second node; and the second node controls the third transistor to be turned off in a first time period. For example, as shown in fig. 11, the fourth control unit 04 includes a first capacitor C1, a first transistor M1, and a third transistor M3. The source of the first transistor M1 receives the first control signal a1, the drain is connected to the third node N3, and the gate receives the second control signal a 2; the first capacitor is located between the drain of the first transistor M1 and the third node N3. The second control signal a2 controls the first transistor M1 to turn on during a first period, and the first control signal a1 is a low level signal during the first period. The source of the third transistor M3 receives the second voltage signal Vgh, the drain is connected to the third node N3, and the gate is connected to the second node N2; wherein the second node N2 controls the third transistor M3 to turn off during the first period.

Since each clock signal in the shift register undergoes a plurality of transitions, the potentials of the first node N1 and the point node N3 are caused to float during the transition. The embodiment of the utility model provides a through setting up third transistor M3, utilize second node N2's electric potential to control third node N3's electric potential, guarantee the signal stability of third node N3 at the high-level. For example, if the shift register is required to output a high level (the second voltage signal Vgh), the second node N2 is a low level, and it is required that the third node N3 keeps a stable high level, the embodiment of the present invention provides the third transistor M3, the gate of the third transistor M3 is connected to the second node N2, the second node N2 is a low level, and the third transistor M3 is turned on, so that the third node N3 is stably maintained at the high level of the second voltage signal Vgh, and it is ensured that the level of the third node N3 does not change until the second node N2 changes to the high level, and only when the second node N2 changes to the high level, the third node N3 changes to a low level signal lower than the first voltage signal Vgl, thereby reducing the tailing phenomenon.

Optionally, the first control unit may include a fourth transistor, a source of the fourth transistor is connected to the input signal, a drain of the fourth transistor is connected to the first node, and a gate of the fourth transistor receives the first clock signal. The second control unit comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a third capacitor and a fourth capacitor. The source of the fifth transistor receives the first clock signal, the drain is connected to the fourth node, and the gate is connected to the first node. The sixth transistor has a source receiving the second clock signal, a drain connected to the fifth node, and a gate connected to the fourth node. The seventh transistor has a source receiving the first voltage signal, a drain connected to the fourth node, and a gate receiving the first clock signal. The eighth transistor has a source receiving the second voltage signal, a drain connected to the second node, and a gate connected to the first node. The ninth transistor has a source connected to the fifth node, a drain connected to the second node, and a gate receiving the second clock signal. The first plate of the third capacitor is connected to the fourth node, and the second plate is connected to the fifth node. The first plate of the fourth capacitor receives the second voltage signal, and the second plate is connected to the second node. The third control unit includes a tenth transistor and an eleventh transistor and a fourth capacitor. The tenth transistor has a source receiving the first voltage signal, a drain outputting the output signal, and a gate connected to the third node. The eleventh transistor has a source receiving the second voltage signal, a drain outputting the output signal, and a gate connected to the second node.

For example, referring to fig. 12, the first control unit 01 may include a fourth transistor M4, a source of the fourth transistor M4 receiving the input signal IN, a drain of the fourth transistor M4 connected to the first node N1, and a gate of the fourth transistor M1 receiving the first clock signal CK 1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. The source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The sixth transistor M6 has a source receiving the second clock signal CK2, a drain connected to the fifth node N5, and a gate connected to the fourth node N4. The seventh transistor M7 has a source receiving the first voltage signal Vgl, a drain connected to the fourth node N4, and a gate receiving the first clock signal CK 1. The eighth transistor M8 has a source receiving the second voltage signal Vgh, a drain connected to the second node N2, and a gate connected to the first node N1. The ninth transistor M9 has a source connected to the fifth node N5, a drain connected to the second node N2, and a gate receiving the second clock signal CK 2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The tenth transistor M10 has a source receiving the first voltage signal Vgl, a drain outputting the output signal OUT, and a gate connected to the third node N3. The eleventh transistor M11 has a source receiving the second voltage signal Vgh, a drain outputting the output signal OUT, and a gate connected to the second node N2.

Optionally, the capacitance value of the first capacitor C1 is smaller than that of the third capacitor C3, or the capacitance value of the first capacitor C1 is smaller than that of the fourth capacitor C4. Since the first capacitor C1 is used to control the pull-down of the potential of the third node N3, the smaller the capacitor is, the faster the pull-down speed of the potential of the third node N3 is, and the easier the effect of reducing the tailing phenomenon is. Therefore, the first capacitor C1 is set to be smaller than the capacitance value of the third capacitor C3 or smaller than the capacitance value of the fourth capacitor C4. The third capacitor C3 is mainly used to stabilize the potential of the fourth node N4, and the fourth capacitor C4 is used to stabilize the potential of the second node N2, so the third capacitor C3 and the fourth capacitor C4 are set to have larger capacitance values than the first capacitor C1.

The following describes the specific implementation principle of the present invention in detail by using several specific shift register circuit structure examples. Fig. 13 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and as shown IN fig. 13, the first control unit 01 includes a fourth transistor M4, a source of the fourth transistor M4 receives the input signal IN, a drain of the fourth transistor M4 is connected to the first node N1, and a gate of the fourth transistor M4 receives the first clock signal CK 1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. The source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The sixth transistor M6 has a source receiving the second clock signal CK2, a drain connected to the fifth node N5, and a gate connected to the fourth node N4. The seventh transistor M7 has a source receiving the first voltage signal Vgl, a drain connected to the fourth node N4, and a gate receiving the first clock signal CK 1. The eighth transistor M8 has a source receiving the second voltage signal Vgh, a drain connected to the second node N2, and a gate connected to the first node N1. The ninth transistor M9 has a source connected to the fifth node N5, a drain connected to the second node N2, and a gate receiving the second clock signal CK 2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The tenth transistor M10 has a source receiving the first voltage signal Vgl, a drain outputting the output signal OUT, and a gate connected to the third node N3. The eleventh transistor M11 has a source receiving the second voltage signal Vgh, a drain outputting the output signal OUT, and a gate connected to the second node N2. The fourth control unit 04 comprises a first capacitor C1, a first plate of the first capacitor C1 is connected to the third node N3, and a second plate receives the first control signal a 1. The fourth control unit 04 further includes a first transistor M1, the source of the first transistor M1 receives the first control signal a1, the drain of the first transistor M1 is connected to the second plate of the first capacitor C1, and the gate of the first transistor M1 receives the second control signal a 2. In this embodiment, the first clock signal, the first control signal A1 and the second control signal A2 are the same signal. In the first time period, the first control signal a1 is a low level signal, and the second control signal a2 controls the first transistor M1 to be turned on. Fig. 14 is a timing diagram of the circuit configuration shown in fig. 13. This is described in detail below with reference to fig. 13 and 14.

First stage T1: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the fourth transistor M4 is turned on, the first node N1 is at a high level, and the third node N3 is at a high level. The seventh transistor M7 is turned on, and the fourth node N4 is at a low level. The second clock signal CK2 is at a high level, the second node N2 is maintained at a high level, the eleventh transistor M11 is turned off, and the output signal OUT is maintained at an output low level.

Second stage T2: the input signal IN is at a high level, the first clock signal CK1 is at a high level, the fourth transistor M4 is turned off, the first node N1 node maintains a high level, and the third node N3 maintains a high level. The fourth node N4 is kept at a low level, the second clock signal CK2 is at a low level, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 node becomes a low level, the eleventh transistor M11 is turned on, and the output signal OUT becomes a high level.

Third stage T3: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the first node N1 is at a high level, the third node N3 is at a high level, the seventh transistor M7 is turned on, the fourth node N4 is at a low level, the second clock signal CK2 is at a high level, the sixth transistor M6 is turned on, the fifth node N5 is at a high level, the ninth transistor M9 is turned off, the second node N2 is at a low level, the eleventh transistor M11 is turned on, and the output signal OUT is at a high level.

Fourth stage T4: the input signal IN is at a low level, the first clock signal CK1 is at a high level, the first node N1 is at a high level, the third node N3 is at a high level, the fourth node N4 is at a low level, the second clock signal CK2 is at a low level, the second node N2 is at a low level, and the output signal OUT is at a high level.

Fifth stage T5: the input signal IN is low, the first clock signal CK1 is low, and the first node N1 is low. During the first period X1, the first transistor M1 is turned on, and the first capacitor C1 is charged rapidly, so that the potential of the third node N3 drops to the first low level signal V1 rapidly. The fourth node N4 is low, the second clock signal CK2 is high, and the second node N2 is high. Since the first low-level signal V1 is lower than the first voltage signal Vgl, and the gate potential of the tenth transistor M10 is lower than the source potential of the tenth transistor M10, the tenth transistor M10 can quickly approach a saturation state, the tenth transistor M10 is turned on, the eleventh transistor M11 is turned off, and the output signal OUT of the shift register substantially coincides with the first voltage signal Vgl, thereby avoiding the tailing phenomenon of the output signal.

Fig. 15 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and as shown IN fig. 15, the first control unit 01 includes a fourth transistor M4, a source of the fourth transistor M4 receives the input signal IN, a drain of the fourth transistor M4 is connected to the first node N1, and a gate of the fourth transistor M4 receives the first clock signal CK 1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. The source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The sixth transistor M6 has a source receiving the second clock signal CK2, a drain connected to the fifth node N5, and a gate connected to the fourth node N4. The seventh transistor M7 has a source receiving the first voltage signal Vgl, a drain connected to the fourth node N4, and a gate receiving the first clock signal CK 1. The eighth transistor M8 has a source receiving the second voltage signal Vgh, a drain connected to the second node N2, and a gate connected to the first node N1. The ninth transistor M9 has a source connected to the fifth node N5, a drain connected to the second node N2, and a gate receiving the second clock signal CK 2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The tenth transistor M10 has a source receiving the first voltage signal Vgl, a drain outputting the output signal OUT, and a gate connected to the third node N3. The eleventh transistor M11 has a source receiving the second voltage signal Vgh, a drain outputting the output signal OUT, and a gate connected to the second node N2. The fourth control unit 04 comprises a first capacitor C1, a first plate of the first capacitor C1 is connected to the third node N3, and a second plate receives the first control signal a 1. The fourth control unit 04 comprises a first capacitor C1, a first plate of the first capacitor C1 is connected to the third node N3, and a second plate receives the first control signal a 1. The fourth control unit 04 further includes a first transistor M1, the source of the first transistor M1 receives the first control signal a1, the drain of the first transistor M1 is connected to the second plate of the first capacitor C1, and the gate of the first transistor M1 receives the second control signal a 2. The second control signal A2 in this embodiment is the signal at the first node N1. The first clock signal CK1 is the same signal as the first control signal A1. In the first time period, the first control signal a1 is a low level signal, and the second control signal a2 controls the first transistor M1 to be turned on. Fig. 16 is a timing diagram of the circuit configuration shown in fig. 15. This is described in detail below with reference to fig. 15 and 16.

First stage T1: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the fourth transistor M4 is turned on, the first node N1 is at a high level, the third node N3 is at a high level, the seventh transistor M7 is turned on, and the fourth node N4 is at a low level. The second clock signal CK2 is at a high level, the second node N2 is maintained at a high level, the eleventh transistor M11 is turned off, and the output signal OUT is maintained at an output low level.

Fifth stage T5: the input signal IN is at a low level, the first clock signal CK1 is at a low level, the first node N1 is at a low level, and the gate of the first transistor M1 is connected to the first node N1, so that during the first period X1, the first transistor M1 is turned on, the first capacitor C1 is rapidly charged, and the potential of the third node N3 is rapidly decreased to the first low level signal V1. The fourth node N4 is low, the second clock signal CK2 is high, and the second node N2 is high. Since the first low-level signal V1 is lower than the first voltage signal Vgl, and the gate potential of the tenth transistor M10 is lower than the source potential of the tenth transistor M10, the tenth transistor M10 can quickly approach a saturation state, the tenth transistor M10 is turned on, the eleventh transistor M11 is turned off, and the output signal OUT of the shift register substantially coincides with the first voltage signal Vgl, thereby avoiding the tailing phenomenon of the output signal.

Fig. 17 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and as shown IN fig. 17, the first control unit 01 includes a fourth transistor M4, a source of the fourth transistor M4 receives the input signal IN, a drain of the fourth transistor M4 is connected to the first node N1, and a gate of the fourth transistor M4 receives the first clock signal CK 1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. The source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The sixth transistor M6 has a source receiving the second clock signal CK2, a drain connected to the fifth node N5, and a gate connected to the fourth node N4. The seventh transistor M7 has a source receiving the first voltage signal Vgl, a drain connected to the fourth node N4, and a gate receiving the first clock signal CK 1. The eighth transistor M8 has a source receiving the second voltage signal Vgh, a drain connected to the second node N2, and a gate connected to the first node N1. The ninth transistor M9 has a source connected to the fifth node N5, a drain connected to the second node N2, and a gate receiving the second clock signal CK 2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The tenth transistor M10 has a source receiving the first voltage signal Vgl, a drain outputting the output signal OUT, and a gate connected to the third node N3. The eleventh transistor M11 has a source receiving the second voltage signal Vgh, a drain outputting the output signal OUT, and a gate connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, a first transistor M1, and a second capacitor C2. The first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal a 1. The first transistor M1 has a source receiving the first control signal a1, a drain connected to the second plate of the first capacitor C1, and a gate receiving the second control signal a 2. The first plate of the second capacitor C2 is connected to the gate of the first transistor M1, and the second plate receives the second voltage signal Vgh. The gate of the first transistor M1 is connected to the first node N1, i.e., the second control signal a2 is a potential signal of the first node N1. In this embodiment, the first clock signal CK1 is the same as the first control signal A1. In the first time period, the first control signal a1 is a low level signal, and the second control signal a2 controls the first transistor M1 to be turned on. Fig. 18 is a timing diagram of the circuit configuration shown in fig. 17. This is described in detail below with reference to fig. 17 and 18.

Fifth stage T5: the input signal IN is at a low level, the first clock signal CK1 is at a low level, the first node N1 is at a low level, and during the first time period X1, the gate of the first transistor M1 is connected to the first node N1, so that the first transistor M1 is turned on, the first capacitor C1 is rapidly charged, and the potential of the third node N3 is rapidly dropped to the first low-level signal V1. The fourth node N4 is low, the second clock signal CK2 is high, and the second node N2 is high. Since the first low-level signal V1 is lower than the first voltage signal Vgl, and the gate potential of the tenth transistor M10 is lower than the source potential of the tenth transistor M10, the tenth transistor M10 can quickly approach a saturation state, the tenth transistor M10 is turned on, the eleventh transistor M11 is turned off, and the output signal OUT of the shift register substantially coincides with the first voltage signal Vgl, thereby avoiding the tailing phenomenon of the output signal. The utility model discloses be provided with second electric capacity C2 in the fourth the control unit 04 of implementation, can stabilize the electric potential of first node N1 node through second voltage signal Vgh and second electric capacity C2, avoid the electric potential of the unsteady influence third node N3 of first node N1 electric potential, and then influence shift register's output signal OUT.

Fig. 19 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and as shown IN fig. 19, the first control unit 01 includes a fourth transistor M4, a source of the fourth transistor M4 receives the input signal IN, a drain of the fourth transistor M4 is connected to the first node N1, and a gate of the fourth transistor M4 receives the first clock signal CK 1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. The source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The sixth transistor M6 has a source receiving the second clock signal CK2, a drain connected to the fifth node N5, and a gate connected to the fourth node N4. The seventh transistor M7 has a source receiving the first voltage signal Vgl, a drain connected to the fourth node N4, and a gate receiving the first clock signal CK 1. The eighth transistor M8 has a source receiving the second voltage signal Vgh, a drain connected to the second node N2, and a gate connected to the first node N1. The ninth transistor M9 has a source connected to the fifth node N5, a drain connected to the second node N2, and a gate receiving the second clock signal CK 2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The tenth transistor M10 has a source receiving the first voltage signal Vgl, a drain outputting the output signal OUT, and a gate connected to the third node N3. The eleventh transistor M11 has a source receiving the second voltage signal Vgh, a drain outputting the output signal OUT, and a gate connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, a first transistor M1, a second capacitor C2, and a second transistor M2. The first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal a 1. The first transistor M1 has a source receiving the first control signal a1, a drain connected to the second plate of the first capacitor C1, and a gate receiving the second control signal a 2. The first plate of the second capacitor C2 is connected to the gate of the first transistor M1, and the second plate receives the second voltage signal Vgh. The gate of the first transistor M1 is connected to the first node N1, i.e., the second control signal a2 is a potential signal of the first node N1. The source of the second transistor M2 is connected to the first node N1, the drain is connected to the third node N3, and the gate receives the first control signal a 1. In the first period, the first control signal a1 controls the second transistor M2 to turn on during the first period, the first control signal a1 is a low level signal, and the second control signal a2 controls the first transistor M1 to turn on. Fig. 20 is a timing diagram of the circuit configuration shown in fig. 19. This is described in detail below with reference to fig. 19 and 20.

First stage T1: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the fourth transistor M4 is turned on, the first node N1 is at a high level, the fourth node N4 is at a low level, the first control signal a1 is at a high level, the second transistor M2 is turned off, the third node N3 is kept at a low level, the second node N2 is at a high level, and the output signal OUT is at a low level.

Second stage T2: the input signal IN is at a high level, the first control signal a1 is at a low level, the second clock signal CK2 is at a high level, the first node N1 is at a high level, the second transistor M2 is turned on, the third node N3 is at a high level, the fourth node N4 is at a low level, the second node N2 is at a high level, and the output signal OUT remains at a low level.

Third stage T3: the input signal IN is at a high level, the second clock signal CK2 is at a low level, the first node N1 is at a high level, the third node N3 is at a high level, the fourth node N4 is at a low level, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 is at a low level, the eleventh transistor M11 is turned on, and the output signal OUT is at a high level.

Fourth stage T4: the input signal IN is at a high level, the second clock signal CK2 is at a high level, the first node N1 is at a high level, the third node N3 is at a high level, the fourth node N4 is at a low level, the second node N2 is at a low level, and the output signal OUT remains at a high level.

Fifth stage T5: the input signal IN is at a low level, the first clock signal CK1 is at a high level, the first control signal a1 is at a high level, the second clock signal CK2 is at a low level, the first node N1 is at a high level, the third node N3 is at a high level, the fourth node N4 is at a low level, the second node N2 is at a low level, and the output signal OUT remains at a high level.

Sixth stage T6: the input signal IN is at a low level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the first node N1 is at a low level, the fifth transistor M5 is turned on, the fourth node N4 is at a low level, the first control signal a1 is at a high level, the second transistor M2 is turned off, and the third node N3 is at a high level. Since the eighth transistor M8 is turned on, the second node N2 becomes a high level, the tenth transistor M10 and the eleventh transistor M11 are turned off, and the output signal OUT maintains a high level.

Seventh stage T7: the input signal IN is at a low level, the first control signal a1 is at a low level, the first node N1 is at a low level, and during the first time period X1, since the first capacitor C1 is rapidly charged, the potential of the first node N1 is pulled down to the potential of the first low-level signal V1, the potential of the first low-level signal V1 is less than the potential of the first voltage signal Vgl, the second transistor M2 is turned on, and therefore the potential of the third node N3 is the potential of the first low-level signal V1. The fourth node N4 and the second node N2 are both at a high level, the eleventh transistor M11 is turned off, and since the potential of the third node N3 is lower than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is lower than the source potential of the tenth transistor M10, the tenth transistor M10 can quickly approach a saturation state, the tenth transistor M10 is turned on, the output signal OUT of the shift register is substantially consistent with the first voltage signal Vgl, and the tailing phenomenon of the output signal is avoided.

Fig. 21 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and as shown IN fig. 21, the first control unit 01 includes a fourth transistor M4, a source of the fourth transistor M4 receives the input signal IN, a drain of the fourth transistor M4 is connected to the first node N1, and a gate of the fourth transistor M4 receives the first clock signal CK 1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. The source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The sixth transistor M6 has a source receiving the second clock signal CK2, a drain connected to the fifth node N5, and a gate connected to the fourth node N4. The seventh transistor M7 has a source receiving the first voltage signal Vgl, a drain connected to the fourth node N4, and a gate receiving the first clock signal CK 1. The eighth transistor M8 has a source receiving the second voltage signal Vgh, a drain connected to the second node N2, and a gate connected to the first node N1. The ninth transistor M9 has a source connected to the fifth node N5, a drain connected to the second node N2, and a gate receiving the second clock signal CK 2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The tenth transistor M10 has a source receiving the first voltage signal Vgl, a drain outputting the output signal OUT, and a gate connected to the third node N3. The eleventh transistor M11 has a source receiving the second voltage signal Vgh, a drain outputting the output signal OUT, and a gate connected to the second node N2. The fourth control unit 04 comprises a first capacitor C1, a first plate of the first capacitor C1 is connected to the third node N3, and a second plate receives the first control signal a 1. The fourth control unit 04 comprises a first capacitor C1, a first plate of the first capacitor C1 is connected to the third node N3, and a second plate receives the first control signal a 1. The fourth control unit 04 further includes a first transistor M1, the source of the first transistor M1 receives the first control signal a1, the drain of the first transistor M1 is connected to the second plate of the first capacitor C1, and the gate of the first transistor M1 receives the second control signal a 2. The second control signal A2 in this embodiment is the signal at the first node N1. In the first time period, the first control signal a1 is a low level signal, and the second control signal a2 controls the first transistor M1 to be turned on. In addition, the fourth control unit 04 further includes a second transistor M2, a source of the second transistor M2 is connected to the first node N1, a drain of the second transistor M2 is connected to the third node N3, and a gate of the second transistor M2 receives the first control signal a 1; in the first period, the first control signal a1 controls the second transistor M2 to be turned on. Fig. 22 is a timing diagram of the circuit configuration shown in fig. 21. This will be described in detail with reference to fig. 21 and 22.

First stage T1: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the fourth transistor M4 is turned on, the first node N1 is at a high level, the first control signal a1 is at a high level, the second transistor M2 is turned off, the third node N3 is kept at a low level, the seventh transistor M7 is turned on, and the fourth node N4 is at a low level. The second node N2 is at a high level, the eleventh transistor M11 is turned off, the tenth transistor M10 is turned on, and the output signal OUT is at a low level.

Second stage T2: the input signal IN is at a high level, the first clock signal CK1 is at a high level, the first control signal a1 is at a low level, the second clock signal CK2 is at a high level, the first node N1 is at a high level, the second transistor M2 is turned on, and the third node N3 is at a high level; the fourth node N4 is at a low level, the second node N2 is at a high level, and the output signal OUT remains at a low level.

Third stage T3: the input signal IN is at a high level, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, the first control signal a1 is at a high level, the first node N1 is at a high level, the third node N3 is at a high level, the fourth node N4 is at a low level, the sixth transistor M6 and the ninth transistor M9 are turned on, the second node N2 is at a low level, the eleventh transistor M11 is turned on, and the output signal OUT is at a high level.

Fifth stage T5: the input signal IN is at a low level, the second clock signal CK2 is at a low level, the first node N1 is at a high level, the third node N3 is at a high level, the fourth node N4 is at a low level, the second node N2 is at a low level, and the output signal OUT remains at a high level.

Sixth stage T6: the input signal IN is at a low level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the first node N1 is at a low level, the fourth node N4 is at a low level, the first control signal a1 is at a high level, the second transistor M2 is turned off, and the third node N3 is at a high level. Since the eighth transistor M8 is turned on, the second node N2 becomes a high level, the tenth transistor M10 and the eleventh transistor M11 are turned off, and the output signal OUT maintains a high level.

Seventh stage T7: the input signal IN is at a low level, the first control signal a1 is at a low level, and during the first time period X1, since the first capacitor C1 is rapidly charged, the first node N1 is pulled down to the potential of the first low level signal V1, the potential of the first low level signal V1 is less than the potential of the first voltage signal Vgl, the second transistor M2 is turned on, and therefore the potential of the third node N3 is equal to the potential of the first low level signal V1. The fourth node N4 is at a high level, the second node N2 is at a high level, the eleventh transistor M11 is turned off, since the potential of the third node N3 is lower than the potential of the first voltage signal Vgl, the gate potential of the tenth transistor M10 is lower than the source potential of the tenth transistor M10, the tenth transistor M10 can quickly approach to a saturation state, the tenth transistor M10 is turned on, and the output signal OUT of the shift register substantially coincides with the first voltage signal Vgl, thereby avoiding the tailing phenomenon of the output signal.

Fig. 23 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and as shown IN fig. 23, the first control unit 01 includes a fourth transistor M4, a source of the fourth transistor M4 receives the input signal IN, a drain of the fourth transistor M4 is connected to the first node N1, and a gate of the fourth transistor M4 receives the first clock signal CK 1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. The source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The sixth transistor M6 has a source receiving the second clock signal CK2, a drain connected to the fifth node N5, and a gate connected to the fourth node N4. The seventh transistor M7 has a source receiving the first voltage signal Vgl, a drain connected to the fourth node N4, and a gate receiving the first clock signal CK 1. The eighth transistor M8 has a source receiving the second voltage signal Vgh, a drain connected to the second node N2, and a gate connected to the first node N1. The ninth transistor M9 has a source connected to the fifth node N5, a drain connected to the second node N2, and a gate receiving the second clock signal CK 2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The tenth transistor M10 has a source receiving the first voltage signal Vgl, a drain outputting the output signal OUT, and a gate connected to the third node N3. The eleventh transistor M11 has a source receiving the second voltage signal Vgh, a drain outputting the output signal OUT, and a gate connected to the second node N2. The fourth control unit 04 comprises a first capacitor C1, a first plate of the first capacitor C1 is connected to the third node N3, and a second plate receives the first control signal a 1. The fourth control unit 04 further includes a first transistor M1, the source of the first transistor M1 receives the first control signal a1, the drain of the first transistor M1 is connected to the second plate of the first capacitor C1, and the gate of the first transistor M1 receives the second control signal a 2. In this embodiment, the first control signal A1 and the second control signal A2 are the same signal. In the first time period, the first control signal a1 is a low level signal, and the second control signal a2 controls the first transistor M1 to be turned on. Fig. 24 is a timing diagram of the circuit configuration shown in fig. 23. This is described in detail below with reference to fig. 23 and 24.

First stage T1: the input signal IN is at a high level, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the fourth transistor M4 is turned on, the first node N1 is at a high level, the seventh transistor M7 is turned on, the fourth node N4 is at a low level, the first control signal a1 is at a high level, the third node N3 is kept at a low level, the second node N2 is at a high level, the eleventh transistor M11 is turned off, and the output signal OUT is kept outputting at a low level.

Second stage T2: the input signal IN is at a high level, the first control signal a1 is at a low level, the second clock signal CK2 is at a high level, the first node N1 is at a high level, the fourth node N4 is at a low level, the second transistor M2 is turned on, the third node N3 is at a high level, the second node N2 is at a high level, and the output signal OUT remains at a low level.

Third stage T3: the input signal IN is at a high level, the second clock signal CK2 is at a low level, the first node N1 is at a high level, the third node N3 is at a high level, the fourth node N4 is at a low level, the second node N2 is at a low level, the eleventh transistor M11 is turned on, and the output signal OUT is at a high level.

Fig. 25 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and as shown IN fig. 25, the first control unit 01 includes a fourth transistor M4, a source of the fourth transistor M4 receives the input signal IN, a drain of the fourth transistor M4 is connected to the first node N1, and a gate of the fourth transistor M4 receives the first clock signal CK 1. The second control unit 02 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a third capacitor C3, and a fourth capacitor C4. The source of the fifth transistor M5 receives the first clock signal CK1, the drain is connected to the fourth node N4, and the gate is connected to the first node N1. The sixth transistor M6 has a source receiving the second clock signal CK2, a drain connected to the fifth node N5, and a gate connected to the fourth node N4. The seventh transistor M7 has a source receiving the first voltage signal Vgl, a drain connected to the fourth node N4, and a gate receiving the first clock signal CK 1. The eighth transistor M8 has a source receiving the second voltage signal Vgh, a drain connected to the second node N2, and a gate connected to the first node N1. The ninth transistor M9 has a source connected to the fifth node N5, a drain connected to the second node N2, and a gate receiving the second clock signal CK 2. The first plate of the third capacitor C3 is connected to the fourth node N4, and the second plate is connected to the fifth node N5. The first plate of the fourth capacitor C4 receives the second voltage signal Vgh, and the second plate is connected to the second node N2. The third control unit 03 includes a tenth transistor M10, an eleventh transistor M11, and a fourth capacitor C4. The tenth transistor M10 has a source receiving the first voltage signal Vgl, a drain outputting the output signal OUT, and a gate connected to the third node N3. The eleventh transistor M11 has a source receiving the second voltage signal Vgh, a drain outputting the output signal OUT, and a gate connected to the second node N2. The fourth control unit 04 includes a first capacitor C1, a first transistor M1, a second capacitor C2, and a third transistor M3. The first plate of the first capacitor C1 is connected to the third node N3, and the second plate receives the first control signal a 1. The first transistor M1 has a source receiving the first control signal a1, a drain connected to the second plate of the first capacitor C1, and a gate receiving the second control signal a 2. The first plate of the second capacitor C2 is connected to the gate of the first transistor M1, and the second plate receives the second voltage signal Vgh. The gate of the first transistor M1 is connected to the first node N1, i.e., the second control signal a2 is a potential signal of the first node N1. The source of the third transistor M3 receives the second voltage signal Vgh, the drain is connected to the third node N3, and the gate is connected to the second node N2; in this embodiment, the first clock signal CK1 is the same as the first control signal A1. In the first time period X1, the first control signal a1 is a low level signal, the second control signal a2 controls the first transistor M1 to turn on, and the second node N2 controls the third transistor M3 to turn off. For example, referring to the introduction of fig. 18, the timing sequence of the circuit configuration shown in fig. 25 is compared with the scheme shown in fig. 17 and fig. 18, the embodiment of the present invention can utilize the potential of the second node N2 to control the potential of the third node N3, and ensure that the signal of the third node N3 is stable at a high level. Since each clock signal or the like makes a plurality of transitions, the potentials of the first node N1 and the third node N3 may be floated during the transition. The embodiment of the utility model provides a set up third transistor M3, when second node N2 is the low level, third transistor M3 switches on, controls the third node and stabilizes at the high level. The third transistor M3 is turned off before the second node N2 becomes a high level, the level of the third node N3 does not change, and the third node N3 becomes a lower potential than the first voltage signal Vgl only when the second node N2 becomes a high level, thereby reducing the tailing phenomenon.

Optionally, the first control signal and the first clock signal are pulse signals with different time sequences, and the first control signal and the second clock signal are pulse signals with different time sequences; the effective pulses of the first clock signal, the first control signal and the second clock signal are generated in sequence. See, for example, fig. 20, 22 and 24.

Optionally, the time length of the effective pulse of the first clock signal is less than or equal to the time length of the effective pulse of the second clock signal, and the time length of the effective pulse of the first control signal is less than or equal to the time length of the effective pulse of the second clock signal. See, for example, fig. 20, 22 and 24.

Optionally, the time length of the effective pulse of the first control signal is less than or equal to the time length of the effective pulse of the first clock signal. The first clock signal needs to participate in the driving process of the first control unit, the second control unit and the third control unit, and the first control signal only needs to control the fourth control unit, so that the time length of the effective pulse of the first control signal can be set to be less than or equal to the time length of the effective pulse of the first clock signal in order to save the time of the effective pulse and save the power consumption.

Optionally, the sum of the time lengths of the active pulses of the first clock signal and the active pulses of the first control signal is equal to or greater than the time length of the active pulses of the second clock signal. The first clock signal and the first control signal control the potential variation of the first node and the third node N3 together, and the second clock signal controls the potential variation of the second node N2. In some embodiments of the present invention, the sum of the effective pulses of the first clock signal and the first control signal may be set equal to the effective pulse of the second clock signal. If the potential of the third node N3 is pulled down for at least the first period when the first node is at the low level, the effective pulse time of the first control signal can be increased appropriately to ensure that the output signal of the shift register has no tailing.

Optionally, the active pulses of the first clock signal at least partially overlap with the active pulses of the first control signal. The effective pulse of the first clock signal and the effective pulse of the first control signal can be partially overlapped, and on the premise that the driving period is not changed, the effective pulse of the first clock signal and the effective pulse of the first control signal can be properly increased so as to ensure that the potentials of the first node and the third node are stably controlled.

Optionally, the on time of the effective pulse of the first clock signal is earlier than the on time of the effective pulse of the first control signal; the end time of the active pulse of the first clock signal is earlier than or the same as the end time of the active pulse of the first control signal. Since it is necessary to continuously pull down the potential of the first node N1 by the fourth control unit 04 after the first node N1 changes from the high level to the low level, it is necessary that the on time of the active pulse of the first clock signal is earlier than the on time of the active pulse of the first control signal. The embodiment of the utility model provides a set up the effective pulse's of first clock signal end time earlier than or be the same as the effective pulse end time of first control signal, can guarantee in the first node electric potential is the at least first time quantum of low level, the electric potential pull-down of fourth the third N3 node of continuous control of control unit. If the end time of the active pulse of the first clock signal is later than the end time of the active pulse of the first control signal, the potential of the third node may be changed back to the potential of the first node before the potential of the first node is pulled down.

Optionally, there may be no overlap between the active pulse of the first control signal and the active pulse of the first clock signal according to the actual product requirement, for example, fig. 20, fig. 22 and fig. 24.

Optionally, in a shifting process from the input signal to the output signal to complete one invalid pulse, an invalid pulse of the input signal starts a time earlier than a start time of an effective pulse of the first clock signal by a first interval time, and a valid pulse of the first clock signal starts a time earlier than a start time of an effective pulse of the first control signal by a second interval time; wherein the first interval time is equal to the second interval time. For example, referring to fig. 20, the inactive pulse of the input signal IN is at a high level, and the on time of the inactive pulse of the input signal IN is earlier than the on time of the active pulse (low level) of the first clock signal CK1 by a first interval time t 1. The on time of the active pulse (low level) of the first clock signal CK1 is earlier than the on time of the active pulse of the first control signal a1 by the second interval time t 2. Due to the control of the first control signal a1, the output signal OUT changes from high level to low level only when the active pulse of the first control signal a1 is turned on, the falling edge of the output signal OUT is delayed by a second interval time t2, and the second interval time t2 is the difference between the on time of the active pulse (low level) of the first clock signal CK1 and the on time of the active pulse of the first control signal a 1. Therefore, the rising edge of the input signal IN is earlier than the falling edge of the first clock signal CK1 by the first time interval t1, and the first time interval t1 is equal to the second time interval t2, so that the invalid pulse widths of the input signal IN and the output signal OUT are equal and the waveforms are consistent.

Optionally, during the first time period, the second clock signal outputs an invalid pulse. For example, referring to fig. 20, in the first time period X1 before the second clock signal CK2 outputs a valid pulse (low level), the third node N3 is pulled down to a lower potential than the first voltage signal Vgl, so as to eliminate the tailing phenomenon as much as possible.

Optionally, the time period in which the first node receives the low level signal further includes a second time period X2, in the first time period X1, the potential of the third node is the first low level signal, and in the second time period X2, the potential of the third node is the high level signal. For example, referring to fig. 20, 22 and 24, when the first clock signal CK1 is low level and the first control signal a1 is high level in the second period X2, the third node N3 is also a high level signal. During a first period X1 after the first control signal a1 becomes a low level, the third node N3 is pulled down to a lower potential than the first voltage signal Vgl, thereby eliminating a tailing phenomenon.

Based on the same utility model conception, the embodiment of the utility model also provides a display device. This display device includes the utility model discloses any embodiment display panel, consequently, the utility model provides a display device possesses the utility model provides a corresponding beneficial effect of display panel, no longer repeated here. For example, the display device may be an electronic device such as a mobile phone, a computer, a smart wearable device (e.g., a smart watch), and an on-vehicle display device, and the embodiment of the present invention is not limited thereto. For example, fig. 26 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 26, the display device includes the display panel 100 in the above-described embodiment.

It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims

1. A display panel, comprising:

the shift register includes:

2. The display panel according to claim 1,

the fourth control unit comprises a first capacitor, a first pole plate of the first capacitor is connected to the third node, and a second pole plate receives a first control signal; wherein the content of the first and second substances,

in the first time period, the first control signal is a low level signal.

3. The display panel according to claim 2,

the fourth control unit comprises a first transistor, the source electrode of the first transistor receives the first control signal, the drain electrode of the first transistor is connected with the second plate of the first capacitor, and the grid electrode of the first transistor receives the second control signal; wherein the content of the first and second substances,

and in the first time period, the second control signal controls the first transistor to be switched on.

4. The display panel according to claim 3, wherein the first control signal and the second control signal are the same signal.

5. The display panel according to claim 3, wherein the first clock signal and the first control signal are the same signal.

6. The display panel according to claim 3, wherein the second control signal is a signal of the first node.

7. The display panel according to claim 6, wherein the fourth control unit further comprises a second capacitor, a first plate of the second capacitor is connected to the gate of the first transistor, and a second plate of the second capacitor receives the second voltage signal.

8. The display panel according to claim 7, wherein a capacitance value of the first capacitor is smaller than a capacitance value of the second capacitor.

9. The display panel according to claim 3, wherein the fourth control unit comprises a second transistor, a source of the second transistor is connected to the first node, a drain of the second transistor is connected to the third node, and a gate of the second transistor receives the first control signal; wherein the content of the first and second substances,

the first control signal controls the second transistor to be turned on in the first time period.

10. The display panel according to claim 3,

the fourth control unit comprises a third transistor, wherein the source electrode of the third transistor receives the second voltage signal, the drain electrode of the third transistor is connected to the third node, and the grid electrode of the third transistor is connected to the second node; wherein the content of the first and second substances,

the second node controls the third transistor to turn off during the first period.

11. The display panel according to claim 3,

the first control signal and the first clock signal are pulse signals with different time sequences, and

the first control signal and the second clock signal are pulse signals with different time sequences; wherein the content of the first and second substances,

the effective pulses of the first clock signal, the first control signal and the second clock signal are generated in sequence.

12. The display panel according to claim 11,

the time length of the active pulses of the first clock signal is less than or equal to the time length of the active pulses of the second clock signal, and,

the time length of the effective pulse of the first control signal is less than or equal to the time length of the effective pulse of the second clock signal.

13. The display panel according to claim 11,

the time length of the effective pulse of the first control signal is less than or equal to the time length of the effective pulse of the first clock signal.

14. The display panel according to claim 11,

the sum of the time lengths of the effective pulses of the first clock signal and the effective pulses of the first control signal is equal to or greater than the time length of the effective pulses of the second clock signal.

15. The display panel according to claim 11,

the active pulses of the first clock signal and the active pulses of the first control signal at least partially overlap.

16. The display panel according to claim 15,

the on time of the effective pulse of the first clock signal is earlier than the on time of the effective pulse of the first control signal;

the end time of the effective pulse of the first clock signal is earlier than or equal to the end time of the effective pulse of the first control signal.

17. The display panel according to claim 11,

there is no overlap between the active pulses of the first control signal and the active pulses of the first clock signal.

18. The display panel according to claim 11,

during the shifting process from the input signal to the output signal to complete one invalid pulse, the on time of the invalid pulse of the input signal is earlier than the on time of the valid pulse of the first clock signal by a first interval time, and the on time of the valid pulse of the first clock signal is earlier than the on time of the valid pulse of the first control signal by a second interval time; wherein the content of the first and second substances,

the first interval time is equal to the second interval time.

19. The display panel according to claim 1,

during the first time period, the second clock signal outputs an invalid pulse.

20. The display panel according to claim 1,

the time period for the first node to receive the low level signal further includes a second time period, in the first time period, the potential of the third node is the first low level signal, and in the second time period, the potential of the third node is the high level signal.

21. The display panel according to claim 7,

the first control unit includes:

a fourth transistor, a source of which receives the input signal, a drain of which is connected to the first node, and a gate of which receives the first clock signal;

the second control unit includes:

a fifth transistor, a source of which receives the first clock signal, a drain of which is connected to a fourth node, and a gate of which is connected to the first node;

a sixth transistor, a source of which receives the second clock signal, a drain of which is connected to a fifth node, and a gate of which is connected to the fourth node;

a seventh transistor, wherein a source of the seventh transistor receives the first voltage signal, a drain of the seventh transistor is connected to the fourth node, and a gate of the seventh transistor receives the first clock signal;

a source of the eighth transistor receives the second voltage signal, a drain of the eighth transistor is connected to the second node, and a gate of the eighth transistor is connected to the first node;

a ninth transistor, a source of which is connected to the fifth node, a drain of which is connected to the second node, and a gate of which receives the second clock signal;

a third capacitor, wherein a first plate of the third capacitor is connected to the fourth node, and a second plate of the third capacitor is connected to the fifth node;

a fourth capacitor, a first plate of which receives the second voltage signal and is connected to the second node;

the third control unit includes:

a tenth transistor, a source of which receives the first voltage signal, a drain of which outputs an output signal, and a gate of which is connected to the third node;

and the source electrode of the eleventh transistor receives the second voltage signal, the drain electrode of the eleventh transistor outputs an output signal, and the grid electrode of the eleventh transistor is connected to the second node.

22. The display panel according to claim 21,

the capacitance value of the first capacitor is smaller than the capacitance value of the third capacitor, or,

the capacitance value of the first capacitor is smaller than that of the fourth capacitor.

23. A display device characterized by comprising the display panel according to any one of claims 1 to 22.