CN214540775U - Evaluation circuit and microsystem of equivalent load of signal interconnection line in multi-chip package - Google Patents

Abstract

The utility model relates to a multi-chip package technical field, concretely relates to evaluation circuit and microsystem of signal interconnection line equivalent load in multi-chip package. The circuit includes: the first analog circuit comprises a target signal interconnection line in the multi-chip package and is used for acquiring a target analog semaphore of the target signal interconnection line; the second analog circuit comprises an adjustable capacitor and is used for acquiring capacitance analog signal quantities of the adjustable capacitor under different capacitance values; and the signal comparison module is used for acquiring a comparison result of the target analog semaphore and the capacitance analog semaphore. The utility model discloses first analog circuit has been found to second analog circuit has been found based on adjustable electric capacity, later utilize the difference of signal comparison module comparison electric capacity analog signal volume and target analog signal volume, can be with the current capacitance value of adjustable electric capacity at last, the equivalence does the load of target signal interconnect line, thereby accurately appraised the signal interconnection load in the multi-chip package.

Description

Evaluation circuit and microsystem of equivalent load of signal interconnection line in multi-chip package

Technical Field

The utility model relates to a multi-chip package technical field, concretely relates to evaluation circuit and microsystem of signal interconnection line equivalent load in multi-chip package.

Background

Multi-chip package (multi-chip package) is a package that integrates a plurality of chips with different sizes, different manufacturing processes, and different materials into a package, including stacking 2D, 2.5D, 3D chips, and is applied to advanced mobile communication/computing and high bandwidth memory systems.

Fig. 1 is a schematic diagram of a typical microsystem composed of 3D multi-chip packages, where 2 chips dieA and dieB for implementing different functions are included, a signal interconnection connector (e.g., TSV, hybrid Bonding Wire, etc.) can implement electrical connection between the dieA and the dieB, and a signal interconnection (e.g., common Bonding Wire, Solder Bump, etc.) implements electrical connection between the chips and the outside through metal traces in a package base substrate.

FIG. 2 is a schematic diagram of the microsystem of FIG. 1, wherein the dieA is composed of a core circuit dieA _ core and an input/output circuit IOA, and implements functions such as control, computation, etc.; a dieB, which is composed of a core circuit dieB _ core and an input/output circuit IOB, and implements functions such as storage, digital/analog conversion, data exchange, etc.); the signal interconnection line realizes the physical electrical connection of the input and output signals IO _1 to IO _ n.

Therefore, the signal interconnection line is used as a bridge between the input and output circuits of each chip, and the size of the equivalent load directly affects the signal integrity of the input and output signals (especially high-speed signals) and the power integrity of the chip, so it is important to accurately evaluate the signal interconnection load.

Currently, the equivalent load value of the signal interconnection line is generally provided by a packaging factory, and after modeling is performed by an EDA tool, an approximate value range is provided for a user. Because the accurate equivalent load value of the signal interconnection line cannot be obtained, the multi-chip package cannot be applied to some application scenes with higher precision requirements.

Therefore, how to accurately evaluate the signal interconnection load in the multi-chip package is a technical problem that needs to be solved at present.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing an evaluation circuit and microsystem of signal interconnection line equivalent load in the multi-chip package to accurately assess out the signal interconnection load in the multi-chip package.

In order to achieve the above object, the embodiment of the present invention provides the following solutions:

in a first aspect, an embodiment of the present invention provides an evaluation circuit for equivalent load of a signal interconnection line in a multi-chip package, including:

the first analog circuit comprises a target signal interconnection line in a multi-chip package and is used for acquiring a target analog semaphore of the target signal interconnection line;

the second analog circuit comprises an adjustable capacitor and is used for acquiring capacitance analog signal quantities of the adjustable capacitor under different capacitance values;

and the signal comparison module is used for acquiring a comparison result of the target analog semaphore and the capacitance analog semaphore so as to equate the capacitance value of the current adjustable capacitor as the load of the target signal interconnection line when the difference between the capacitance analog semaphore and the target analog semaphore is smaller than a set threshold value.

In one possible embodiment, the target signal interconnection line includes a signal interconnection line between any two chips in the multi-chip package and/or a signal interconnection line between any one chip and a package base.

In one possible embodiment, the first analog circuit is a first oscillating circuit; the target signal interconnection line is the first oscillating circuit capacitor;

the second analog circuit is a second oscillating circuit; wherein the adjustable capacitor is the second oscillating circuit capacitor.

In one possible embodiment, the first analog circuit is a first ring oscillator; the second analog circuit is a second ring oscillator.

In one possible embodiment, the target signal interconnect line includes at least one set of signal interconnect line combinations; each group of signal interconnection line combination comprises two signal interconnection lines which are connected in series;

the first and second ring oscillators are disposed in a common ring oscillator;

the common ring oscillator comprises a delay module and a NAND gate logic circuit; the output end of the NAND gate logic circuit is connected with the input end of the delay module; the output end of the delay module is connected with the input end of the NOT gate logic circuit;

the delay module comprises at least one delay unit; each group of signal interconnection line combination corresponds to one delay unit;

the delay unit comprises an input buffer, a first selector, a second selector and an output buffer;

the output end of the output buffer is connected with the input end of the first selector; the first output end of the first selector is connected with the first input end of the second selector through the signal interconnection line combination corresponding to the delay unit; the second output end of the first selector and the second input end of the second selector are both grounded through the adjustable capacitor; the output end of the second selector is connected with the input end of the output buffer;

the common ring oscillator further comprises: a first buffer and a frequency divider;

the output end of the NAND gate logic circuit is connected with the input end of the frequency divider through the first buffer.

In a possible embodiment, the first analog circuit is a first charge-discharge circuit; the target signal interconnection line is a charge-discharge capacitor of the first charge-discharge circuit;

the second analog circuit is a second charge-discharge circuit; the adjustable capacitor is a charge-discharge capacitor of the charge-discharge circuit.

In a possible embodiment, the first charge-discharge circuit includes a first current source, a first MOS transistor, a second MOS transistor, and a first capacitor; the second charge-discharge circuit comprises a second current source, a third MOS (metal oxide semiconductor) tube, a fourth MOS tube and a second capacitor;

the first current source is grounded through the first MOS tube, the target signal interconnection line and the first capacitor; the target signal interconnection line is also grounded through the second MOS tube;

the second current source is grounded through the third MOS tube and the adjustable capacitor; the fourth MOS tube and the second capacitor are both connected with the adjustable capacitor in parallel;

the grid electrode of the first MOS tube is respectively connected with the grid electrode of the second MOS tube, the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube;

the channel types of the first MOS tube and the second MOS tube are different; the channel types of the third MOS tube and the fourth MOS tube are different; the channel types of the first MOS tube and the third MOS tube are the same.

In a possible embodiment, the signal comparison module comprises a comparator and a D flip-flop;

a first input end of the comparator is connected with a drain electrode of the first MOS tube; the second input end of the comparator is connected with the drain electrode of the third MOS tube; the output end of the comparator is connected with the D end of the D trigger; and the grid electrode of the first MOS tube is connected with the CP end of the D trigger through an inverter.

In a second aspect, an embodiment of the present invention provides a multi-chip packaged microsystem, including: the evaluation circuit of any of the first aspects; wherein the evaluation circuit is disposed in any one chip of a multi-chip packaged microsystem.

Compared with the prior art, the utility model, following advantage and beneficial effect have:

the utility model discloses according to the actual size of signal interconnection line, be equivalent for equivalent capacitance with its true load, because equivalent capacitance is less, direct measurement is comparatively difficult, the utility model discloses in based on the target signal interconnection line has found first analog circuit, a target analog semaphore for acquireing the target signal interconnection line, and based on adjustable electric capacity has found second analog circuit, be used for acquireing the electric capacity analog semaphore of adjustable electric capacity under different capacitance values, later utilize the difference of signal comparison module comparison electric capacity analog semaphore and target analog semaphore, can be less than the capacitance value of the adjustable electric capacity when setting for the threshold value with the difference of electric capacity analog semaphore and target analog semaphore at last, the equivalence does the load of target signal interconnection line to accurately appraise the signal interconnection load in the multi-chip package.

Drawings

In order to more clearly illustrate the embodiments of the present specification or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present specification, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a typical microsystem consisting of a 3D multi-chip package;

FIG. 2 is a schematic diagram of the microsystem of FIG. 1;

fig. 3 is a schematic connection diagram of an evaluation circuit for an equivalent load of a signal interconnection line in a multi-chip package according to an embodiment of the present invention;

FIG. 4 is a schematic view of the working principle of FIG. 3;

fig. 5 is a schematic connection diagram of a common ring oscillator according to an embodiment of the present invention;

fig. 6 is a schematic connection diagram of a delay unit according to an embodiment of the present invention;

FIG. 7 is a waveform schematic diagram of the operation of the common ring oscillator of FIG. 5;

fig. 8 is a schematic connection diagram of an evaluation circuit for equivalent load of a signal interconnection line in a multi-chip package according to an embodiment of the present invention;

FIG. 9 is a waveform diagram illustrating the operation of the evaluation circuit for the equivalent load of the signal interconnect line in the multi-chip package of FIG. 8;

fig. 10 is a flowchart of a method for acquiring a load of a signal interconnection line according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of an apparatus for acquiring a load of a signal interconnection line according to an embodiment of the present invention;

fig. 12 is a schematic diagram of a multi-chip packaged micro system according to an embodiment of the present invention.

Description of reference numerals: 110 is a first analog circuit, 111 is a target signal interconnection line, 112 is a signal interconnection line combination, 120 is a second analog circuit, 121 is an adjustable capacitor, 130 is a signal comparison module, 210 is a delay module, 220 is a nand gate logic circuit, 230 is a first buffer, 240 is a frequency divider, 310 is a delay unit, 311 is an input buffer, 312 is a first selector, 313 is a second selector, 314 is an output buffer, It is a first current source, Ir is a second current source, M1 is a first MOS transistor, M2 is a second MOS transistor, M3 is a third MOS transistor, M4 is a fourth MOS transistor, Ctb is a first capacitor, Crb is a second capacitor, 411 is a comparator, and 412 is a D flip-flop.

Detailed Description

The technical solution in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by those skilled in the art based on the embodiments of the present invention belong to the protection scope of the embodiments of the present invention.

Referring to fig. 3, fig. 3 is a schematic connection diagram of an evaluation circuit for an equivalent load of a signal interconnection line in a multi-chip package according to an embodiment of the present invention, the circuit includes: a first analog circuit 110, a second analog circuit 120 and a signal comparison module 130.

The first analog circuit 110 includes a target signal interconnection line 111 in a multi-chip package, and is configured to obtain a target analog signal amount of the target signal interconnection line 111.

Specifically, the signal interconnection line in the multi-chip package may be a connection line between a plurality of chips, or a connection line between a chip and a package case. Here, the chip may be a packaged chip, or may be a bare chip (i.e., a chip that has not been packaged after a wafer is produced, cut, and tested by a fabrication plant). The target signal interconnect line may be one or more signal interconnect lines in a multi-chip package for which a load needs to be detected.

Here, since the actual size of the signal interconnection line is on the order of nanometers to micrometers, the equivalent resistance and the equivalent inductance thereof are very small, and thus the equivalent load of the signal interconnection line can be regarded as the equivalent capacitance. In this embodiment, the first analog circuit 110 is constructed based on the equivalent capacitor, and is used to obtain an analog semaphore representing the magnitude of the equivalent capacitor.

Specifically, the target analog signal amount may be in an analog quantity form of current, voltage, or frequency, and correspondingly, the first analog circuit 110 may employ an RC oscillation circuit to obtain an oscillation signal of the equivalent capacitor corresponding to the signal interconnection line, may also employ a capacitor charge-discharge circuit to obtain a charge voltage or a discharge voltage of the equivalent capacitor corresponding to the signal interconnection line, may also employ a ring oscillator to obtain an oscillation signal frequency corresponding to the equivalent capacitor corresponding to the signal interconnection line, and of course, the first analog circuit 110 in this embodiment may also be constructed by using other analog circuits based on a capacitor to achieve the purpose of obtaining the target analog signal amount of the target signal interconnection line 111, and a specific implementation manner is not limited herein.

The second analog circuit 120 includes an adjustable capacitor 121, and is configured to obtain capacitance analog signal quantities of the adjustable capacitor 121 at different capacitance values.

Specifically, the adjustable capacitor 121 is provided with a control end, and when the adjustable capacitor 121 receives an instruction to adjust the capacitance value, the adjustable capacitor 121 may adjust the capacitance according to the instruction.

The capacitance analog signal quantity may adopt analog quantity forms such as current, voltage, or frequency, and correspondingly, the second analog circuit 120 may adopt a capacitance charge-discharge circuit to obtain a charge voltage or a discharge voltage of the adjustable capacitor 121, and may also adopt a ring oscillator to obtain an oscillation signal frequency corresponding to the adjustable capacitor 121, and of course, other capacitance-based analog circuits may also be adopted to construct the second analog circuit 120 in this embodiment to achieve the purpose of obtaining the capacitance analog signal quantity of the adjustable capacitor 121 under different capacitance values, and a specific implementation manner is not limited herein.

The signal comparison module 130 is configured to obtain a comparison result between the target analog semaphore and the capacitor analog semaphore, so that when a difference between the capacitor analog semaphore and the target analog semaphore is smaller than a set threshold, a capacitance value of the current adjustable capacitor is equivalent to a load of the target signal interconnection line 111.

In practical applications, the signal comparison module 130 may be configured according to the analog semaphore type obtained by the first analog circuit 110 and the second analog circuit 120. If the analog semaphore type is in voltage form, the signal comparison module 130 can be implemented by using a comparator 411 circuit; if the analog semaphore type is in a frequency form, the frequency value can be directly obtained to realize the function of the signal comparison module 130; of course, the analog signal quantities obtained by the first analog circuit 110 and the second analog circuit 120 may also be directly output to an oscilloscope, so that the oscilloscope is utilized to obtain the comparison result between the target analog signal quantity and the capacitance analog signal quantity, and the specific implementation manner of the signal comparison module 130 is not limited herein.

When the capacitance value of the adjustable capacitor 121 is properly adjusted, and the difference between the capacitance analog semaphore and the target analog semaphore is smaller than a set threshold, the load corresponding to the current adjustable capacitor 121 is equivalent to the equivalent load of the target signal interconnection line 111.

Here, the difference between the capacitance analog signal amount and the target analog signal amount may be in a form of a ratio, or may also be in a form of a difference between the analog signal amounts, and the corresponding set threshold may be flexibly selected according to an actual situation.

The working principle of the embodiment is as follows:

as shown in fig. 4, which is a schematic diagram of the operation principle of fig. 3, the first analog circuit 110 can obtain a target analog signal quantity of the target signal interconnection line 111, the second analog circuit 120 can obtain a capacitance analog signal quantity of the adjustable capacitor 121 under different capacitance values, and the signal comparison module 130 can obtain a comparison result between the target analog signal quantity and the capacitance analog signal quantity, so that a controller (for example, a certain chip in a multi-chip package, or an upper computer outside the multi-chip package) can issue a capacitance adjustment instruction according to the comparison result, and adjust the capacitance value of the adjustable capacitor 121 until a difference between the capacitance analog signal quantity and the target analog signal quantity is smaller than a set threshold.

In this embodiment, the target analog semaphore of the target signal interconnection line 111 is represented as an equivalent load of the target signal interconnection line 111, and when a difference between the capacitance analog semaphore of the adjustable capacitor 121 and the representation of the target analog semaphore of the target signal interconnection line 111 is small, the equivalent load of the target signal interconnection line 111 can be represented through the current adjustable capacitor 121, so that accurate estimation of the equivalent load of the target signal interconnection line 111 in multi-chip packaging is achieved.

In a multi-chip package, the target signal interconnection line 111 may be a signal interconnection line between any two chips in the multi-chip package, or may be a signal interconnection line between any one chip in the multi-chip package and a package base, which is not limited herein.

In practical applications, the first analog circuit 110 may be a first oscillating circuit; the target signal interconnection line 111 is a first oscillation circuit capacitor; and the second analog circuit 120 is a second oscillating circuit; the adjustable capacitor 121 is a second oscillating circuit capacitor.

Of course, the oscillation generator may also be a ring oscillator, and the first analog circuit 110 may be a first ring oscillator; the second analog circuit 120 may be a second ring oscillator, and the output oscillation signal is a frequency signal.

In order to simplify the structure of the first analog circuit 110 and the second analog circuit 120 and reduce the circuit size, the present embodiment further provides a simplification scheme of the first ring oscillator and the second ring oscillator, and particularly, the first ring oscillator and the second ring oscillator are disposed in a common ring oscillator to reduce the device size. The specific scheme is as follows:

the target signal interconnect line 111 may include at least one set of signal interconnect line combinations 112; wherein each group of signal interconnection line combinations 112 comprises two signal interconnection lines connected in series.

Specifically, because the equivalent capacitance corresponding to a single signal interconnection line is too small, the target signal interconnection line 111 can select a plurality of signal interconnection lines to increase the equivalent capacitance of the target signal interconnection line 111, reduce the oscillation frequency output by the ring oscillator, and facilitate the test. Because the evaluation circuit is arranged in one chip in the multi-chip packaged micro system, the signal interconnection line in the target signal interconnection line 111 can be divided into a plurality of (more than or equal to one) signal interconnection line combinations 112, and the signal interconnection lines in each signal interconnection line combination 112 are grouped in pairs and integrally connected in series, so that the input end and the output end of each signal interconnection line combination 112 are positioned on one side, and the wiring is convenient.

Fig. 5 is a schematic connection diagram of a common ring oscillator according to an embodiment of the present invention, wherein the common ring oscillator includes a delay module 210 and a nand gate logic circuit 220.

Specifically, the output end of the nand gate logic circuit 220 is connected to the input end of the delay module 210; the output end of the delay module 210 is connected to the input end of the not gate logic circuit; thus, the inverted signal output by the nand gate logic circuit 220 is delayed by the delay module 210, returns to the input terminal of the nand gate logic circuit 220 again, and is inverted and output by the nand gate logic circuit 220 again, so that a clock frequency signal is formed at the output terminal of the nand gate logic circuit 220.

The delay module 210 includes at least one delay unit 310; each group of signal interconnect line combinations 112 corresponds to one delay unit 310. As shown in fig. 6, which is a schematic diagram of a connection of the delay unit 310 according to an embodiment of the present invention, the delay unit 310 includes an input buffer 311, a first selector 312, a second selector 313, and an output buffer 314; an output terminal of the output buffer 314 is connected to an input terminal of the first selector 312; a first output terminal of the first selector 312 is connected to a first input terminal of the second selector 313 through the corresponding signal interconnection line combination 112 of the delay unit 310; a second output terminal of the first selector 312 and a second input terminal of the second selector 313 are both grounded through an adjustable capacitor; an output terminal of the second selector 313 is connected to an input terminal of the output buffer 314. The first ring oscillator and the second ring oscillator can be switched by the control of the first selector and the second selector in the delay unit.

The common ring oscillator further comprises: a first buffer 230 and a frequency divider 240; the output of the nand gate logic 220 is connected to the input of the frequency divider 240 via the first buffer 230. In this way, the frequency of the clock frequency signal output by the nand gate logic circuit 220 is further reduced by the first buffer 230 and the frequency divider 240, which facilitates the comparison and analysis of the clock frequency signal.

Fig. 7 is a waveform diagram illustrating an operation process of the common ring oscillator shown in fig. 5, where EN is an enable signal of the common ring oscillator, and EV _ CTRL is a selection signal of a device to be evaluated (when EV _ CTRL is equal to 0, the target signal interconnection line 111 is selected, and when EV _ CTRL is equal to 1, the adjustable capacitor 121 is selected).

The specific operation process of the common ring oscillator shown in fig. 5 is as follows:

1, t 0-t 1: pulling up an enable signal EN, and starting the ring oscillator to work; at this time, EV _ CTRL is low, and target signal interconnection line 111 is selected as the device under test; the clock frequency of the output signal EV _ OUT is fref;

2, t 1-t 2: the EV _ CTRL is pulled high, and the internal adjustable capacitor 121 is selected as a device to be tested; at this time, the value corresponding to CFGCAP < K:0> is 1, the clock frequency of the output EV _ OUT is fcon _1, and fcon _1 is greater than fref;

3, t 2-t 3: continuously configuring the corresponding value of the CFGCAP < K:0> signal as 2, wherein the clock frequency of the output EV _ OUT is fcon _2, and fcon _2 is greater than fref;

t 3-t 5: continuously configuring the value corresponding to the CFGCAP < K:0> signal as j (3< ═ j < ^ 2^ K), outputting the clock frequency of EV _ OUT as fcon _ j, comparing the magnitudes of fcon _ j and fref until the magnitudes are equal or close to each other, and recording the value corresponding to the CFGCAP < K:0> signal at the moment as eq;

and 5, t5, pulling down the enable signal EN, stopping the ring oscillator, finishing the equivalent load evaluation process of the whole signal interconnection line, and keeping the CFGCAP < K:0> signal at the corresponding value eq.

If not, returning to the step 4, continuing to configure CFGCAP < K:0> until Rref and Rcon are equal, storing the corresponding value of the control signal CFGCAP < K:0> at the moment, and finishing the evaluation.

At this time, the capacitance of the tunable capacitor 121 corresponding to the control signal CFGCAP < K:0> is regarded as the equivalent capacitance of the target signal interconnection line 111.

Of course, in practical applications, the first analog circuit 110 and the second analog circuit 120 may also be implemented by using a capacitor charging and discharging circuit. At this time, the first analog circuit 110 is a first charge-discharge circuit; the target signal interconnection line 111 is a charge-discharge capacitor of the first charge-discharge circuit; the second analog circuit 120 is a second charge-discharge circuit; the adjustable capacitor 121 is a capacitor of a charge-discharge circuit.

Fig. 8 is a schematic diagram illustrating a connection of an evaluation circuit for an equivalent load of a signal interconnection line in a multi-chip package according to an embodiment of the present invention, specifically:

the first charge-discharge circuit comprises a first current source It, a first MOS tube M1, a second MOS tube M2 and a first capacitor Ctb; the second charge-discharge circuit comprises a second current source Ir, a third MOS tube M3, a fourth MOS tube M4 and a second capacitor Crb; the first current source It is grounded through the first MOS transistor M1, the target signal interconnection line 111 and the first capacitor Ctb; one end of the target signal interconnection line 111, which is far away from the first capacitor Ctb, is grounded through a second MOS transistor M2; the second current source Ir is grounded through a third MOS tube M3 and the adjustable capacitor; the fourth MOS transistor M4 and the second capacitor Crb are both connected with the adjustable capacitor in parallel; the gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2, the gate of the third MOS transistor M3 and the gate of the fourth MOS transistor M4, respectively.

Specifically, the channel types of the first MOS transistor M1 and the second MOS transistor M2 are different; the channel types of the third MOS transistor M3 and the fourth MOS transistor M4 are different; the channel types of the first MOS transistor M1 and the third MOS transistor M3 are the same. If the first MOS transistor M1 and the third MOS transistor M3 are PMOS transistors, the second MOS transistor M2 and the fourth MOS transistor M4 are NMOS transistors; if the first MOS transistor M1 and the third MOS transistor M3 are NMOS transistors, the second MOS transistor M2 and the fourth MOS transistor M4 are PMOS transistors.

Specifically, the capacitance values of the first capacitor Ctb and the second capacitor Crb may be equal, and the current values output by the first current source It and the second current source Ir may be equal, which facilitates evaluation.

The signal comparison module 130 includes a comparator 411 and a D flip-flop 412; a first input end of the comparator 411 is connected with the drain of the first MOS transistor M1; a second input end of the comparator 411 is connected with the drain of the third MOS transistor M3; the output end of the comparator 411 is connected with the D end of the D flip-flop 412; the gate of the first MOS transistor M1 is connected to the CP terminal of the D flip-flop 412 through an inverter.

Fig. 9 is a waveform diagram illustrating an operation process of the evaluation circuit for an equivalent load of a signal interconnection line in the multi-chip package shown in fig. 8, and the operation process is as follows:

1, t 0-t 1: enabling the enable signal EN to be pulled high, and enabling an evaluation circuit of the equivalent load of the signal interconnection line to start working; configuring the corresponding value of CFGCAP < K:0> as 1; the evaluation control signal EV _ CTRL is pulled high, and the reference current respectively charges the adjustable capacitor 121 and the equivalent load capacitor of the target signal interconnection line; after a period of time Δ T (determined by the EN _ CTRL signal), the evaluation control signal EV _ CTRL is pulled low, the charging is completed, and the comparator 411 compares the voltages vref and vcon on the adjustable capacitor 121 and the equivalent capacitor of the target signal interconnection line, if vref is higher than vcon, the result is latched by the D flip-flop 412 and the output EV _ OUT is low;

2, t 1-t 2: continuously configuring the corresponding value of CFGCAP < K:0> as 2;

3, t 2-t 7, repeating the operation at the stage t 0-t 1 until the output signal EV _ OUT is pulled high, wherein the capacitance values of the adjustable reference capacitor and the equivalent load capacitor of the target signal interconnection line are equal or similar, and the value corresponding to the CFGCAP < K:0> signal is recorded as eq;

and 4, t8, pulling down the enable signal EN, stopping the evaluation circuit, finishing the evaluation process of the equivalent load of the whole signal interconnection line, and keeping the CFGCAP < K:0> signal at the corresponding value eq.

The following beneficial effects exist in the above embodiment:

1. for the packaged chip, the capacitance value of the equivalent load capacitor of the signal interconnection line can be accurately obtained by the embodiment, but not in an approximate range;

2. after the evaluation is completed by the embodiment, the obtained configuration signal CFGCAP < K:0> -eq of the adjustable capacitor 121 can be used for optimizing and configuring the driving capability of each chip output driver, so that a good compromise exists between signal integrity and power integrity.

Based on the same utility model concept as the method, the embodiment of the present invention further provides an obtaining method of the load of the signal interconnection line, and fig. 10 shows a flowchart of the obtaining method. The method is based on any one of the evaluation circuit arrangements, and specifically comprises the following steps:

and step 11, acquiring a target analog semaphore of a target signal interconnection line 111 in the multi-chip package.

Wherein the target analog semaphore comprises a target frequency semaphore, a target voltage semaphore or a target current semaphore.

Step 12, adjusting the capacitance value of the adjustable capacitor 121 to make the difference between the current analog semaphore of the adjustable capacitor 121 and the target analog semaphore smaller than a set threshold, and obtaining the current capacitance value of the adjustable capacitor 121.

And step 13, equating the current capacitance value as the load of the target signal interconnection line 111.

After obtaining the signal interconnection load of the target signal interconnection line 111, the method further includes:

step 21, adjusting the driving capability of the chip corresponding to the target signal interconnection line 111 according to the load of the target signal interconnection line 111.

Based on the same utility model concept with the method, the embodiment of the utility model provides a still provides the acquisition device of the load of signal interconnection line, is the schematic structure diagram of this acquisition device as shown in fig. 11. The device is arranged based on any one of the evaluation circuits, and specifically comprises:

the first obtaining module 31 is configured to obtain a target analog semaphore of a target signal interconnection line 111 in a multi-chip package; wherein the target analog semaphore comprises a target frequency semaphore, a target voltage semaphore or a target current semaphore;

a second obtaining module 32, configured to adjust a capacitance value of the adjustable capacitor 121, so that a difference between a current analog signal quantity of the adjustable capacitor 121 and the target analog signal quantity is smaller than a set threshold, and obtain the current capacitance value of the adjustable capacitor 121;

the third obtaining module 33 is configured to equate the current capacitance value to a load of the target signal interconnection line 111.

In a possible embodiment, the apparatus further comprises:

and the driving capability adjusting module is used for adjusting the driving capability of the chip corresponding to the target signal interconnection line 111 according to the signal interconnection load of the target signal interconnection line 111.

Based on the same utility model conception with the aforesaid embodiment, the embodiment of the utility model provides a microsystem of multi-chip package is still provided, include the above arbitrary evaluation circuit. Wherein the evaluation circuit is disposed in any one chip of a multi-chip packaged microsystem.

Fig. 12 is a schematic diagram of a multi-chip packaged micro-system according to an embodiment of the present invention, which includes 2 chips dieA and dieB for implementing different functions, where the dieA is composed of a core circuit dieA _ core and an input/output circuit IOA, and implements functions such as control and calculation; a dieB, which is composed of a core circuit dieB _ core and an input/output circuit IOB, and implements functions such as storage, digital/analog conversion, data exchange, etc.); the signal interconnection lines 31 to 3n are used for physically and electrically connecting the input and output signals IO _1 to IO _ n.

Compared with fig. 2, an evaluation circuit (Evaluator) of the equivalent load of the signal interconnection line is added (in the embodiment, the evaluation circuit can be flexibly set according to the application scene requirements in practice), a target signal interconnection line array 3ev _ 1-3 ev _ n to be detected, and an adjustable capacitor 121 configure the signal interconnection line 3ev _ 0; the target signal interconnection line arrays 3ev _1 to 3ev _ n are arranged corresponding to the signal interconnection lines 31 to 3 n. CFGCAP < K:0>, EV _ CTRL and EN signals of the evaluation circuit of the equivalent load of the signal interconnection line come from a core circuit dieA _ core, an output signal EV _ OUT of the core circuit is connected to the outside of a chip, and CFGCAP < K:0> is connected to an output driver of the dieA and an output driver of the dieB through a signal interconnection line 3EV _ 0.

Of course, it is also possible to provide one evaluation circuit as described above between every two chips in the memory chip, and also to provide one evaluation circuit as described above between each chip in the memory chip and the package base.

Based on the same concept of the present invention as in the previous embodiments, the embodiments of the present invention further provide a computer system, including a multi-chip packaged microsystem, where the multi-chip packaged microsystem performs the steps of any of the above-described methods.

The embodiment of the utility model provides an in the technical scheme who provides, following technological effect or advantage have at least:

the embodiment of the utility model provides a according to the actual size of signal interconnection line, be equivalent for equivalent capacitance with its true load, because equivalent capacitance is less, direct measurement is comparatively difficult, the utility model discloses in based on the target signal interconnection line has found first analog circuit, be used for acquireing the target analog semaphore of target signal interconnection line, and based on adjustable electric capacity has found second analog circuit, be used for acquireing the electric capacity analog semaphore of adjustable electric capacity under different capacitance values, later utilize the difference of signal comparison module comparison electric capacity analog semaphore and target analog semaphore, can be less than the capacitance value of the adjustable electric capacity when setting for the threshold value with the difference of electric capacity analog semaphore and target analog semaphore at last, the equivalence does the load of target signal interconnection line, thereby accurately appraised the signal interconnection load in the multichip encapsulation.

While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (9)

1. An evaluation circuit for equivalent load of a signal interconnection line in a multi-chip package, comprising:

the first analog circuit comprises a target signal interconnection line in a multi-chip package and is used for acquiring a target analog semaphore of the target signal interconnection line;

the second analog circuit comprises an adjustable capacitor and is used for acquiring capacitance analog signal quantities of the adjustable capacitor under different capacitance values;

and the signal comparison module is used for acquiring a comparison result of the target analog semaphore and the capacitance analog semaphore so as to enable the capacitance value of the current adjustable capacitor to be equivalent to the load of the target signal interconnection line when the difference between the capacitance analog semaphore and the target analog semaphore is smaller than a set threshold value.

2. The evaluation circuit of claim 1, wherein the target signal interconnect line comprises:

signal interconnection lines between any two chips in the multi-chip package, and/or

And a signal interconnection line between any one of the chips and the package base.

3. The evaluation circuit according to claim 1 or 2, wherein the first analog circuit is a first oscillating circuit; the target signal interconnection line is the first oscillating circuit capacitor;

the second analog circuit is a second oscillating circuit; wherein the adjustable capacitor is the second oscillating circuit capacitor.

4. The evaluation circuit of claim 3, wherein the first analog circuit is a first ring oscillator; the second analog circuit is a second ring oscillator.

5. The evaluation circuit of claim 4, wherein the target signal interconnect line comprises at least one set of signal interconnect line combinations; each group of signal interconnection line combination comprises two signal interconnection lines which are connected in series;

the first and second ring oscillators are disposed in a common ring oscillator;

the common ring oscillator comprises a delay module and a NAND gate logic circuit; the output end of the NAND gate logic circuit is connected with the input end of the delay module; the output end of the delay module is connected with the input end of the NOT gate logic circuit;

the delay module comprises at least one delay unit; each group of signal interconnection line combination corresponds to one delay unit;

the delay unit comprises an input buffer, a first selector, a second selector and an output buffer;

the output end of the output buffer is connected with the input end of the first selector; the first output end of the first selector is connected with the first input end of the second selector through the signal interconnection line combination corresponding to the delay unit; the second output end of the first selector and the second input end of the second selector are both grounded through the adjustable capacitor; the output end of the second selector is connected with the input end of the output buffer;

the common ring oscillator further comprises: a first buffer and a frequency divider;

the output end of the NAND gate logic circuit is connected with the input end of the frequency divider through the first buffer.

6. The evaluation circuit according to claim 1 or 2, wherein the first analog circuit is a first charge-discharge circuit; the target signal interconnection line is a charge-discharge capacitor of the first charge-discharge circuit;

the second analog circuit is a second charge-discharge circuit; the adjustable capacitor is a charge-discharge capacitor of the second charge-discharge circuit.

7. The evaluation circuit of claim 6, wherein the first charge-discharge circuit comprises a first current source, a first MOS transistor, a second MOS transistor and a first capacitor; the second charge-discharge circuit comprises a second current source, a third MOS (metal oxide semiconductor) tube, a fourth MOS tube and a second capacitor;

the first current source is grounded through the first MOS tube, the target signal interconnection line and the first capacitor; the target signal interconnection line is also grounded through the second MOS tube;

the second current source is grounded through the third MOS tube and the adjustable capacitor; the fourth MOS tube and the second capacitor are both connected with the adjustable capacitor in parallel;

the grid electrode of the first MOS tube is respectively connected with the grid electrode of the second MOS tube, the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube;

the channel types of the first MOS tube and the second MOS tube are different; the channel types of the third MOS tube and the fourth MOS tube are different; the channel types of the first MOS tube and the third MOS tube are the same.

8. The evaluation circuit of claim 7, wherein the signal comparison module comprises a comparator and a D flip-flop;

a first input end of the comparator is connected with a drain electrode of the first MOS tube; the second input end of the comparator is connected with the drain electrode of the third MOS tube; the output end of the comparator is connected with the D end of the D trigger; and the grid electrode of the first MOS tube is connected with the CP end of the D trigger through an inverter.

9. A multi-chip packaged microsystem, comprising: the evaluation circuit of any of claims 1 to 8; wherein the evaluation circuit is disposed in any one chip of a multi-chip packaged microsystem.

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