CN214506902U - Intelligent power module and air conditioner - Google Patents

Abstract

The utility model discloses an intelligent power module and air conditioner, this intelligent power module includes: the three-channel high voltage integrated circuit comprises a three-channel HVIC chip, a three-channel LVIC chip, a three-phase upper bridge arm circuit and a three-phase lower bridge arm circuit. The three-channel HVIC chip comprises a high-voltage driving circuit; the three-channel LVIC chip comprises a low-voltage driving circuit and an interlocking and dead-zone circuit, and the interlocking and dead-zone circuit is respectively connected with the high-voltage driving circuit and the low-voltage driving circuit; the driving signal input end of each phase of upper bridge arm circuit is connected with the driving signal output end of the corresponding phase in the high-voltage driving circuit; and the driving signal input end of each phase of lower bridge arm circuit is connected with the driving signal output end of the corresponding phase in the low-voltage driving circuit. The intelligent power module can reduce the module volume, reduce the complexity of assembly and processing and improve the working reliability of the module while realizing the functions of upper and lower bridge interlocking and dead zone control.

Description

Intelligent power module and air conditioner

Technical Field

The utility model belongs to the technical field of the air conditioner technique and specifically relates to an intelligent power module and an air conditioner is related to.

Background

Today, energy conservation and emission reduction become the current hot spots due to serious shortage of energy, and realization of efficient driving of a motor becomes more and more important. Because an Insulated Gate Bipolar Transistor (IGBT) has the advantages of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and a Gate Transistor (GTR) in motor drive application, the IGBT has an increasingly obvious advantage as a switching tube in motor drive, and it becomes a key for efficient driving of a motor to realize reliable and efficient driving of the IGBT.

Common IGBT driving schemes include: a six-channel HVIC (High Voltage Gate Driver IC) drives six IGBT tubes; one three-channel HVIC respectively drives three upper bridge IGBTs, and one three-channel LVIC (Low Voltage Gate Driver IC) respectively drives three lower bridge IGBTs; three two-channel HVICs, each HVIC drives two paths of IGBTs of an in-phase upper bridge and a lower bridge respectively; three one-channel HVICs drive one upper bridge IGBT respectively, and one three-channel LVIC drives three lower bridge IGBTs respectively.

However, the intelligent power module in the above-mentioned conventional IGBT driving scheme cannot achieve the functions of upper and lower bridge interlocking and dead zone control, while reducing the module size, reducing the complexity of assembly and processing, and improving the reliability.

SUMMERY OF THE UTILITY MODEL

The present invention aims at solving at least one of the technical problems in the related art to a certain extent. Therefore, an object of the utility model is to provide an intelligent power module, can reduce the module volume when realizing upper and lower bridge interlocking and blind spot control function, reduce the complexity of equipment and processing, improve the reliability of module work.

A second object of the present invention is to provide an air conditioner.

In order to achieve the above object, the utility model discloses a first aspect provides an intelligent power module, include: the three-channel HVIC chip comprises a high-voltage driving circuit; the three-channel LVIC chip comprises a low-voltage driving circuit and an interlocking and dead-zone circuit, and the interlocking and dead-zone circuit is respectively connected with the high-voltage driving circuit and the low-voltage driving circuit; the driving signal input end of each phase of upper bridge arm circuit is connected with the driving signal output end of the corresponding phase in the high-voltage driving circuit; and the driving signal input end of each phase of lower bridge arm circuit is connected with the driving signal output end of the corresponding phase in the low-voltage driving circuit.

According to the intelligent power module of the utility model, the interlocking and dead zone circuit respectively connected with the high-voltage driving circuit and the low-voltage driving circuit can reduce the module volume and the complexity of assembly and processing while realizing the functions of interlocking of the upper bridge and the lower bridge and dead zone control; by designing the interlock and dead band circuit in a three-channel LVIC chip (i.e., in the low-voltage region), the high-low voltage region matching can be increased.

In order to achieve the above object, the second aspect of the present invention provides an air conditioner, including the above intelligent power module.

According to the utility model discloses an air conditioner can reduce the module volume when realizing upper and lower bridge interlocking and blind spot control function through foretell intelligent power module, reduces the complexity of equipment and processing to with interlocking and blind spot circuit design in low-pressure area, multiplicable high low-pressure area matching degree improves the reliability of module work.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

Fig. 1 is a block diagram of an intelligent power module according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a circuit connection between a three-channel HVIC chip and a three-channel LVIC chip according to an embodiment of the present invention;

fig. 3 is a schematic diagram of an internal connection structure of an intelligent power module according to an embodiment of the present invention;

fig. 4 is a circuit schematic of a first power supply circuit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a high-voltage rectifying and filtering circuit according to an embodiment of the present invention;

fig. 6 is a schematic diagram of an enable error reporting circuit according to an embodiment of the present invention;

fig. 7 is a schematic diagram of an interlock and dead band circuit according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a high voltage driving circuit according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a low voltage driving circuit according to an embodiment of the present invention;

fig. 10 is a schematic circuit diagram of an intelligent power module according to another embodiment of the present invention;

fig. 11 is a block diagram of an air conditioner according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present invention, and should not be construed as limiting the present invention.

The intelligent power module and the air conditioner according to the embodiments of the present invention are described below with reference to the accompanying drawings.

Fig. 1 is a block diagram of an intelligent power module according to an embodiment of the present invention. Referring to fig. 1, the intelligent power module 1000 may include two three-channel chips, which are a three-channel HVIC chip 100 and a three-channel LVIC chip 200, respectively, and two bridge arm circuits, which are a three-phase upper bridge arm circuit 300 corresponding to the three-channel HVIC chip 100 and a three-phase lower bridge arm circuit 400 corresponding to the three-channel LVIC chip 200, respectively.

As shown in fig. 2-3, the three-channel HVIC chip 100 may include a high-voltage driving circuit 101 corresponding to the three-phase upper bridge arm circuit 300, where the high-voltage driving circuit 101 is configured to drive the three-phase upper bridge arm circuit 300; the three-channel LVIC chip 200 may include an interlock and dead-band circuit 202 and a low-voltage driving circuit 201 corresponding to the three-phase lower bridge arm circuit 400, the low-voltage driving circuit 201 is configured to drive the three-phase lower bridge arm circuit 400, and the interlock and dead-band circuit 202 is connected to the high-voltage driving circuit 101 and the low-voltage driving circuit 201, respectively. The interlock and dead zone circuit 202 has an input/output IO port, and the three-channel HVIC chip 100 is in communication connection with the three-channel LVIC chip 200 through the interlock in the three-channel LVIC chip 200 and the IO port of the dead zone circuit 202. The high-voltage driving circuit 101 and the low-voltage driving circuit 201 can realize the interlocking and dead zone control functions of the three-phase upper and lower bridge arm circuits through the interlocking and dead zone circuit 202, and the interlocking and dead zone circuit 202 is only arranged in the three-channel LVIC chip 200, so that the complexity of assembly and processing can be reduced, the matching degree of a high-voltage area and a low-voltage area is increased, and the reliability is improved.

As shown in fig. 3, the drive signal input terminal of each of the three phases of the three-phase upper arm circuit 300 is connected to the drive signal output terminal of the corresponding phase in the high-voltage drive circuit 101, and the drive signal input terminal of each of the three phases of the three-phase lower arm circuit 400 is connected to the drive signal output terminal of the corresponding phase in the low-voltage drive circuit 201. Specifically, referring to fig. 3, a driving signal input terminal HO1 of the U-phase upper arm circuit is connected to a U-phase driving signal output terminal in the high-voltage driving circuit 101, a driving signal input terminal HO2 of the V-phase upper arm circuit is connected to a V-phase driving signal output terminal in the high-voltage driving circuit 101, and a driving signal input terminal HO1 of the W-phase upper arm circuit is connected to a W-phase driving signal output terminal in the high-voltage driving circuit 101. A driving signal input end LO1 of the U-phase lower arm circuit is connected to a U-phase driving signal output end in the low-voltage driving circuit 201, a driving signal input end LO2 of the V-phase lower arm circuit is connected to a V-phase driving signal output end in the low-voltage driving circuit 201, and a driving signal input end LO1 of the W-phase lower arm circuit is connected to a W-phase driving signal output end in the low-voltage driving circuit 201.

In some embodiments of the present invention, as shown in fig. 2, the three-channel HVIC chip 100 may further include a first power circuit 102, wherein the first power circuit 102 may supply power to the high-voltage driving circuit 101 after rectification and filtering.

In some embodiments of the present invention, the three-channel LVIC chip 200 may further include a plurality of protection circuits, which are the over-temperature protection circuit 203, the under-voltage protection circuit 205, the over-current protection circuit 204, and the over-voltage protection circuit 206, respectively, and the three-channel LVIC chip 200 may further include an enable error reporting circuit 207 and a second power circuit 208.

The enabling error reporting circuit 207 is connected to each protection circuit (i.e., the over-temperature protection circuit 203, the over-current protection circuit 204, the under-voltage protection circuit 205, and the over-voltage protection circuit 206) and the interlock and dead zone circuit 202. The second power circuit 208 may be used to power the low voltage driver circuit 201.

In some embodiments of the utility model, intelligent power module 1000 can still include two feeder ends, be first feeder end VCC1 and second feeder end VCC2 respectively, and overcurrent protection end ITRIP, enable and report error end EN FLT, wherein, first feeder end VCC1 is connected to first power supply circuit 102, second feeder end VCC2 respectively with undervoltage protection circuit 205, second power supply circuit 208 and overvoltage protection circuit 206 are connected, overcurrent protection end ITRIP is connected to overcurrent protection circuit 204, enable and report error end EN FLT and enable and report error circuit 207 and be connected.

Specifically, the over-temperature protection circuit 203 is configured to detect a temperature of the intelligent power module 1000, and when an operating temperature of the intelligent power module 1000 is greater than an over-temperature protection temperature threshold set by the over-temperature protection circuit 203, send an over-temperature error-reporting fault signal to the enabling error-reporting circuit 207, so that the enabling error-reporting circuit 207 outputs the over-temperature error-reporting signal to the outside. The overcurrent protection circuit 204 is used for overcurrent detection and protection of the input current of the overcurrent protection terminal ITRIP. The undervoltage protection circuit 205 is configured to perform undervoltage detection and protection on the smart power module 1000, and the overvoltage protection circuit 206 is configured to perform overvoltage detection and protection on the smart power module 1000. For example, when the working voltage input from the VCC2 is lower than the working voltage of the low voltage driving circuit 201 in the three-channel LVIC chip 200, the under-voltage fault signal is sent to the enable error reporting circuit 207, so that the under-voltage fault signal is output to the outside through the enable error reporting circuit 207.

The operation principle of the enable error reporting circuit 207 may specifically be as follows: when the power supply terminals VCC1 and VCC2 of the intelligent power module 1000 are powered on, if the enable error reporting circuit 207 is in a low level state, the low voltage driving circuit 201 is in an off state in this state, and the high voltage driving circuit 101 is also in an off state by sharing this state with the high voltage driving circuit 101 through the interlock and dead zone circuit 202. When the external controller transmits a high-level enable signal to the enable error reporting circuit 207, the enable error reporting terminal EN/FLT is maintained at a high level, the low-voltage driving circuit 201 is in a working state, the state is shared by the interlocking and dead zone circuit 202 to the high-voltage driving circuit 101, the high-voltage driving circuit 101 is also in a working state, and when an error signal occurs, the enable error reporting terminal EN/FLT is pulled down to a low level until the error signal disappears, and the enable error reporting terminal EN/FLT can not be recovered to the high-level state. In addition, the interlock and dead zone circuit 202 is arranged in the three-channel LVIC chip 200, so that the output of an enable signal to a high-voltage area can be avoided, the signal is reduced, and the reliability is improved.

In some embodiments of the present invention, as shown in fig. 3, the smart power module 1000 may further include a positive power supply terminal (e.g., HIN1 terminal of U-phase) for three-phase high voltage region and a positive power supply terminal (e.g., LIN1 terminal of U-phase) for three-phase low voltage region. The three-phase high-voltage region power supply positive terminal is connected to the high-voltage driving circuit 101 and the interlock and dead-band circuit 202 respectively, and the three-phase low-voltage region power supply positive terminal is connected to the interlock and dead-band circuit 202.

Further, the three-channel HVIC chip 100 may further include three high-voltage region rectifying and filtering circuits corresponding to the high-voltage region phases to form the first rectifying and filtering circuit 103. The three high-voltage area rectifying and filtering circuits are respectively a U-phase high-voltage area rectifying and filtering circuit, a V-phase high-voltage area rectifying and filtering circuit and a W-phase high-voltage area rectifying and filtering circuit. In this embodiment, each phase (e.g., U-phase) high-voltage region rectifying and filtering circuit is connected to the first power circuit 102, the power supply positive terminal (e.g., HIN1) of the corresponding phase high-voltage region, and the control signal input terminal of the corresponding phase in the high-voltage driving circuit.

In some embodiments of the present invention, the three-channel LVIC chip 200 may further include three low-voltage zone rectifying and filtering circuits corresponding to the phases of the low-voltage zone to form the second rectifying and filtering circuit 209. The three low-voltage area rectifying and filtering circuits are respectively a U-phase low-voltage area rectifying and filtering circuit, a V-phase low-voltage area rectifying and filtering circuit and a W-phase low-voltage area rectifying and filtering circuit. Wherein each phase (e.g., U-phase) low-voltage region rectifying and filtering circuit is connected to the second power circuit 208, the corresponding phase low-voltage region power supply positive terminal (e.g., LIN1), and the control signal input terminal of the corresponding phase in the interlock and dead-band circuit 202.

Specifically, when the intelligent power module 1000 is powered on, if the enable terminal of the enable error reporting circuit 207 inputs a low level, at this time, the low voltage driving circuit 201 is in a non-operating state, and the interlock and dead zone circuit 202 transmits the state signal to the high voltage driving circuit 101, so that the high voltage driving circuit 101 is in a non-driving state. When the external controller inputs a high level to the enable terminal of the enable error reporting circuit 207, the enable error reporting circuit 207 enables the over-temperature protection circuit 203, the under-voltage protection circuit 205, the over-current protection circuit 204 and the over-voltage protection circuit 206 to perform state detection, and when the voltage, current and temperature state detection is normal, the enable error reporting circuit 207 enables the low-voltage driving circuit 201 to be in a normal working state. At this time, the interlock and dead zone circuit 202 transmits the state to the high voltage driving circuit 101 through the signal control IO port to make the high voltage driving circuit 101 in a normal operation state. When power is supplied to the high-voltage driving circuit 101 from the positive end of the three-phase high-voltage region power supply, the power supply voltage can be rectified and filtered through the first rectifying and filtering circuit 103; accordingly, when power is supplied to the low-voltage driving circuit 201 from the three-phase low-voltage region power supply positive terminal, the power supply voltage can be rectified and filtered by the second rectifying and filtering circuit 209.

Further, when any one of the over-temperature protection circuit 203, the under-voltage protection circuit 205, the over-current protection circuit 204 and the over-voltage protection circuit 206 detects an abnormal state, an error signal can be transmitted to the outside through the enable error signal circuit 207, and the abnormal state is transmitted to the interlock and dead zone circuit 202 to control the low-voltage driving circuit 201 to stop working, and meanwhile, the state signal can be transmitted to the high-voltage driving circuit 101 to control the high-voltage driving circuit 101 to stop working.

Fig. 4 is a circuit diagram of a first power circuit according to an embodiment of the present invention. In this embodiment, the first power supply circuit 102 and the second power supply circuit 208 may have the same configuration.

Referring to fig. 4, the first power circuit 102 may include two N-type switches, i.e., a first N-type switch N1 and a second N-type switch N2; the two P-type switching tubes are respectively a first P-type switching tube P1, a second P-type switching tube P2 and a third P-type switching tube P3; the six resistors are respectively a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, and one capacitor is a first capacitor C1; two diodes, a first diode D1 and a second diode D2; the two triodes are a first triode Q1 and a second triode Q2 respectively. The switching tubes N1, N2, P1, P2 and P3 may be all IGBT (Insulated Gate Bipolar Transistor) tubes.

Further, as shown in fig. 4, the specific structure of the first power circuit 102 is: the source electrode of the first N-type switch tube N1, the source electrode of the second N-type switch tube N2, the drain electrode of the third P-type switch tube P3 and one end of the R1 are all connected with the first power supply end VCC1, the grid electrode G of the first N-type switch tube N1 is respectively connected with the drain electrode D of the first N-type switch tube N1 and the grid electrode G of the second N-type switch tube N2, and the other end of the first resistor R1 is grounded GND sequentially through the second resistor R2 and the third resistor R3. The cathode of the first diode D1 is connected to the other end of the first resistor R1, the anode of the first diode D1 is connected to the collector c and the base b of the first triode Q1, the emitter e of the first triode Q1 is connected to the collector c and the base b of the second triode Q2, and the emitter e of the second triode Q2 is grounded. A drain D of the first P-type switch tube P1 is connected to a drain D of the first N-type switch tube N1, a gate G of the first P-type switch tube P1 is connected to a midpoint between the second resistor R2 and the third resistor R3, a source S of the first P-type switch tube P1 and a source S of the second P-type switch tube P2 are connected to the fourth resistor R4 and are grounded through the fourth resistor R4, a drain D of the second P-type switch tube P2 is connected to a drain D of the second N-type switch tube N2, a gate G of the third P-type switch tube P3 and one end of the first capacitor C1, a gate G of the second P-type switch tube P2 is connected to the other end of the first capacitor C1, a cathode of the second diode D2, one end of the fifth resistor R5, one end of the sixth resistor R6, an anode of the second diode D2 and the other end of the sixth resistor R5 are connected to the ground, and a source of the fifth P58573s 24 is connected to the third resistor P57323, and may serve as an output terminal VREG of the first power supply circuit 102 through which the high voltage driving circuit 101 is supplied with power.

Fig. 5 is a schematic structural diagram of a high-voltage region rectifying and filtering circuit according to an embodiment of the present invention. The structure of the high voltage region rectifying and filtering circuit and the structure of the low voltage region rectifying and filtering circuit in this embodiment may be the same. Referring to fig. 5, the high voltage region rectifying and filtering circuit may include five NMOS transistors, which are a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM1, and a fifth NMOS transistor NM 5; the four PMOS tubes are respectively a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3 and a fourth PMOS tube PM 4; and a seventh resistor R7 and a second capacitor C2.

Further, as shown in fig. 5, the U-phase high voltage region rectifying and filtering circuit has a specific structure that the sources S of the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 and a substrate lead (shown by a dotted line) are all connected to the first power supply terminal VCC1, the gates G of the first NMOS transistor NM1 and the first PMOS transistor PM1 are all connected to the U-phase high voltage region power supply positive terminal HIN1, and the drain D of the first NMOS transistor NM1 is connected to the drain D of the first PMOS transistor PM1 and one end of the seventh resistor R7, respectively. The other end of the seventh resistor R7 is connected to one end of the second capacitor C2, the gate G of the second PMOS transistor NM2, the gate G of the fourth PMOS transistor NM4, the gate G of the second PMOS transistor PM2, and the gate G of the third PMOS transistor PM3, respectively, the other end of the second capacitor C2 is grounded, the substrate lead of the second PMOS transistor NM2 is connected to the substrate lead of the fourth PMOS transistor NM4, and the drain D of the second PMOS transistor NM2 is connected to the source S of the fourth PMOS transistor NM4 and the source S of the fifth PMOS transistor NM5, respectively. A substrate lead of a fifth PMOS transistor NM5 is connected to the first power supply terminal VCC1, a drain D of the fifth PMOS transistor NM5 is connected to the gate G of the third PMOS transistor NM3, a drain D of the third PMOS transistor NM3 is connected to the drain D of the fourth PMOS transistor PM4, a substrate lead of the fourth PMOS transistor PM4, a source S and a substrate lead of the third PMOS transistor PM3, a source S and a substrate lead of the first PMOS transistor PM1 are all grounded, a substrate lead of the second PMOS transistor PM2 is connected to the substrate lead of the third PMOS transistor PM3, a source S of the second PMOS transistor PM2 is connected to the drain D of the third PMOS transistor PM3, a gate G of the fifth PMOS transistor NM5 is connected to the drain D of the fourth PMOS transistor NM4, a drain D of the second PMOS transistor PM2, and a gate of the fourth PMOS transistor PM4, and connected to a node OUTH, so as to serve as an output terminal of the U-phase high voltage rectifying-region filter circuit.

Fig. 6 is a schematic structural diagram of an enable error reporting circuit according to an embodiment of the present invention. Referring to fig. 6, the enable error reporting circuit 207 may include a first logic sub-circuit 2071, a second logic sub-circuit 2072 and a third logic sub-circuit 2073.

In this embodiment, as shown in fig. 6, the first logic sub-circuit 2071 is respectively and correspondingly connected to the over-temperature protection circuit 203, the over-current protection circuit 204, the under-voltage protection circuit 205 and the over-voltage protection circuit 206 through the UVLO terminal, the OV terminal, the OT terminal and the OC terminal. The second logic sub-circuit 2072 is connected to the enable error terminal EN/FLT. The third logic sub-circuit 2073 is connected to the first logic sub-circuit 2071 and the second logic sub-circuit 2072, respectively.

Specifically, as shown in fig. 6, the first logic sub-circuit 2071 may include four NMOS transistors, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8 and a ninth NMOS transistor NM 9; and the four PMOS tubes are a fifth PMOS tube PM5, a sixth PMOS tube PM6, a seventh PMOS tube PM7 and an eighth PMOS tube PM8 respectively.

Referring to fig. 6, the sources S and the substrate leads of the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, and the ninth NMOS transistor NM9 are all connected to the second power supply terminal VCC2, the gates G of the sixth NMOS transistor NM6 and the fifth PMOS transistor PM5 are all connected to the output terminal UVLO of the undervoltage protection circuit 205, the gates G of the seventh NMOS transistor NM7 and the sixth PMOS transistor PM6 are all connected to the output terminal OV of the overvoltage protection circuit 206, the gates G of the eighth NMOS transistor NM8 and the seventh PMOS transistor PM7 are all connected to the output terminal OT of the over-temperature protection circuit 203, and the gates G of the ninth NMOS transistor NM9 and the eighth PMOS transistor PM8 are all connected to the output terminal OC of the over-temperature protection circuit 204; drain electrodes D of a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, and a drain electrode D of an eighth PMOS transistor PM8 are all connected to the third logic sub-circuit 2073, a source electrode S of the eighth PMOS transistor PM8 is connected to a drain electrode D of a seventh PMOS transistor PM7, a source electrode S of the seventh PMOS transistor PM7 is connected to a drain electrode D of the PM6, a source electrode S of the sixth PMOS transistor PM6 is connected to a drain electrode D of the fifth PMOS transistor PM5, a source electrode S of the fifth PMOS transistor PM5 is grounded to the PMOS VSS, and substrate leads of the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, and the eighth PMOS transistor PM8 are connected to each other.

Further, as shown in fig. 6, the second logic sub-circuit 2072 may include a third diode D3, a fourth diode D4, an eighth resistor R8, a ninth PMOS transistor PM9, a schmitt trigger a and a noise filter B.

Referring to fig. 6, the anode of D3, the cathode of D4, one end of R8, and the drain D of PM9 are all connected to an enable error reporting terminal EN/FLT, the cathode of D3 is connected to a second power supply terminal VCC2, the anode of D4 and the source S of PM9 are all grounded, the other end of R8 is connected to the input terminal of a schmitt trigger a, the output terminal of the schmitt trigger a is connected to the input terminal of a noise filter B, and the output terminal of the noise filter B is connected to the gate G of the PM9 and the third logic sub-circuit 2073, respectively.

Further, as shown in fig. 6, the third logic sub-circuit 2073 may include three NMOS transistors, a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11 and a twelfth NMOS transistor NM 12; and three PMOS tubes, which are a tenth PMOS tube PM10, an eleventh PMOS tube PM11 and a twelfth PMOS tube PM12 respectively.

Referring to fig. 6, the sources S of the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 are connected to the second power supply terminal VCC2, the gates G of the tenth NMOS transistor NM10 and the tenth PMOS transistor PM10 are connected to the first logic sub-circuit 2071, the drain D of the tenth NMOS transistor NM10 is connected to the source S of the twelfth NMOS transistor NM12, the substrate lead of the tenth NMOS transistor NM10 is connected to the substrate lead of the twelfth NMOS transistor NM12, the gates G of the twelfth NMOS transistor NM12 and the twelfth NMOS transistor NM G, PM12 are connected to the second logic sub-circuit 2072, the drain D of the twelfth NMOS transistor NM12 is connected to the drain D of the tenth transistor PM10, the drain D of the twelfth PMOS transistor PM12, the gate G, PM11 of the eleventh NMOS transistor NM11, the drains PM 3684 and the drain of the twelfth PMOS transistor PM12 are connected to the drains VSS 12, and the drains of the eleventh NMOS transistor NM11 are connected to the drain p 11, and is connected to a node EN as an output of the enable error reporting circuit 207.

Alternatively, as shown in fig. 7-9, the present invention further specifically illustrates the schematic circuit structure of the interlock and dead-zone circuit 202, the high voltage driving circuit 101, and the low voltage driving circuit 201.

It should be noted that the first rectifying Circuit 103, the second rectifying Circuit 209, the enable error reporting Circuit 207, the interlock and dead zone Circuit 202, the high voltage driving Circuit 101 and the low voltage driving Circuit 201, which are formed by the high-voltage and low-voltage area rectifying and filtering Circuit in this embodiment, are implemented by an IC (Integrated Circuit Chip) manufacturing process such as a BCD process (a process in which a CMOS device, a CMOS device and a bipolar device are Integrated on the same Chip), a CMOS process (a process in which only a CMOS device is Integrated on the same Chip) and a Bi-CMOS process (a process in which a CMOS device and a bipolar device are Integrated on the same Chip), the intelligent power module 1000 is assembled inside by a lead frame, and specifically, the three-channel HVIC chip 100, the three-channel LVIC chip 200, the three-phase upper bridge arm circuit 300 and the three-phase lower bridge arm circuit 400 can be all pasted on the lead frame.

Specifically, the three-channel HVIC chip 100 and the three-channel LVIC chip 200 may be bonded to the lead frame by using bonding wires made of materials such as gold, copper or aluminum, so as to form electrical connection; gold bonding wires, copper bonding wires or aluminum bonding wires can also be used for bonding between the three-channel HVIC chip 100 and the three-channel LVIC chip 200 so as to form electrical connection. The three-phase upper bridge arm circuit 300, the three-phase lower bridge arm circuit 400 and the lead frame can be bonded by adopting aluminum bonding wires to form electrical connection; between the three-channel HVIC chip 100 and the three-phase upper bridge arm circuit 300, and between the three-channel LVIC chip 200 and the three-phase lower bridge arm circuit 400, gold bonding wires, copper bonding wires or aluminum bonding wires may also be used for bonding, so as to form electrical connections. The chips and circuits are assembled through the lead frame, so that a Printed Circuit Board (PCB) structure is not needed, the module volume can be reduced, the driving path is shortened, and the parasitic resistance, the inductance and the like of the driving Circuit are reduced.

To sum up, the embodiment of the utility model provides an intelligent power module need not to adopt the PCB structure, can reduce the module volume, shortens drive path, reduces drive line parasitic resistance, inductance etc to with interlocking and dead zone circuit design in the low-pressure area, multiplicable high low-pressure area matching degree, and can effectively avoid enabling signal output to the high-pressure area, improve module reliability.

Fig. 10 is a schematic circuit diagram of an intelligent power module according to another embodiment of the present invention. It should be noted that the intelligent power module in this embodiment omits a rectifier and filter circuit, so that the module size can be further reduced, the driving path can be shortened, and the parasitic resistance and inductance of the driving circuit can be reduced.

It should be noted that the actual number of pins of the smart power module 1000 and its constituent structures is not limited to the illustrations in fig. 2 to 11.

Further, as shown in fig. 11, the present invention further provides an air conditioner 10000, including the above intelligent power module 1000.

According to the utility model discloses an air conditioner, through foretell intelligent power module, can be when realizing upper and lower bridge interlocking and blind spot control function, reduce the module volume, reduce the complexity of equipment and processing to with interlocking and blind spot circuit design in low-pressure area, multiplicable high low-pressure area matching degree improves the reliability of module work.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, for example, two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

Although embodiments of the present invention have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art without departing from the scope of the present invention.

Claims (11)

1. A smart power module, comprising:

the three-channel HVIC chip comprises a high-voltage driving circuit;

the three-channel LVIC chip comprises a low-voltage driving circuit and an interlocking and dead-zone circuit, and the interlocking and dead-zone circuit is respectively connected with the high-voltage driving circuit and the low-voltage driving circuit;

the driving signal input end of each phase of upper bridge arm circuit is connected with the driving signal output end of the corresponding phase in the high-voltage driving circuit;

and the driving signal input end of each phase of lower bridge arm circuit is connected with the driving signal output end of the corresponding phase in the low-voltage driving circuit.

2. The smart power module of claim 1, wherein the three-channel HVIC chip further comprises:

and the first power supply circuit is used for supplying power to the high-voltage driving circuit.

3. The smart power module of claim 2 wherein said three-channel LVIC chip further comprises:

the over-temperature protection circuit, the over-current protection circuit, the under-voltage protection circuit and the over-voltage protection circuit;

the enabling error reporting circuit is respectively connected with the over-temperature protection circuit, the over-current protection circuit, the under-voltage protection circuit, the overvoltage protection circuit and the interlocking and dead zone circuit;

and the second power supply circuit is used for supplying power to the low-voltage driving circuit.

4. The smart power module of claim 3, wherein the smart power module further comprises:

a first power supply terminal connected to the first power supply circuit;

the second power supply end is respectively connected with the second power supply circuit, the undervoltage protection circuit and the overvoltage protection circuit;

the overcurrent protection end is connected with the overcurrent protection circuit;

and the enabling error reporting end is connected with the enabling error reporting circuit.

5. The smart power module of claim 3, wherein the smart power module further comprises:

the three-phase high-voltage area power supply positive end is respectively connected with the high-voltage driving circuit and the interlocking and dead zone circuit;

and the three-phase low-voltage area power supply positive terminal is connected with the interlocking and dead zone circuit.

6. The smart power module of claim 5,

the three-channel HVIC chip also comprises three high-voltage area rectifying and filtering circuits, wherein each high-voltage area rectifying and filtering circuit is connected with the first power supply circuit and is respectively connected with a power supply positive end of a corresponding phase high-voltage area and a control signal input end of a corresponding phase in the driving circuit;

the three-channel LVIC chip further comprises three low-voltage area rectifying and filtering circuits, and each low-voltage area rectifying and filtering circuit is connected with the second power circuit and is respectively connected with a power supply positive end of a corresponding low-voltage area and a control signal input end of a corresponding phase in the interlocking and dead zone circuit.

7. The smart power module of claim 4, wherein the first power circuit comprises: first to second N-type switching tubes, first to third P-type switching tubes, first to sixth resistors, a first capacitor, first to second diodes, and first to second triodes,

the source electrode of the first N-type switch tube, the source electrode of the second N-type switch tube, the drain electrode of the third P-type switch tube and one end of the first resistor are all connected to the first power supply end, the grid electrode of the first N-type switch tube is respectively connected with the drain electrode of the first N-type switch tube and the grid electrode of the second N-type switch tube, the other end of the first resistor is grounded sequentially through the second resistor and the third resistor, the cathode of the first diode is connected with the other end of the first resistor, the anode of the first diode is respectively connected with the collector electrode and the base electrode of the first triode, the emitter electrode of the first triode is respectively connected with the collector electrode and the base electrode of the second triode, the emitter electrode of the second triode is grounded, the drain electrode of the first P-type switch tube is connected with the drain electrode of the first N-type switch tube, the grid electrode of the first P-type switch tube is connected with the midpoint of the second resistor and the third resistor, the source electrode of the first P-type switch tube and the source electrode of the second P-type switch tube are grounded through a fourth resistor, the drain electrode of the second P-type switch tube is connected with the drain electrode of the second N-type switch tube, the grid electrode of the third P-type switch tube and one end of the first capacitor respectively, the grid electrode of the second P-type switch tube is connected with the other end of the first capacitor, the cathode of the second diode, one end of a fifth resistor and one end of a sixth resistor respectively, the anode of the second diode and the other end of the sixth resistor are grounded, and the other end of the fifth resistor is connected with the source electrode of the third P-type switch tube and serves as the output end of the first power circuit.

8. The smart power module of claim 4, wherein the enable error reporting circuit comprises:

the first logic sub-circuit is respectively connected with the undervoltage protection circuit, the overvoltage protection circuit, the over-temperature protection circuit and the overcurrent protection circuit;

the second logic sub-circuit is connected with the enabling error reporting end;

and the third logic sub-circuit is respectively connected with the first logic sub-circuit and the second logic sub-circuit.

9. The intelligent power module as claimed in claim 7, wherein the first to second N-type switching tubes and the first to third P-type switching tubes are all IGBT tubes.

10. The intelligent power module as claimed in claim 1, wherein a lead frame is arranged inside the intelligent power module, and the three-channel HVIC chip, the three-channel LVIC chip, the three-phase upper bridge arm circuit and the three-phase lower bridge arm circuit are all adhered to the lead frame.

11. An air conditioner comprising the smart power module as recited in any one of claims 1-10.

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