CN214505005U - Application verification circuit for memory device - Google Patents
Application verification circuit for memory device Download PDFInfo
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- CN214505005U CN214505005U CN202120718117.9U CN202120718117U CN214505005U CN 214505005 U CN214505005 U CN 214505005U CN 202120718117 U CN202120718117 U CN 202120718117U CN 214505005 U CN214505005 U CN 214505005U
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Abstract
A memory device application verification circuit comprises a main control board, wherein the main control board comprises a download control circuit and a download mode selection circuit connected with the download control circuit and used for switching a download mode through the download control circuit and the download mode selection circuit; the memory test motherboard comprises the main control board and a plurality of image generation board cards, and the image generation board cards are used for capturing signals and judging; the image generation board card comprises a control core module, a driving module and a channel output module which are connected in sequence and used for controlling data acquisition and driving output data; the image generation board card further comprises a communication interface module, a program storage module and a vector storage module which are connected with the control core module and are respectively used for transmitting data through the communication interface module and storing program data and vector data.
Description
Technical Field
The utility model belongs to the technical field of the memory application verification technique and specifically relates to a memory class device application verification circuit.
Background
The memory is a memory device in the computer system and is mainly used for storing programs and data; all information in the computer, including input original data, computer program, intermediate operation result and final operation result, are stored in the memory, and the information is stored and taken out according to the position appointed by the controller; with the development of the electronic industry, the demand of people on the memory is rapidly increased, and the standard of the current memory is also improved; however, the existing memory verification system cannot switch the downloading mode to download the code stream, and cannot store and process the program data and the vector data in real time, so that the accuracy of the verification data is ensured.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome prior art's not enough, provide a memory class device application verification circuit.
The utility model provides a its technical problem take following technical scheme to realize:
the utility model provides a memory class device application verification circuit, includes the main control board, the main control board includes download control circuit and with download control circuit connection download mode selection circuit for through download control circuit and download mode selection circuit switching download mode.
Preferably, the memory test motherboard comprises the main control board and a plurality of image generation boards, and the image generation boards are used for capturing signals and performing judgment processing.
Preferably, the image generation board card comprises a control core module, a driving module and a channel output module which are connected in sequence and used for controlling data acquisition and driving output data.
Preferably, the image generation board card further comprises a communication interface module connected with the control core module, and the communication interface module is used for transmitting data.
Preferably, the image generation board card further comprises a program storage module and a vector storage module connected to the control core module, and the program storage module and the vector storage module are respectively used for storing program data and vector data.
Preferably, the test device further comprises a memory test sub-board, wherein the memory test sub-board is connected with the test chip; the memory test sub-board comprises a sub-board I and a sub-board II, and the test chip is subjected to verification test.
Preferably, the model of the first sub-board is SM29LV 160; the second sub-board is model number SM41J28M 16M.
Preferably, the memory test system further comprises a connector connected with the memory test motherboard.
Preferably, the daughter board one, the daughter board two and the image generation board card are respectively connected to the connector.
Preferably, the memory test motherboard is connected with the upper computer through a network port.
The utility model has the advantages that:
1. the utility model relates to a memory class device application verification circuit, including the main control board, the main control board including download control circuit and with download control circuit connects download mode selection circuit, is used for passing through download control circuit and download mode selection circuit switch download mode.
2. The utility model discloses well memory test motherboard includes main control board and a plurality of image generation integrated circuit boards, image generation integrated circuit board is used for snatching the signal and judges and handles; the image generation board card comprises a control core module, a driving module and a channel output module which are connected in sequence and used for controlling data acquisition and driving output data; the image generation board card further comprises a communication interface module, a program storage module and a vector storage module which are connected with the control core module, and the communication interface module is used for transmitting data and storing program data and vector data respectively, so that the accuracy of verification data is guaranteed.
Drawings
Fig. 1 is a circuit connection block diagram of the present invention;
FIG. 2 is a connection diagram of a download control circuit according to the present invention;
FIG. 3 is a circuit diagram of the download mode selection circuit of the present invention;
FIG. 4 is a circuit diagram of the daughter board of the present invention;
FIG. 5 is a diagram of the daughter board of the present invention;
fig. 6 is a circuit diagram of the connector of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When a component is referred to as being "disposed on" another component, it can be directly on the other component or intervening components may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1-3, the present invention provides a verification circuit for memory device applications, which is characterized in that: the device comprises a main control board, wherein the main control board comprises a download control circuit and a download mode selection circuit connected with the download control circuit and used for switching download modes through the download control circuit and the download mode selection circuit;
specifically, an INIT _ B pin, a PROG _ B pin, a DONE pin, an M0 pin, an M1 pin, an M2 pin, and a CFGBVS pin of the main control board are respectively connected to an INIT _ B pin, a PROG _ B pin, a DONE pin, an M0 pin, an M1 pin, an M2 pin, and a CFGBVS pin of the download mode selection circuit; the DONE pin of the main control board is a drain open circuit output, and is connected with an LED to display whether the output exists or not; the main control board initializes (clears) the configuration memory of the download mode selection circuit from power-on reset or program reset of the INIT _ B pin.
Further, the memory test motherboard comprises the main control board and a plurality of image generation board cards; the image generation board card comprises a control core module, a driving module and a channel output module which are connected in sequence and used for controlling data acquisition and driving output data.
Specifically, the memory test motherboard comprises a main control board and 6 image generation board cards with the same structure, and the image generation board cards are used for capturing signals and judging and processing the signals; the image generation board card is realized by a K7 series FPGA of Xilinx; the control core module is used for finishing the generation of an algorithm, the expansion of a vector, the generation of each triggering edge and the generation of any period; the drive module adopts an ADATE305 digital channel driver chip and is used for output level, input signal comparison and parameter measurement; the image generation board card also comprises a communication interface module connected with the control core module and used for transmitting data through the communication interface module; the image generation board card further comprises a program storage module and a vector storage module which are connected with the control core module and are respectively used for storing program data and vector data.
Further, as shown in fig. 4 and 5, the test device further includes a memory test sub-board, and the memory test sub-board is connected to the test chip; the memory test sub-board comprises a sub-board I and a sub-board II, and the test chips are subjected to verification test; specifically, the model of the daughter board one is SM29LV 160; the model of the daughter board II is SM41J28M 16M; the first daughter board is a flash device, when testing direct current parameters and time parameters, a testing chip is placed in a first chip base of the first daughter board, the first chip base is designed to resist high temperature of 150 ℃, a driving signal of the testing chip transmits a signal of the testing mother board of the memory through a connector, and meanwhile, the connector can resist high temperature of 150 ℃, so that the requirement of performing a high-temperature environment test by using the verification circuit is met.
According to the characteristics of the read-write parameters of the memory, when testing the direct current parameters and the time parameters, the testing chip is placed in the second testing base of the second daughter board, and the PIN PIN of the testing chip is directly connected with the testing channel of the image generation board card, so that the direct current parameters and the time parameters are directly tested, the upper computer monitors the voltage and the current information in real time, and the upper computer can timely turn off the power supply when sudden situations occur.
Further, as shown in fig. 4-6, a connector connected to the memory test motherboard is further included; the daughter board I, the daughter board II and the image generation board card are respectively connected with the connector; and the memory test motherboard is connected with the upper computer through the network port.
The working principle is as follows:
1. the memory test motherboard comprises the main control board and a plurality of image generation board cards, and the image generation board cards are used for capturing signals and judging;
2. the main control board comprises a download control circuit and a download mode selection circuit connected with the download control circuit, and is used for switching download modes through the download control circuit and the download mode selection circuit;
3. the image generation board card also comprises a program storage module and a vector storage module which are connected with the control core module and are respectively used for storing program data and vector data;
4. the memory test daughter board is connected with the test chip; the memory test sub-board comprises a sub-board I and a sub-board II, and the test chips are subjected to verification test;
5. the memory test mother board and the memory test daughter board are connected through a connector;
6. and the memory test motherboard is connected with the upper computer through the network port.
The utility model relates to a memory device application verification circuit, which comprises a main control board, wherein the main control board comprises a download control circuit and a download mode selection circuit connected with the download control circuit, and is used for switching download modes through the download control circuit and the download mode selection circuit; the memory test motherboard comprises the main control board and a plurality of image generation board cards, and the image generation board cards are used for capturing signals and judging; the image generation board card comprises a control core module, a driving module and a channel output module which are connected in sequence and used for controlling data acquisition and driving output data; the image generation board card further comprises a communication interface module, a program storage module and a vector storage module which are connected with the control core module and are respectively used for transmitting data through the communication interface module and storing program data and vector data.
The above description is for the detailed description of the preferred possible embodiments of the present invention, but the embodiments are not intended to limit the scope of the present invention, and all equivalent changes or modifications accomplished under the technical spirit suggested by the present invention should fall within the scope of the present invention.
Claims (10)
1. A memory class device application verification circuit, comprising: the device comprises a main control board, wherein the main control board comprises a download control circuit and a download mode selection circuit connected with the download control circuit and used for switching download modes through the download control circuit and the download mode selection circuit.
2. The memory device application verification circuit of claim 1, wherein: the memory test motherboard comprises the main control board and a plurality of image generation board cards, and the image generation board cards are used for capturing signals and judging.
3. The memory device application verification circuit of claim 2, wherein: the image generation board card comprises a control core module, a driving module and a channel output module which are connected in sequence and used for controlling data acquisition and driving output data.
4. The memory device application verification circuit of claim 2, wherein: the image generation board card further comprises a communication interface module connected with the control core module, and the communication interface module is used for transmitting data.
5. The memory device application verification circuit of claim 2, wherein: the image generation board card further comprises a program storage module and a vector storage module which are connected with the control core module and are respectively used for storing program data and vector data.
6. The memory device application verification circuit of claim 2, wherein: the memory test sub-board is connected with the test chip; the memory test sub-board comprises a sub-board I and a sub-board II, and the test chip is subjected to verification test.
7. The memory device application verification circuit of claim 6, wherein: the model of the daughter board I is SM29LV 160; the second sub-board is model number SM41J28M 16M.
8. The memory device application verification circuit of claim 7, wherein: the memory test system further comprises a connector connected with the memory test motherboard.
9. The memory device application verification circuit of claim 8, wherein: the daughter board I, the daughter board II and the image generation board card are respectively connected with the connector.
10. The memory device application verification circuit of claim 2, wherein: and the memory test motherboard is connected with the upper computer through the network port.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120445459 | 2021-03-01 | ||
| CN2021204454598 | 2021-03-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214505005U true CN214505005U (en) | 2021-10-26 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120718117.9U Active CN214505005U (en) | 2021-03-01 | 2021-04-08 | Application verification circuit for memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN214505005U (en) |
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2021
- 2021-04-08 CN CN202120718117.9U patent/CN214505005U/en active Active
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