CN214480522U - Trigger device - Google Patents

Abstract

The present application provides a flip-flop. In the trigger, each MOS transistor is connected according to a preset connection relationship to realize a corresponding trigger function, for example, set to 0 or set to 1; in addition, in the trigger, at least one MOS tube adopts an FDSOI-MOS tube, so that the leakage current of the trigger in the actual operation process is reduced, and the influence of the leakage current on the self operation is reduced; in addition, after the FDSOI-MOS tube is adopted, the FDSOI-MOS tube has extremely small threshold voltage variability, namely has better threshold voltage uniformity, and is further favorable for timing convergence of a digital integrated circuit corresponding to the trigger.

Description

Trigger device

Technical Field

The utility model relates to the field of semiconductor technology, especially, relate to a trigger.

Background

A flip-flop is a basic circuit cell capable of storing a 1-bit binary signal, having two stable states, which can receive, store and output signals. In practical digital systems, a large number of flip-flops are often included for saving; and they are required to act synchronously at the same time, and for this purpose, a clock pulse is introduced to the flip-flop as a control signal, namely, the flip-flop can be triggered to act when the pulse arrives, and the output state is changed according to the input signal.

However, during the actual operation of the flip-flop, leakage current exists in the flip-flop itself, and the leakage current affects the operation of the flip-flop itself.

SUMMERY OF THE UTILITY MODEL

In view of this, the present invention provides a trigger to reduce the influence of the leakage current of the trigger itself on the operation of the trigger in the actual operation process.

In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:

the present application provides a flip-flop, comprising: a plurality of MOS tubes; wherein:

the MOS tubes are connected according to a preset connection relation; the preset connection relation is the connection relation of the trigger to realize the function of the trigger;

at least one MOS tube is an FDSOI-MOS tube.

Optionally, the MOS transistors are divided into four groups, and the preset connection relationship includes: the connection relationship between the MOS tubes in each group and the connection relationship between the MOS tubes in each group.

Optionally, each group of MOS transistors includes: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor; the connection relation among the MOS tubes in the group is as follows:

the first MOS tube is connected with the third MOS tube in a common grid mode, and a connection point is used as an input end of each group;

the second MOS tube and the fourth MOS tube are connected in a common grid mode, and a connection point is used as the other input end of each group;

the first MOS tube is connected with the second MOS tube in a common source mode, and a connecting point is connected with a power supply;

the first MOS tube, the second MOS tube and the third MOS tube are connected in a common drain electrode mode, and a connection point is used as an output end of each group;

the source electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube, and the source electrode of the fourth MOS tube is grounded;

the first MOS tube and the second MOS tube are PMOS tubes, and the third MOS tube and the fourth MOS tube are NMOS transistors.

Optionally, the four groups of MOS transistors respectively are: a first group, a second group, a third group and a fourth group.

Optionally, if the trigger is an SR trigger, the connection relationship among the groups specifically includes:

any input end of the first group and the second group is respectively used as a first input end and a second input end of the SR trigger;

the other input end of the first group is connected with the other input end of the second group, and the connection point is used as a signal end of the SR trigger;

and any input end of the third group and the fourth group is respectively connected with the output ends of the first group and the second group, the other input end of the third group and the fourth group is respectively connected with the output end of the other group, and the output ends of the third group and the fourth group are respectively used as the output end and the reverse output end of the SR trigger.

Optionally, if the flip-flop is a JK flip-flop, the connection relationship among the groups specifically includes:

the first input end of the first group is used as a first input end of the JK trigger; the first input end of the second group is used as a second input end of the JK trigger; the second input ends of the first group and the second group are connected, and the connection point is used as a signal end of the JK trigger;

one input end of the third group is connected with the output end of the first group, one input end of the fourth group is connected with the output end of the second group, the output end of the third group is connected with the other input end of the fourth group, and the output end of the fourth group is connected with the other input end of the third group;

the output end of the third group is used as the output end of the JK trigger, and the output end of the fourth group is used as the reverse output end of the JK trigger;

the output end of the third group is also connected with the first input end of the second group, and the output end of the fourth group is also connected with the first input end of the first group.

Optionally, if the flip-flop is a D flip-flop, the connection relationship among the groups specifically includes:

one input end of the first group is used as the input end of the D trigger; one input end of the second group is connected with the output end of the first group;

the other input end of the first group is connected with the other input end of the second group, and the connection point is used as a signal end of the D trigger;

the output end of the first group is connected with one input end of the third group, and the output end of the second group is connected with one input end of the fourth group;

the other input end of the third group is connected with the output end of the fourth group; the other input end of the fourth group is connected with the output end of the third group;

and the output end of the third group is used as the output end of the D trigger, and the output end of the fourth group is used as the reverse output end of the D trigger.

Optionally, if the trigger is a T trigger, the connection relationship among the groups specifically includes:

the first input end of the first group is connected with the first input end of the second group, and a connection point is used as the input end of the T trigger; the second input ends of the first group and the second group are connected, and the connection point is used as a signal end of the T trigger;

one input end of the third group is connected with the output end of the first group, one input end of the fourth group is connected with the output end of the second group, the output end of the third group is connected with the other input end of the fourth group, and the output end of the fourth group is connected with the other input end of the third group;

the output end of the third group is used as the output end of the T trigger, and the output end of the fourth group is used as the inverted output end of the T trigger;

the output end of the third group is also connected with the first input end of the second group, and the output end of the fourth group is also connected with the first input end of the first group.

According to the technical scheme, the application provides the trigger. In the trigger, each MOS transistor is connected according to a preset connection relationship to realize a corresponding trigger function, for example, set to 0 or set to 1; in addition, in the trigger, at least one MOS tube adopts an FDSOI-MOS tube, so that the leakage current of the trigger in the actual operation process is reduced, and the influence of the leakage current on the self operation is reduced; in addition, after the FDSOI-MOS tube is adopted, the FDSOI-MOS tube has extremely small threshold voltage variability, namely has better threshold voltage uniformity, and is further favorable for timing convergence of a digital integrated circuit corresponding to the trigger.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of the internal structure of a bulk silicon MOS transistor;

FIG. 2 is a schematic diagram of the internal structure of the FDSOI-MOS transistor;

FIG. 3 is a schematic diagram of the internal connections of each group of MOS transistors;

FIG. 4 is an internal schematic diagram of an SR flip-flop;

FIG. 5 is a timing diagram of an SR flip-flop;

FIG. 6 is a schematic diagram of an internal structure of a JK flip-flop;

FIG. 7 is a timing diagram of a JK flip-flop;

FIG. 8 is a schematic diagram of the internal structure of a D flip-flop;

FIG. 9 is a timing diagram of a D flip-flop;

FIG. 10 is a schematic diagram of the internal structure of a T flip-flop;

FIG. 11 is a timing diagram of a T flip-flop;

fig. 12a, 12b, 12c, and 12D are logic symbols of an SR flip-flop, a JK flip-flop, a D flip-flop, and a T flip-flop, respectively.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In this application, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In order to reduce the influence of the leakage current of the trigger on the operation of the trigger in the actual operation process, an embodiment of the present application provides a trigger, which specifically includes: a plurality of MOS tubes.

In the flip-flop, the MOS transistors are connected according to a preset connection relationship to realize corresponding functions, such as setting 0 or setting 1.

In practical application, the trigger utilizes the conduction and the cut-off of the MOS tube to realize the on and the off of the circuit, and then combines the preset connection relation among the MOS tubes to realize the corresponding function.

In the prior art, all MOS transistors in the flip-flop are bulk silicon MOS transistors, as shown in fig. 1 (only an NMOS transistor is taken as an example in the figure to show the internal structure of the bulk silicon MOS transistor):

if a forward voltage VGS is applied between the gate G and the source S, i.e., VGS > 0, SiO will be between the gate G and the P-type silicon substrate₂In the insulating layer, an electric field pointing to the P-type silicon substrate from the gate G is generated; but due to SiO₂The forward voltage VGS applied to the gate G cannot form a current due to the insulating effect of the insulating layer, so that SiO is generated₂A capacitor is formed on two sides of the insulating layer, namely VGS is equivalent to capacitor charging, and an electric field is formed at the same time; as the forward voltage VGS gradually increases, attracted by the forward voltage VGS of the gate G, a large number of electrons are accumulated on the other side of the capacitor, thereby forming an N-type electric channel from the drain D to the source S; when the forward voltage VGS of the grid G is larger than the starting voltage of the NMOS tube, the N channel starts to be conducted, and drain current is formed.

In the flip-flop provided in the embodiment of the present application, at least one of the MOS transistors is an FDSOI-MOS transistor, as shown in fig. 2 (only an NMOS transistor is shown in the drawing as an example to show the internal structure of the FDSOI-MOS transistor):

as can be seen from fig. 2 and fig. 1, compared with the bulk silicon MOS transistor, the FDSOI-MOS transistor has an extra thin buried oxide layer 10, so that the leakage between the source S and the drain D of the FDSOI-MOS transistor is greatly reduced, that is, the level value output by the FDSOI-MOS transistor is more stable; in addition, the channel between the source S and the drain D of the FDSOI-MOS transistor is not doped at all, i.e., the channel is a fully depleted region, so in this case, the FDSOI-MOS transistor has a very small threshold voltage variability, i.e., has better threshold voltage uniformity, compared to a bulk silicon MOS transistor.

Therefore, the leakage current of the trigger provided by the application in the actual operation process is reduced, so that the influence of the leakage current on the self operation is reduced; in addition, since the FDSOI-MOS transistor has better uniformity of the threshold voltage, timing convergence of the digital integrated circuit corresponding to the flip-flop is facilitated.

It should be noted that the larger the number of FDSOI-MOS transistors included in the flip-flop, the better the advantage of the FDSOI-MOS transistors can be embodied, and the number of FDSOI-MOS transistors in the flip-flop is not limited herein, and may be determined according to specific situations, and all of them are within the protection scope of the present application.

In the above flip-flop, the MOS transistors may be respectively provided in four groups, namely a first group 01, a second group 02, a third group 03, and a fourth group 04, and therefore, the preset connection relationship of the MOS transistors includes: the connection relationship among the MOS tubes in the group and the connection relationship among the groups.

Specifically, as shown in fig. 3, each group of MOS transistors includes: a first MOS transistor T1, a second MOS transistor T2, a third MOS transistor T3 and a fourth MOS transistor T4; wherein, the connection relation between each MOS pipe in the group specifically is:

the first MOS transistor T1 is connected with the common gate G of the third MOS transistor T3, and the connection point is used as an input end A of each group; the second MOS transistor T2 and the fourth MOS transistor T4 are connected with a common gate G, and the connection point is used as the other input end B of each group; the first MOS transistor T1 is connected with a common source S of the second MOS transistor T2, and the connecting point is connected with a power supply VDD; the common drain D of the first MOS transistor T1, the second MOS transistor T2 and the third MOS transistor T3 are connected, and the connection point is used as the output end L of each group; the source S of the third MOS transistor T3 is connected with the drain D of the fourth MOS transistor T4, and the source S of the fourth MOS transistor is grounded GND; vb is the connection point for the body bias.

The first MOS transistor T1 and the second MOS transistor T2 are PMOS transistors, and the third MOS transistor T3 and the fourth MOS transistor T4 are NMOS transistors.

The input and output states of each group of MOS tubes and the operating state table of each MOS tube are as follows:

A

B

T3

T1

T4

T2

L

0

0

cut-off

Conduction of

Cut-off

Conduction of

1

0

1

Cut-off

Conduction of

Conduction of

Cut-off

1

1

0

Conduction of

Cut-off

Cut-off

Conduction of

1

1

1

Conduction of

Cut-off

Conduction of

Cut-off

0

When the input end a inputs a low level (0) and the input end B inputs a low level (0), the first MOS transistor T3 and the second MOS transistor T4 are turned on, the third MOS transistor T5 and the fourth MOS transistor T6 are turned off, and the output end L outputs a high level (1).

When the input end a inputs a low level (0) and the input end B inputs a high level (1), the first MOS transistor T3 and the fourth MOS transistor T6 are turned on, the second MOS transistor T4 and the third MOS transistor T5 are turned off, and the output end L outputs a high level (1).

When the input end a inputs a high level (1) and the input end B inputs a low level (0), the first MOS transistor T3 and the fourth MOS transistor T6 are turned off, the second MOS transistor T4 and the third MOS transistor T5 are turned on, and the output end L outputs the high level (1).

When the input end a inputs a high level (1) and the input end B inputs a high level (1), the first MOS transistor T3 and the second MOS transistor T4 are turned off, the third MOS transistor T5 and the fourth MOS transistor T6 are turned on, and the output end L outputs a low level (0).

In summary, the output terminal L outputs a low level (0) only when both the input terminal a and the input terminal B input a high level (1), otherwise the output terminal L outputs a high level (1).

If the flip-flop is an SR flip-flop, the connection relationship between the groups is as shown in fig. 4, specifically:

first group 01 andany input end of the second group 02 is respectively used as a first input end 1S and a second input end 1R of the SR trigger; the other input end of the first group 01 is connected with the other input end of the second group 02, and the connection point is used as a signal end C1 of the SR trigger; any input end of the third group 03 and the fourth group 04 is respectively connected with the output ends of the first group 01 and the second group 02, the other input end of the third group 03 and the fourth group 04 is respectively connected with the output end of the other, and the output ends of the third group 03 and the fourth group 04 are respectively used as the output end Q and the reverse output end of the SR trigger

In general, an SR flip-flop is the simplest type of flip-flop, and is the basis for forming other complex flip-flops, and has a trigger function of being set to a high level (1), a low level (0), and a hold; the logical symbol is shown in FIG. 12 a; the characteristic equation is as follows:

and sxr is 0, where S is a first input of the SR flip-flop, R is a second input of the SR flip-flop,

is a negation of the second input, Q, of the SR flip-flopⁿ⁺¹Is output for the (n + 1) th time, QⁿIs the nth output.

The characteristic table is as follows:

the timing sequence is shown in fig. 5 (in the figure, CLK is a clock pulse signal and is input to the signal terminal C1 of the flip-flop):

when the first input S is low (0) and the second input R of the SR flip-flop is low (0), the output remains, that is:if the nth output Q of the SR flip-flopⁿIs low (0), the (n + 1) th time of the SR flip-flop outputs Qⁿ⁺¹Is low (0), if the n-th output Q of the SR flip-flop isⁿHigh level (1), the (n + 1) th time of the SR flip-flop outputs Qⁿ⁺¹Is high (1).

When the first input S is at low level (0) and the second input R of the SR flip-flop is at high level (1), the output of the SR flip-flop is at low level (0), that is: no matter the nth output Q of SR flip-flopⁿLow level (0) or high level (1), and the (n + 1) th time outputs Qⁿ⁺¹Are all low (0).

When the first input S is at high level (1) and the second input R of the SR flip-flop is at low level (0), the output of the SR flip-flop is at high level (1), that is: no matter the nth output Q of SR flip-flopⁿLow level (0) or high level (1), and the (n + 1) th time outputs Qⁿ⁺¹Are all high (1).

When the first input S is high (1) and the second input R of the SR flip-flop is high (1), the output of the SR flip-flop is indeterminate.

If the flip-flop is a JK flip-flop, the connection relationship between the groups is, as shown in fig. 6, specifically:

the first input end of the first group 01 is used as a first input end 1J of the JK trigger; the first input terminal of the second group 02 is used as a second input terminal 1K of the JK trigger; the second input ends of the first group 01 and the second group 02 are connected, and the connection point is used as a signal end C1 of the JK trigger; one input end of the third group 03 is connected with the output end of the first group 01, one input end of the fourth group 04 is connected with the output end of the second group 02, the output end of the third group 03 is connected with the other input end of the fourth group 04, and the output end of the fourth group 04 is connected with the other input end of the third group 03; the output end of the third group 03 is used as the output end Q of the JK trigger, and the output end of the fourth group 04 is used as the reverse output end of the JK trigger

The outputs of the third group 03 are further connected to the first inputs of the second group 02 and the outputs of the fourth group 04 are further connected to the first inputs of the first group 01.

In general, the JK flip-flop is the flip-flop with the strongest logic function in all logic flip-flops, and has the functions of holding, setting to high level (1), setting to low level (0) and flipping, and the logic symbol thereof is as shown in fig. 12 b; the characteristic equation is as follows:

wherein J is a first input of the JK flip-flop, K is a second input of the JK flip-flop, QⁿFor the nth output of the JK flip-flop,

is the nth output Q of a JK flip-flopⁿIs not value, Qⁿ⁺¹For the (n + 1) th output of the JK flip-flop,

is the negation of the second input K of the JK flip-flop.

The characteristic table is as follows:

J	K	Qn	Qn+1
				0	0	0	0
0	0	1	1
				0	1	0	0
0	1	1	0
				1	0	0	1
1	0	1	1
				1	1	0	1
1	1	1	0

the timing sequence is shown in fig. 7 (in the figure, CLK is a self-clock signal, and is input to the signal terminal C1 of the flip-flop):

when the first input J of the JK flip-flop is low (0) and the second input K is low (0), the output of the JK flip-flop is maintained, that is: if the nth output Q of the JK flip-flopⁿIs at a low level (0) and,the (n + 1) th output Q of the JK flip-flopⁿ⁺¹Also low (0), if the Nth output Q of the JK flip-flop isⁿHigh level (1), the (n + 1) th time of the JK flip-flop outputs Qⁿ⁺¹Is high (1).

When the first input J of the JK flip-flop is at a low level (0) and the second input K is at a high level (1), the output of the JK flip-flop is at a low level (0), that is: no matter the nth output Q of the JK triggerⁿThe (n + 1) th output Q of the JK trigger is low level (0) or high level (1)ⁿ⁺¹Are all low (0).

When the first input J of the JK trigger is at high level (1) and the second input K is at low level (0), the output of the JK trigger is at high level (1), i.e. no matter the nth output Q of the JK triggerⁿThe (n + 1) th output Q of the JK trigger is low level (0) or high level (1)ⁿ⁺¹Are all high (1).

When the first input J of the JK flip-flop is high level (1) and the second input K is high level (1), the output of the JK flip-flop is inverted, that is: if the nth output Q of the JK flip-flopⁿIs low (0), the (n + 1) th time of the JK flip-flop outputs Qⁿ⁺¹Is high (1), if the n-th output Q of the JK flip-flopⁿHigh level (1), the (n + 1) th time of the JK flip-flop outputs Qⁿ⁺¹Is low (0).

If the flip-flop is a D flip-flop, the connection relationship between the groups is, as shown in fig. 8, specifically:

one input end of the first group 01 is used as an input end 1D of the D trigger; an input end of the second group 02 is connected with the output end of the first group 01; the other input end of the first group 01 is connected with the other input end of the second group 02, and the connection point is used as a signal end C1 of the D trigger; the output end of the first group 01 is connected with one input end of the third group 03, and the output end of the second group 02 is connected with one input end of the fourth group 04; the other input end of the third group 03 is connected with the output end of the fourth group 04; the other input end of the fourth group 04 is connected with the output end of the third group 03; the output end of the third group 03 is used as the output end Q of the D flip-flop, and the output end of the fourth group 04 is used as the inverted output end of the D flip-flop

In general, the logical sign of the D flip-flop is as shown in FIG. 12 c; the secondary state of the D flip-flop, i.e. the new state, depends on the input D itself before triggering, so the D flip-flop has two triggering functions, i.e. set to low level (0) and set to high level (1); the characteristic equation is as follows: qⁿ⁺¹D, where D is the input of the D flip-flop, high level is denoted by 1, low level is denoted by 0; qⁿ⁺¹Is the output of the n +1 th time of the D flip-flop.

The characteristic table is shown below (Q in the table)ⁿFor the nth output of the D flip-flop):

D	Qn	Qn+1
			0	0	0
0	1	0
			1	0	1
1	1	1

the timing sequence is shown in fig. 9 (in the figure, CLK is a self-clock signal, and is input to the signal terminal C1 of the flip-flop):

when the input D of the D flip-flop is at low level (0) and the clock pulse signal is at high level (1), the nth output Q of the D flip-flopⁿLow (0); when the input D of the D flip-flop is at high level (1) and the clock pulse signal is at high level (1), the nth output Q of the D flip-flopⁿHigh (1); when the clock pulse signal CP of the D flip-flop is at low level (0), the output of the D flip-flop is latched, i.e. Q is output from the n +1 th time of the D flip-flopⁿ⁺¹Equal to the input D of the D flip-flop before triggering.

If the flip-flop is a T flip-flop, the connection relationship between the groups is, as shown in fig. 10, specifically:

the first input end of the first group 01 is connected with the first input end of the second group 02, and the connection point is used as the input end 1T of the T trigger; the second input ends of the first group 01 and the second group 02 are connected, and the connection point is used as a signal end C1 of the T trigger; one input end of the third group 03 is connected with the output end of the first group 01, one input end of the fourth group 04 is connected with the output end of the second group 02, the output end of the third group 03 is connected with the other input end of the fourth group 04, and the output end of the fourth group 04 is connected with the other input end of the third group 03; the output end of the third group 03 is used as the output end Q of the T trigger, and the output end of the fourth group 04 is used as the reverse output end of the T trigger

The outputs of the third group 03 are further connected to the first inputs of the second group 02 and the outputs of the fourth group 04 are further connected to the first inputs of the first group 01.

In general, the T flip-flop may have a hold or flip-flop function according to the difference of its own input T; the logical sign is shown in FIG. 12 d; the characteristic equation is as follows:

wherein T is the input of a T trigger,

is a negation of the input of a T flip-flop, QⁿIs the nth output, Q, of a JK flip-flopⁿ⁺¹Is the n +1 th output of the JK flip-flop.

The characteristic table is as follows:

T	Qn	Qn+1
			0	0	0
0	1	1
			1	0	1
1	1	0

the timing sequence is shown in fig. 11 (in the figure, CLK is a self-clock signal, and is input to the signal terminal C1 of the flip-flop):

when the input T of the T flip-flop is low (0), the output remains, i.e.: if the nth output Q of the T flip-flopⁿLow (0), the n +1 th time of the T flip-flop outputs Qⁿ⁺¹Is low (0), if the nth output of the T flip-flopQⁿHigh level (1), Q of the n +1 th time of T triggerⁿ⁺¹Is high (1).

When the input T of the T flip-flop is high (1), the output flips, i.e.: if the nth output Q of the T flip-flopⁿLow (0), the n +1 th time of the T flip-flop outputs Qⁿ⁺¹Is high, if the nth output Q of the T triggerⁿHigh level (1), the n +1 th time of T trigger outputs Qⁿ⁺¹Is low (0).

The above description is only four basic triggers, and in practical applications, including but not limited to the above embodiments, the basic triggers are not specifically limited herein, and may be within the protection scope of the present application.

In the above description of the disclosed embodiments, features described in various embodiments in this specification can be substituted for or combined with each other to enable those skilled in the art to make or use the present application. The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention. The invention is not limited to the embodiments described herein, but is capable of other embodiments according to the invention, and may be used in various other applications, including, but not limited to, industrial, or industrial. Therefore, any simple modification, equivalent change and modification made to the above embodiments by the technical entity of the present invention all still fall within the protection scope of the technical solution of the present invention, where the technical entity does not depart from the content of the technical solution of the present invention.

Claims (8)

1. A flip-flop, comprising: a plurality of MOS tubes; wherein:

the MOS tubes are connected according to a preset connection relation; the preset connection relation is the connection relation of the trigger to realize the function of the trigger;

at least one MOS tube is an FDSOI-MOS tube.

2. The flip-flop according to claim 1, wherein the MOS transistors are divided into four groups, and the predetermined connection relationship includes: the connection relationship between the MOS tubes in each group and the connection relationship between the MOS tubes in each group.

3. The flip-flop according to claim 2, wherein each of said MOS transistors comprises: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor; the connection relation among the MOS tubes in the group is as follows:

the first MOS tube is connected with the third MOS tube in a common grid mode, and a connection point is used as an input end of each group;

the second MOS tube and the fourth MOS tube are connected in a common grid mode, and a connection point is used as the other input end of each group;

the first MOS tube is connected with the second MOS tube in a common source mode, and a connecting point is connected with a power supply;

the first MOS tube, the second MOS tube and the third MOS tube are connected in a common drain electrode mode, and a connection point is used as an output end of each group;

the source electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube, and the source electrode of the fourth MOS tube is grounded;

the first MOS tube and the second MOS tube are PMOS tubes, and the third MOS tube and the fourth MOS tube are NMOS transistors.

4. The flip-flop according to claim 2 or 3, wherein four sets of said MOS transistors are respectively: a first group, a second group, a third group and a fourth group.

5. The flip-flop according to claim 4, wherein if the flip-flop is an SR flip-flop, the connection relationship between the groups is specifically:

any input end of the first group and the second group is respectively used as a first input end and a second input end of the SR trigger;

the other input end of the first group is connected with the other input end of the second group, and the connection point is used as a signal end of the SR trigger;

and any input end of the third group and the fourth group is respectively connected with the output ends of the first group and the second group, the other input end of the third group and the fourth group is respectively connected with the output end of the other group, and the output ends of the third group and the fourth group are respectively used as the output end and the reverse output end of the SR trigger.

6. The flip-flop according to claim 4, wherein if the flip-flop is a JK flip-flop, the connection relationship between the groups is specifically:

the first input end of the first group is used as a first input end of the JK trigger; the first input end of the second group is used as a second input end of the JK trigger; the second input ends of the first group and the second group are connected, and the connection point is used as a signal end of the JK trigger;

one input end of the third group is connected with the output end of the first group, one input end of the fourth group is connected with the output end of the second group, the output end of the third group is connected with the other input end of the fourth group, and the output end of the fourth group is connected with the other input end of the third group;

the output end of the third group is used as the output end of the JK trigger, and the output end of the fourth group is used as the reverse output end of the JK trigger;

the output end of the third group is also connected with the first input end of the second group, and the output end of the fourth group is also connected with the first input end of the first group.

7. The flip-flop according to claim 4, wherein if the flip-flop is a D flip-flop, the connection relationship between the groups specifically is:

one input end of the first group is used as the input end of the D trigger; one input end of the second group is connected with the output end of the first group;

the other input end of the first group is connected with the other input end of the second group, and the connection point is used as a signal end of the D trigger;

the output end of the first group is connected with one input end of the third group, and the output end of the second group is connected with one input end of the fourth group;

the other input end of the third group is connected with the output end of the fourth group; the other input end of the fourth group is connected with the output end of the third group;

and the output end of the third group is used as the output end of the D trigger, and the output end of the fourth group is used as the reverse output end of the D trigger.

8. The flip-flop according to claim 4, wherein if the flip-flop is a T flip-flop, the connection relationship between the groups specifically is:

the first input end of the first group is connected with the first input end of the second group, and a connection point is used as the input end of the T trigger; the second input ends of the first group and the second group are connected, and the connection point is used as a signal end of the T trigger;

one input end of the third group is connected with the output end of the first group, one input end of the fourth group is connected with the output end of the second group, the output end of the third group is connected with the other input end of the fourth group, and the output end of the fourth group is connected with the other input end of the third group;

the output end of the third group is used as the output end of the T trigger, and the output end of the fourth group is used as the inverted output end of the T trigger;

the output end of the third group is also connected with the first input end of the second group, and the output end of the fourth group is also connected with the first input end of the first group.

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