CN214473586U

CN214473586U - Detection device for sampling input end isolation voltage

Info

Publication number: CN214473586U
Application number: CN202120525073.8U
Authority: CN
Inventors: 李军町; 赵志华; 张大维
Original assignee: Beijing Aerospace Changfeng Co Ltd
Current assignee: Beijing Aerospace Changfeng Co Ltd
Priority date: 2021-03-12
Filing date: 2021-03-12
Publication date: 2021-10-22
Anticipated expiration: 2031-03-12

Abstract

The utility model relates to a detection device for input isolation voltage sampling, including keeping apart sampling circuit, rectifier circuit and converting circuit, keep apart sampling circuit and will input the BUS power and convert to keeping apart the sampling port to PGND's linear proportional of voltage, keep apart the sampling port and be connected to rectifier circuit, after rectifier circuit's rectification, export converting circuit, through converting circuit operational amplification output to CPU sampling port, realize isolation voltage's conversion. The utility model provides a current isolated chip switching power supply disturb, detection voltage distortion, miniaturized design difficulty, inefficiency scheduling problem.

Description

Detection device for sampling input end isolation voltage

Technical Field

The utility model belongs to the power electronics field, concretely relates to a detection device that is used for module switch power input isolated voltage to sample.

Background

At present, on the basis of a miniaturization design scheme of a module switching power supply, the design of high-efficiency soft switching, high-power density digitization, isolation magnetic integration topology and other schemes is the best path for developing high-power density module switching power supply products. In order to meet the requirements of sampling precision and control design simplification, most of the existing designs adopt an isolation chip to carry out isolation sampling design, a sampling voltage division network and the isolation chip are large in size, high in power consumption and high in cost, and meanwhile, signal processing after isolation is complex and inflexible, and the miniaturization design optimization of the high-power-density module switching power supply is seriously influenced.

Disclosure of Invention

An object of the utility model is to the above-mentioned problem, provide a detection device for input isolation voltage sampling, utilize isolating circuit, rectifier circuit and converting circuit, accomplish input voltage's isolation and detect, guarantee the reliability and the miniaturization of design.

The technical scheme of the utility model as follows:

a detection device for input end isolation voltage sampling is characterized in that: including keeping apart sampling circuit, rectifier circuit and converting circuit, wherein:

the isolation sampling circuit comprises an isolation transformer, an NMOS tube Q1, a capacitor C1 and a diode D1; one end of an input side winding T4B of the isolation transformer is connected to an input power BUS, the other end of the input side winding T4B of the isolation transformer is connected to a drain pin of an NMOS tube Q1, a GATE of Q1 is connected to a GATE driving signal, a source of Q1 is connected to a PGND input ground, an output side winding T4E of the isolation transformer and T4B are in linear proportion relation, one end of T4E is connected with an isolation sampling port V1 and one end of C1, the other end of T4E is connected with another isolation sampling port V2 and a cathode of D1, and an anode of D1 and the other end of C1 are connected to an SGND ground together;

the rectifying circuit comprises capacitors C3, C4, C5 and Cout, a PMOS tube P1, an NMOS tube Q2, resistors R1, R2, R3, R4, R5 and R6, and bidirectional voltage-stabilizing tubes DZ1 and DZ 2; one end of C3 is connected with a port V1 led out from the isolation sampling circuit, the other end of C3 is connected with one end of R1 and the drain of P1, the other end of R1 is connected with a port V2 led out from the isolation sampling circuit, the source of P1 is simultaneously connected with one ends of C5, R3, a bidirectional voltage regulator tube DZ2 and Cout, and is connected with the grid of a rectification output port VO +, the other end of P1 and the other ends of C5, R3 and bidirectional voltage regulator tube DZ2 are respectively connected with one end of R4, the other end of R4 is connected with the drain of an NMOS tube Q2, and the other end of Cout is simultaneously connected with the source of an NMOS tube Q2, one end of R2, one end of a bidirectional voltage regulator tube DZ1 and the end of an isolation sampling port V1 and is connected with the rectification output port VO-; the grid of the NMOS tube Q2 is connected with the other ends of the R2 and the bidirectional voltage regulator tube DZ1 and is connected with one end of the C4, and the other end of the C4 is connected with the V2 end of the isolation sampling circuit; one end of R5 and R6 are connected with the rectification output port Vo + after being connected in series, and the other end is connected with the rectification output port Vo-;

the conversion circuit comprises resistors R7, R8, R9 and R10 and an operational amplifier U1B; one end of R7 is connected with the output port VO + of the rectifier circuit, and the other end is connected with one end of R9 and the 5 pins of U1B; one end of R8 is connected with the output port Vo of the rectification circuit, and the other end is connected with the 6 pin of U1B and one end of R10; the other end of R9 is connected to SGND ground, and the other end of R10 is connected to pin 7 of U1B and the output terminal VBUS of the conversion circuit.

The utility model discloses the circuit provides the design of keeping apart sampling, rectification to the conversion, has solved input/output isolation, switching power supply interference, detection voltage distortion, miniaturized design difficulty, inefficiency scheduling problem.

Drawings

FIG. 1 is a logical block diagram of the present invention;

fig. 2 is an isolated sampling circuit diagram of the present invention;

FIG. 3 is a rectification circuit diagram of the present invention;

fig. 4 is a conversion circuit diagram of the present invention.

Detailed Description

As shown in FIG. 1, the utility model discloses an keep apart sampling circuit unit, rectifier circuit unit and converting circuit unit. The isolation sampling circuit unit converts the linear direct ratio of the voltage of the input BUS power supply to the PGND to an isolation sampling port, the isolation sampling port is connected to the rectification circuit, the voltage is output to the conversion circuit after being rectified by the rectification circuit, and the voltage is output to the CPU sampling port after being amplified by the conversion circuit, so that the conversion of the isolation voltage is realized.

As shown in fig. 2, the isolation sampling circuit unit includes an isolation transformer, an NMOS transistor Q1, a capacitor C1, and a diode D1; one end of an input side winding T4B of the isolation transformer is connected to an input power BUS, the other end of the input side winding T4B of the isolation transformer is connected to a drain pin of an NMOS tube Q1, a GATE of Q1 is connected to a GATE driving signal, a source of Q1 is connected to a PGND input ground, an output side winding T4E of the isolation transformer and T4B are in linear proportion relation, one end of T4E is connected with an isolation sampling port V1 and one end of C1, the other end of T4E is connected with another isolation sampling port V2 and a cathode of D1, and an anode of D1 and the other end of C1 are connected to an SGND ground together; PGND is the BUS power supply ground reference potential.

As shown in fig. 3, the rectifier circuit includes capacitors C3, C4, C5, Cout, a PMOS transistor P1, an NMOS transistor Q2, resistors R1, R2, R3, R4, R5, R6, bidirectional voltage regulators DZ1 and DZ 2; one end of C3 is connected with a port V1 led out from the isolation sampling circuit, the other end of C3 is connected with one end of R1 and the drain electrode of a PMOS tube P1, the other end of R1 is connected with a port V2 led out from the isolation sampling circuit, the source electrode of the PMOS tube P1 is simultaneously connected with one end of a capacitor C5, a resistor R3, a bidirectional voltage regulator tube DZ2 and Cout and is connected with a rectification output port VO +, the grid electrode of P1 and the other ends of C5, R3 and bidirectional voltage regulator tube DZ2 are respectively connected with one end of R4, the other end of R4 is connected with the drain electrode of an NMOS tube Q2, the other end of Cout is simultaneously connected with the source electrode of an NMOS tube Q2, one end of R2, one end of the bidirectional voltage regulator tube DZ1 and the end of an isolation sampling port V1 and is connected with the rectification output port VO-; the grid of the NMOS tube Q2 is connected with the other ends of the R2 and the bidirectional voltage regulator tube DZ1 and is connected with one end of the C4, and the other end of the C4 is connected with the V2 end of the isolation sampling circuit; one end of R5 and R6 are connected with the rectification output port Vo + after being connected in series, and the other end is connected with the rectification output port Vo-;

as shown in fig. 4, the conversion circuit includes resistors R7, R8, R9, R10, and an operational amplifier U1B; one end of R7 is connected with the output port VO + of the rectifier circuit, and the other end is connected with one end of R9 and the 5 pins of U1B; one end of R8 is connected with the output port Vo of the rectification circuit, and the other end is connected with the 6 pin of U1B and one end of R10; the other end of R9 is connected to SGND ground, and the other end of R10 is connected to pin 7 of U1B and the output terminal VBUS of the conversion circuit. SGND is the reference potential of the sampled voltage signal VBUS.

The utility model discloses the theory of operation as follows:

the isolation sampling circuit enables the reference voltage of the input BUS power supply to PGND to be linearly proportional to two ports of V1 and V2 through the connection and disconnection of an isolation transformer and an NMOS tube Q1, and square wave voltage collection is achieved.

In the rectifier circuit unit, the level relation of V1 and V2 is positive and negative square wave voltage, when the two ends of V2 and V1 are positive potential difference, the positive electric potential of V1 passes through a PMOS tube P1, a resistor R1 and a capacitor Cout to complete charging and filtering of voltage on the input side, VO + at the two ends of Cout at the moment corresponds to VBUS linear proportional voltage, R2 and C4 filter the voltage at the two ends of V1 and V2 to enable the voltage of a resistor R2 with the parallel connection of a grid and a source of Q2 to be positive voltage, so that the conduction of Q2 is realized, meanwhile, Q2, R4, R3 and C5 divide the voltage of t, so that the voltage at the two ends of the grid and the source of the PMOS P1 and the R3 at the sides is reverse voltage, the conduction of P1 is realized, and the lossless sampling of the voltage on the input side is completed; under the condition that the two ends of V2 and V1 are negative potential difference, the reverse voltages of V2 and V1 are filtered by R2 and C4, the voltage of a resistor R2 with the grid electrode and the source electrode of Q2 connected in parallel is the reverse voltage, Q2 is turned off, the voltage of the grid electrode and the source electrode of a PMOS tube P1 is not the reverse voltage, P1 is turned off, Cout discharge is blocked, isolation sampling and holding of the voltage on the input side are completed, and the VO + and VO-voltages of Cout are linearly proportional to the voltage of VBUS to PGND by a rectifier circuit unit;

in the conversion circuit, one end of R7 is connected with the output port VO + of the rectification circuit, and the other end is connected with one end of R9 and the 5 pins of U1B; one end of R8 is connected with the output port Vo of the rectification circuit, and the other end is connected with the 6 pin of U1B and one end of R10; the other end of R9 is connected to SGND ground terminal, and the other end of R10 is connected with pin 7 of U1B and converting circuit output end VBUS and accomplishes the voltage attenuation, uses the difference proportion amplifying circuit, attenuates the proportion of corresponding R10/R8, realizes that VO + and VO-both ends difference voltage convert into VBUS to SGND voltage signal, and nimble application is in the CPU sampling port, realizes the purpose of input end isolation voltage sampling.

Claims

1. A detection device for input end isolation voltage sampling is characterized in that: including keeping apart sampling circuit, rectifier circuit and converting circuit, wherein: