CN214429520U - Signal amplitude adjusting and power dividing module - Google Patents
Signal amplitude adjusting and power dividing module Download PDFInfo
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- CN214429520U CN214429520U CN202120752843.2U CN202120752843U CN214429520U CN 214429520 U CN214429520 U CN 214429520U CN 202120752843 U CN202120752843 U CN 202120752843U CN 214429520 U CN214429520 U CN 214429520U
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Abstract
The utility model discloses a module is divided with merit to signal amplitude regulation, divide the ware circuit including feeder circuit, power amplifier circuit, adjustable attenuator circuit, control circuit, equalizer circuit and merit, the feeder circuit comprises inductance L4, electric capacity C2, electric capacity C6 and electric capacity C9, and inductance L4 connects behind electric capacity C2 and electric capacity C6, connects the 5V direct current, and electric capacity C9 connects behind inductance L4, connects radio frequency input signal RFin; the power amplifier circuit is composed of a chip U2, a pin 3 of the chip U2 is connected with a capacitor C9, a pin 6 of the chip U2 is connected with a capacitor C7 and an inductor L3, and meanwhile, an inductor L3 is connected with a capacitor C3 and then connected with 5V direct current. The signal amplitude adjusting and power dividing module can flexibly adjust the amplitude of an input signal, divides the signal into three paths, conveniently performs various processing on a received signal, and has the advantages of compact structure, miniaturization and cost saving.
Description
Technical Field
The utility model relates to a radio frequency communication technical field specifically is a module is divided with merit to signal amplitude modulation.
Background
In modern communication systems such as wireless communication, mobile communication, radar, remote measurement and control, satellite communication, electronic countermeasure and the like, signals need to be amplified, attenuated, equalized, power-divided and the like, particularly when an array antenna technology is adopted, signals of a plurality of channels need to be amplified, attenuated, equalized, power-divided and the like, and in addition, when a beam forming technology is adopted, signal amplitude and phase values needed by each channel are different, so that how to flexibly adjust the amplitude of input signals becomes a main problem to be solved.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a module is divided with merit to signal amplitude modulation, can be nimble carry out amplitude modulation to input signal, divide into three routes with the signal simultaneously, and the convenience carries out multiple processing to received signal, has compact structure, can miniaturize, practices thrift the advantage of cost, can solve the problem among the prior art.
In order to achieve the above object, the utility model provides a following technical scheme: a signal amplitude regulation and power division module comprises a feed circuit, a power amplifier circuit, an adjustable attenuator circuit, a control circuit, an equalizer circuit and a power divider circuit, wherein the feed circuit consists of an inductor L4, a capacitor C2, a capacitor C6 and a capacitor C9, the inductor L4 is connected with a 5V direct current after being connected with a capacitor C2 and a capacitor C6, and the capacitor C9 is connected with an inductor L4 and then is connected with a radio frequency input signal RFin; the power amplifier circuit consists of a chip U2, wherein a pin 3 of the chip U2 is connected with a capacitor C9, a pin 6 of the chip U2 is connected with a capacitor C7 and an inductor L3, and meanwhile, an inductor L3 is connected with 5V direct current after being connected with a capacitor C3;
the adjustable attenuator circuit consists of a chip U1, the control circuit consists of an output exclusion RP1 and a dial switch SW1, a pin 4 of the chip U1 is connected with a capacitor C7, a pin 2 of the chip U1 is connected with a capacitor C1 and a capacitor C4 and then connected with 5V direct current, pins 19, 20, 21, 22, 23 and 24 of the chip U1 are respectively connected with circuit interfaces of a pin 1, a pin 2, a pin 3, a pin 4, a pin 5 and a pin 6 of the dial switch SW1, and a pin 1, a pin 2, a pin 3, a pin 4, a pin 5 and a pin 6 of the switch SW1 are connected with the output exclusion RP 1;
the equalizer circuit consists of an inductor L1, an inductor L2, an inductor L5, an inductor L6, an inductor L7, an inductor L8, an inductor L9, a resistor R5, a resistor R6, a resistor R7, a capacitor C5, a capacitor C11 and a capacitor C12, wherein the resistor R5 is connected with the resistor R6 in series, meanwhile, the resistor R5 is connected with the inductor L5 and the inductor L6, the resistor R6 is connected with the inductor L7 and the inductor L8, the resistor R7 is connected with the capacitor C11 in series, meanwhile, the resistor R7 is connected with a circuit interface formed by connecting the resistor R7 with the resistor R7 in series, the capacitor C7 is connected with a circuit interface formed by connecting the capacitor C7 with the inductor L7 in series, the capacitor C7 is connected with a circuit interface formed by connecting the resistor R7 in parallel, and the inductor L7 are connected with the capacitor C7 in parallel;
the power divider circuit is composed of a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R8, a resistor R9, a resistor R10 and a resistor R11, wherein the resistor R1 is connected with a resistor R2 in parallel, the resistor R3 is connected with a resistor R4 in parallel, the resistor R8 is connected with a resistor R9 in parallel, and the resistor R10 is connected with a resistor R11 in parallel.
Preferably, the 15 pins of the chip U1 are connected to the capacitor C8, and the capacitor C8 is connected to the inductor L5 and the inductor L6.
Preferably, the inductor L8 is connected to a resistor R1 and a resistor R2 connected in parallel, a resistor R3 and a resistor R4 connected in parallel, a resistor R8 and a resistor R9 connected in parallel, and a resistor R10 and a resistor R11 connected in parallel, and then outputs video signals RFout1, RFout2, and RFout 3.
Preferably, the model of the chip U2 is PSA-0012, and the model of the chip U1 is HMC 472A.
Compared with the prior art, the beneficial effects of the utility model are as follows:
the signal amplitude adjusting and power dividing module feeds a direct current 5V power supply into a radio frequency cable through an interface of a radio frequency signal input end through a set feed circuit so as to supply power to front-end electric equipment, a power amplifier circuit amplifies a radio frequency input signal, an adjustable attenuator circuit performs amplitude attenuation on the signal under the control of a control circuit so as to flexibly adjust attenuation, an equalizer circuit is used for compensating a low-frequency signal with low loss and a high-frequency signal with high loss, and a power divider circuit performs power distribution on the signal so as to divide one path of signal into multiple paths of signals; therefore, the module can flexibly adjust the amplitude of the input signal, simultaneously divides the signal into three paths, is convenient to carry out various processing on the received signal, and has the advantages of compact structure, miniaturization and cost saving.
Drawings
Fig. 1 is a circuit diagram of a feeding and power amplifier of the present invention;
FIG. 2 is a diagram of the adjustable attenuator and control circuit of the present invention;
fig. 3 is a circuit diagram of the equalizer of the present invention;
fig. 4 is a circuit diagram of the power divider of the present invention.
In the figure: 1. a feed circuit; 2. a power amplifier circuit; 3. an adjustable attenuator circuit; 4. a control circuit; 5. an equalizer circuit; 6. provided is a power divider circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, a signal amplitude adjusting and power dividing module includes a feed circuit 1, a power amplifier circuit 2, an adjustable attenuator circuit 3, a control circuit 4, an equalizer circuit 5, and a power divider circuit 6, where the feed circuit 1 includes an inductor L4, a capacitor C2, a capacitor C6, and a capacitor C9, the inductor L4 is connected to a capacitor C2 and a capacitor C6, and then connected to a 5V dc power, and the capacitor C9 is connected to an inductor L4, and then connected to a radio frequency input signal RFin; the power amplifier circuit 2 is composed of a chip U2, a pin 3 of the chip U2 is connected with a capacitor C9, a pin 6 of the chip U2 is connected with a capacitor C7 and an inductor L3, and meanwhile, an inductor L3 is connected with a capacitor C3 and then connected with 5V direct current.
In the above, the dc 5V power supply provides dc power for the front-end device through the capacitor C2, the capacitor C6, the inductor L4, and the radio frequency input port RFin, and the radio frequency input signal enters the power amplifier circuit 2 through the inductor L4 and the capacitor C9, wherein the capacitor C2 and the capacitor C6 filter the input 5V dc power, the capacitor C2 mainly filters low-frequency noise, the capacitor C6 mainly filters high-frequency noise, the capacitor C9 prevents the dc power from entering the power amplifier, and the inductor L4 prevents the radio frequency signal from entering the 5V power supply; radio frequency input signals enter a chip U2 through a capacitor C9, are amplified and output, and pass through an inductor L3, a capacitor C7 and an adjustable attenuator circuit 3, wherein the capacitor C7 plays a role of cutting off direct current, the inductor L3 prevents the radio frequency signals from entering a 5V power supply, and the capacitor C3 filters the input 5V direct current.
Referring to fig. 2, the adjustable attenuator circuit 3 is composed of a chip U1, the control circuit 4 is composed of an output resistor RP1 and a dial switch SW1, a pin 4 of the chip U1 is connected to a capacitor C7, a pin 2 of the chip U1 is connected to a capacitor C1 and a capacitor C4 and then connected to dc power of 5V, pins 19, 20, 21, 22, 23 and 24 of the chip U1 are respectively connected to circuit interfaces of pins 1, 2, 3, 4, 5 and 6 of the dial switch SW1, pins 1, 2, 3, 4, 5 and 6 of the switch SW1 are connected to the output resistor RP1, a pin 15 of the chip U1 is connected to the capacitor C8, and the capacitor C8 is connected to the inductor L5 and the inductor L6.
In the above, the input radio frequency signal is attenuated by the chip U1 and then output, and is input to the equalizer circuit 5 through the capacitor C8, and the voltage of the chip U1 is controlled by turning on and off each path of the dial switch SW1, so that six control ports of the chip U1 are controlled to realize any combination, and control of sixty-four attenuation states is realized.
Referring to fig. 3, the equalizer circuit 5 includes an inductor L1, an inductor L2, an inductor L5, an inductor L6, an inductor L7, an inductor L8, an inductor L9, a resistor R5, a resistor R6, a resistor R7, a capacitor C5, a capacitor C11, and a capacitor C12, the resistor R5 is connected in series with the resistor R6, the resistor R5 is connected with the inductor L5 and the inductor L6, the resistor R6 is connected with the inductor L7 and the inductor L8, the resistor R7 is connected in series with the capacitor C11, the resistor R7 is connected with a circuit interface formed by connecting the resistor R7 and the resistor R7 in series, the capacitor C7 is connected with a circuit interface formed by connecting the capacitor C7 and the inductor L7 in series, the capacitor C7 is connected with a circuit interface formed by connecting the resistor R7, the inductor L7 is connected in parallel with the capacitor C7 and the inductor L7.
In the above, the inductor L5 and the inductor L6 play a role in input port impedance matching, the capacitor C7 and the capacitor C11 play a role in output port impedance matching, the resistor R5, the resistor R6 and the resistor R7 form a pi-type attenuator, the attenuation of the attenuator is the balance of an equalizer, the capacitor C12 and the inductor L9 form a series resonant circuit, the resonant frequency is greater than or equal to the maximum value of the module operating frequency, the capacitor C5, the inductors L1 and L2 form parallel resonance, the resonant frequency is less than or equal to the minimum value of the module operating frequency, the capacitor C7 and the inductor L11 form a series resonant circuit, the resonant frequency is less than or equal to the minimum value of the module operating frequency, the capacitor C8 and the inductor L9 form parallel resonance, and the resonant frequency is greater than or equal to the maximum value of the module operating frequency.
Referring to fig. 4, the power divider circuit 6 includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R8, a resistor R9, a resistor R10, and a resistor R11, the resistor R1 is connected in parallel with the resistor R2, the resistor R3 is connected in parallel with the resistor R4, the resistor R8 is connected in parallel with the resistor R9, the resistor R10 is connected in parallel with the resistor R11, the inductor L8 is connected with the parallel resistor R1 and the resistor R2, the parallel resistor R3 and the resistor R4, the parallel resistor R8 and the resistor R9, and the parallel resistor R10 and the resistor R11, and then outputs video signals RFout1, RFout2, and RFout 3.
In the above, the model of the chip U2 is PSA-0012, and the model of the chip U1 is HMC 472A.
The signal amplitude adjusting and power dividing module feeds a direct current 5V power supply into a radio frequency cable through an interface of a radio frequency signal input end through a set feed circuit 1 so as to supply power to front-end electric equipment, a power amplifier circuit 2 amplifies a radio frequency input signal, an adjustable attenuator circuit 3 attenuates the amplitude of the signal under the control of a control circuit 4 so as to flexibly adjust the attenuation amount, an equalizer circuit 5 is used for compensating a low-frequency signal with small loss and a high-frequency signal with large loss, a power divider circuit 6 distributes the power of the signal and divides one path of signal into multiple paths of signals; therefore, the module can flexibly adjust the amplitude of the input signal, simultaneously divides the signal into three paths, is convenient to carry out various processing on the received signal, and has the advantages of compact structure, miniaturization and cost saving.
In summary, the following steps: the signal amplitude adjusting and power dividing module can flexibly adjust the amplitude of an input signal, simultaneously divides the signal into three paths, is convenient to carry out various processing on a received signal, and has the advantages of compact structure, miniaturization and cost saving, thereby effectively solving the problems of the prior art.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. The utility model provides a module is divided with merit to signal amplitude regulation, includes feeder circuit (1), power amplifier circuit (2), adjustable attenuator circuit (3), control circuit (4), equalizer circuit (5) and merit and divides ware circuit (6), its characterized in that: the feed circuit (1) consists of an inductor L4, a capacitor C2, a capacitor C6 and a capacitor C9, wherein the inductor L4 is connected with 5V direct current after being connected with the capacitor C2 and the capacitor C6, and the capacitor C9 is connected with a radio frequency input signal RFin after being connected with the inductor L4; the power amplifier circuit (2) is composed of a chip U2, a pin 3 of a chip U2 is connected with a capacitor C9, a pin 6 of a chip U2 is connected with a capacitor C7 and an inductor L3, and meanwhile, an inductor L3 is connected with a capacitor C3 and then connected with 5V direct current;
the adjustable attenuator circuit (3) is composed of a chip U1, the control circuit (4) is composed of an output exclusion RP1 and a dial switch SW1, a 4 pin of the chip U1 is connected with a capacitor C7, a 2 pin of the chip U1 is connected with a capacitor C1 and a capacitor C4 and then connected with 5V direct current, a 19 pin, a 20 pin, a 21 pin, a 22 pin, a 23 pin and a 24 pin of the chip U1 are respectively connected with a 1 pin, a 2 pin, a 3 pin, a 4 pin, a 5 pin and a 6 pin circuit interface of the dial switch SW1, and a 1 pin, a 2 pin, a 3 pin, a 4 pin, a 5 pin and a 6 pin of the switch SW1 are connected with the output RP exclusion 1;
the equalizer circuit (5) is composed of an inductor L1, an inductor L2, an inductor L5, an inductor L6, an inductor L7, an inductor L8, an inductor L9, a resistor R5, a resistor R6, a resistor R7, a capacitor C5, a capacitor C11 and a capacitor C12, wherein the resistor R5 is connected with the resistor R6 in series, the resistor R5 is connected with the inductor L5 and the inductor L6, the resistor R6 is connected with the inductor L7 and the inductor L8, the resistor R7 is connected with the capacitor C11 in series, the resistor R7 is connected with a circuit interface formed by connecting the resistor R5 and the resistor R6 in series, the capacitor C11 is connected with a circuit interface formed by connecting the capacitor C12 and the inductor L9 in series, the capacitor C5 is connected with the inductor L2 in series, the capacitor C5 is connected with a circuit interface formed by connecting the resistor R5, the inductor L2 is connected with a circuit interface formed by connecting the resistor R6, and the inductor L1 is connected with the capacitors C5 and L2 in parallel;
the power divider circuit (6) is composed of a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R8, a resistor R9, a resistor R10 and a resistor R11, wherein the resistor R1 is connected with a resistor R2 in parallel, the resistor R3 is connected with a resistor R4 in parallel, the resistor R8 is connected with a resistor R9 in parallel, and the resistor R10 is connected with a resistor R11 in parallel.
2. The signal amplitude conditioning and power dividing module of claim 1, wherein: the 15 pins of the chip U1 are connected with a capacitor C8, and a capacitor C8 is connected with an inductor L5 and an inductor L6.
3. The signal amplitude conditioning and power dividing module of claim 1, wherein: the inductor L8 is connected to a resistor R1 and a resistor R2 connected in parallel, a resistor R3 and a resistor R4 connected in parallel, a resistor R8 and a resistor R9 connected in parallel, and a resistor R10 and a resistor R11 connected in parallel, and then outputs video signals RFout1, RFout2, and RFout 3.
4. The signal amplitude conditioning and power dividing module of claim 1, wherein: the model of the chip U2 is PSA-0012, and the model of the chip U1 is HMC 472A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120752843.2U CN214429520U (en) | 2021-04-14 | 2021-04-14 | Signal amplitude adjusting and power dividing module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120752843.2U CN214429520U (en) | 2021-04-14 | 2021-04-14 | Signal amplitude adjusting and power dividing module |
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| Publication Number | Publication Date |
|---|---|
| CN214429520U true CN214429520U (en) | 2021-10-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120752843.2U Active CN214429520U (en) | 2021-04-14 | 2021-04-14 | Signal amplitude adjusting and power dividing module |
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| CN (1) | CN214429520U (en) |
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- 2021-04-14 CN CN202120752843.2U patent/CN214429520U/en active Active
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