CN214411126U - Thinning device for back of wafer - Google Patents
Thinning device for back of wafer Download PDFInfo
- Publication number
- CN214411126U CN214411126U CN202022055336.1U CN202022055336U CN214411126U CN 214411126 U CN214411126 U CN 214411126U CN 202022055336 U CN202022055336 U CN 202022055336U CN 214411126 U CN214411126 U CN 214411126U
- Authority
- CN
- China
- Prior art keywords
- wafer
- grinding
- polishing
- grinder
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The utility model belongs to the technical field of the electronic technology and specifically relates to a thinization device for wafer back, including wafer gripping device, grinder, finishing device and grinding thick liquids supply system, wafer gripping device is used for fixing to the wafer and maintains wafer protrusion face and accept the grinding, grinder is used for grinding wafer protrusion face, and finishing device is used for carrying out grinder's grinding pad roughness renovation and getting rid of the grinding discarded object to grinder, and grinding thick liquids supply system is used for carrying out the ration to supply grinding thick liquids between grinder and the wafer protrusion face, the utility model provides promote productivity and yield, improve the automation rate and make operation safety and optimization quality, save equipment investment and maintenance cost, reduce the solution of targets such as raw materials consumptive material expense, the adhesiveness of metal level preferred, all have the advantage on product yield and productivity.
Description
The application is as follows: 18/02/2020, application number: 2020201793849, the name of invention creation is: a wafer backside metallization structure and thinning apparatus are disclosed.
Technical Field
The utility model relates to the field of electronic technology, the specific field is a thinization device for the wafer back.
Background
As is well known, the application ranges of insulated Gate Bipolar Transistor (igbt), Power metal oxide semiconductor Field Effect Transistor (MOS) Power MOSFET (Power MOSFET), intelligent Power device (ipd), etc. are increasingly wide, and the wafer needs to be thinned from the aspects of reducing energy loss and optimizing heat dissipation function, and meanwhile, a metallization process is performed on the back of the wafer, so that the thinning process and the back metallization process are related to the performance and yield of the Power semiconductor device.
Currently, in a complementary Metal Oxide semiconductor (cmos) process, a back-end process of wafer processing includes steps of back grinding or etching, surface treatment, cleaning, back metallization, and the like.
In the conventional wafer thinning process, the steps include: directly grinding the back surface of the wafer to reach the target thickness; or polishing the wafer to a first-stage thickness by stages, and etching the wafer with the first-stage thickness by an etching process to reach a target thickness.
In the conventional wafer backside metallization process, one or more metal layers are formed on the backside of the wafer by Evaporation (Evaporation) or sputtering (Sputter), and the metal layers can be used as electrodes, bonding, and heat conducting metal layers, and are tightly connected to the substrate to achieve better heat dissipation and lower resistivity. However, the thinning steps of back grinding, etching, surface treatment, cleaning, etc. before the back metallization process are lengthy and complicated, and the surface treatment effect is not good, which usually affects the back metallization performance of the wafer. For example: peeling off the metal layer, increasing the resistivity, affecting the product yield and the reliability of the semiconductor device, etc.
In addition, the conventional process steps have room for improvement, which is discussed in terms of maximizing productivity, manually changing automation, simplifying equipment maintenance, reducing manufacturing cost, and the like.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a wafer back metallization structure and thinization device to solve among the prior art the lengthy complicated surface treatment effect that also causes of wafer metallization process not good, can influence the problem of the efficiency of wafer back metallization usually.
In order to achieve the above object, the utility model provides a following technical scheme: the wafer back metallization structure comprises a thinned integrated circuit wafer, wherein the thinned integrated circuit wafer is a silicon wafer substrate, an integrated circuit is formed on the upper surface of the silicon wafer substrate, the thinned wafer back is the lower surface of the silicon wafer substrate, a protective adhesive layer is arranged on the upper surface of the silicon wafer substrate and above the integrated circuit, and a metal seed layer, a metal thin film layer and an ion implantation protective layer are sequentially arranged on the wafer back downwards.
Preferably, the silicon wafer substrate is made of silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), indium phosphide (InP), gallium nitride (GaN), and gallium oxide (Ga)2O3) One or more of the above components.
Preferably, the ion implantation protective layer is made of silicon dioxide.
In order to achieve the above object, the utility model provides a following technical scheme: a thinning device for the back surface of a wafer comprises a wafer holding device, a grinding device, a finishing device and a grinding slurry supply system, wherein the wafer holding device is used for fixing the wafer and maintaining the convex surface of the wafer to be ground, the grinding device is used for grinding the convex surface of the wafer, the finishing device is used for carrying out roughness finishing on a grinding pad of the grinding device and removing grinding waste on the grinding device, and the grinding slurry supply system is used for quantitatively supplying grinding slurry between the grinding device and the convex surface of the wafer.
Preferably, the wafer holding device comprises a wafer holder and a wafer holding ring arranged on the wafer holder, and the wafer to be thinned is fixed on the wafer holding ring.
Preferably, the grinding device comprises a grinding base and a grinding pad, the grinding pad is mounted on the grinding base, and a grinding surface of the grinding pad is matched with the wafer holding ring.
Preferably, the dressing device is an abrasive pad dresser, and a dressing head of the abrasive pad dresser is disposed toward an abrasive surface of the abrasive pad.
Compared with the prior art, the beneficial effects of the utility model are that: the manufacturing process method is based on the method that the wafer thinning is carried out by chemical mechanical polishing, the metallization is carried out by electroless plating, the precise and strict requirements of the wafer thinning and the wafer back metallization are met, and the yield is improved, so that the losses of resistivity, switch, energy and the like are reduced, and the heat dissipation function is optimized;
the wafer back thinning process is carried out by mechanical chemical grinding, and the wafer back metallization process method is carried out by chemical electroless plating, so that the method has the solution scheme for realizing the aims of simplifying the process steps, improving the productivity and yield, improving the automation rate, ensuring the operation safety and optimizing the quality, saving the equipment investment and maintenance cost, reducing the material consumption cost, improving the adhesion of a metal layer and the like, and has advantages in the yield and the productivity of products.
Drawings
Fig. 1 is a block diagram illustrating a wafer backside thinning and metallization process according to the present invention;
fig. 2 is a schematic structural diagram of an insulated gate bipolar transistor according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a thinned layer structure of an insulated gate bipolar transistor according to an embodiment of the present invention;
FIG. 4 is a schematic view of an exemplary chemical mechanical polishing apparatus for back thinning;
FIG. 5 is a schematic diagram of an exemplary backside thinning and metallization process;
fig. 6 is a schematic diagram of a structure for performing backside thinning and metallization in an embodiment.
In the figure: 101. an integrated circuit; 102. a silicon wafer substrate; 103. a wafer surface protection glue layer; 121. a metal seed layer; 122. a metal thin film layer; 123. ion implantation into the protective layer;
131. a wafer holding device; 132. a stainless steel wafer grip ring;
141. grinding the base; 142. a polyurethane polishing pad;
151. a polishing pad dresser device; 152. an epoxy diamond dresser;
161. slurry of the grinding fluid; 162. a slurry drop tube;
163. the slurry is in the gap between the wafer and the polishing pad.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In this embodiment, taking a silicon wafer as an example for manufacturing a power device, after the front side of the wafer is completed with a power device circuit and an electrode, a thinning process is performed on the back side of the wafer. Generally, the wafer will be deformed and warped in the thinning process, and the warping degree is larger when the thickness of the wafer is reduced; the wafer is broken, and the thinner the thickness of the wafer, the higher the probability of breaking.
In the power device manufacturing step, after the back surface of the wafer is thinned to a predetermined thickness, when a step of forming a back metal layer or Bump Metallization (Under Bump Metallization) on the back surface of the wafer is required, the wafer is easily warped; if a Back Grinding (Back Grinding) or a Back Metallization (Back Metallization) step is required after bump Metallization is formed, a heating process is required in the process, so that a nickel film for bump Metallization is crystallized to cause warpage of the wafer, and the warpage is greater than that in the step of forming the Back Metallization or the bump Metallization after the Back Grinding.
The manufacturing method of the power device in the embodiment of the present invention is to use the process of electroless plating metal film layer or electroless plating bump metallization to avoid the wafer warpage generated during the process of back metal layer and bump metallization. In order to prevent the wafer from warping or breaking caused by the electroless plating process and facilitate operation, a glass substrate is adhered on the back of the wafer to serve as a protective layer after the back metal film process, and the glass substrate is peeled off after the bump metallization process is completed; meanwhile, if the requirement of the embodiment is met, the glass substrate can also be used as a barrier layer in the step of carrying out high-energy ion implantation process in the wafer manufacturing, and the protective layer is stripped after the ion implantation process is finished.
As shown in fig. 1, the process of thinning and metalizing the back surface of the wafer of the present invention includes the steps of (1) and (7) sequentially from (2) to (6):
(1) s1 the previous step is to form circuits, wires, devices, etc. on the front surface of the wafer and to apply adhesive for protection
(2) S2-S5 steps of performing a full or partial CMP and thinning process on the back side of the wafer
(3) S6 metallization or metal layer formation on the back of wafer
(4) S7 step of forming a passivation layer or barrier layer on the back side of the wafer
(5) S7 high energy ion implantation on the back of wafer
(6) S7 peeling the passivation or barrier layer on the back surface of the wafer
(7) And step S8, cutting chips, devices and the like on the wafer or directly packaging the wafer by using a wafer level packaging technology, and testing.
The detailed process in the examples is as follows:
as shown in fig. 5, the utility model provides a technical solution: the wafer back metallization structure comprises a thinned integrated circuit wafer, wherein the thinned integrated circuit wafer is a silicon wafer substrate, an integrated circuit is formed on the upper surface of the silicon wafer substrate, the thinned wafer back is the lower surface of the silicon wafer substrate, a protective adhesive layer is arranged on the upper surface of the silicon wafer substrate and above the integrated circuit, and a metal seed layer, a metal thin film layer and an ion implantation protective layer are sequentially arranged on the wafer back downwards.
The silicon wafer substrate is made of silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), indium phosphide (InP), gallium nitride (GaN) and gallium oxide (Ga)2O3) The wafer has a diameter size of 4 inches to 12 inches, but not limited thereto, in this embodiment, a 8-inch silicon wafer is used as the substrate 102, and the metal layer or electrode is preferably aluminum or copper. The steps of forming the internal circuit structures and the metal layers, dielectric layers or electrodes on the wafer surface 101 are conventional wafer processing steps for manufacturing power devices, and are performed using processing equipment, such as photolithography, etching, diffusion, ion implantation, sputtering, thin film deposition, and other conventional methods. After the front surface 101 of the wafer is formed with electrodes such as circuits, wires, devices, etc., the surface of the wafer is attached with a protective tape 103 or a glass substrate as a better protective layer, and the preceding steps are completed.
The ion implantation protective layer is made of silicon dioxide.
Step of Back Grinding process for wafer
A thinning device for the back surface of a wafer comprises a wafer holding device, a grinding device, a finishing device and a grinding slurry supply system, wherein the wafer holding device is used for fixing the wafer and maintaining the convex surface of the wafer to be ground, the grinding device is used for grinding the convex surface of the wafer, the finishing device is used for carrying out roughness finishing on a grinding pad of the grinding device and removing grinding waste on the grinding device, and the grinding slurry supply system is used for quantitatively supplying grinding slurry between the grinding device and the convex surface of the wafer.
The wafer holding device comprises a wafer holder and a wafer holding ring arranged on the wafer holder, wherein a wafer needing thinning is fixed on the wafer holding ring, the wafer holder is made of stainless steel coating, and the specification is as follows: leveling and maintaining the wafer height to be 100-200 micrometers (um); depending on the actual requirements, the description is not limited to this.
Grinder includes grinding base and grinding pad, and the grinding pad is installed on grinding base, and the abrasive surface and the cooperation of wafer grip ring of grinding pad set up, and the material of grinding pad is Polyurethane (Polyurethane), its specification: adding cerium oxide, silica gel, a foaming aperture of 20-40 micrometers (um), a thickness of 8-10 millimeters (mm) and a medium-hardness value; depending on the actual requirements, the description is not limited to this.
The truing device is a grinding pad truing device, a truing head of the grinding pad truing device is arranged towards a grinding surface of the grinding pad, the material of the grinding pad truing device is Epoxy Resin glue (Epoxy Resin Adhesive) molded diamond disc, the grinding pad truing device has high-efficiency truing capability, and the specification is as follows: 11.8 millimeters (mm) in diameter, 7.7 millimeters (mm) in thickness, 3000 ± 300 angstroms (a) in removal rate, 0.12 millimeters (mm) in pad wear rate per hour; depending on the actual requirements, the description is not limited to this.
The chemical polishing liquid device comprises a polishing liquid conveying circulating system, a polishing liquid drop leakage head and the like, wherein the specification of polishing liquid slurry is as follows: acidic solution, aluminum oxide (Al)2O3) Hydrofluoric acid-containing etching slurry special for the particles or the silicon substrate; depending on the actual requirements, the description is not limited to this.
The motor and transmission control device comprises a motor, a positioning and rotating speed controller, a power supply and the like, and the specification is as follows: 220V Alternating Current (AC) -3 Horsepower (HP), 25% -100% of a frequency converter, 90-180 Revolutions Per Minute (RPM) of a rotating speed device, a laser detection bottoming controller and the like; depending on the actual requirements, it is not limited to this description.
The thinning device also comprises a cleaning device, and the cleaning device comprises an ultrapure water cleaning tank, an ultrasonic cleaning tank, a drying device and the like; the content is not limited to the description content according to the actual requirement;
the material of ultrapure water washing tank is polypropylene (PP), its specification: a volume of 250 liters, using ultrapure water having a resistance value of 18.2 million ohm-centimeters (M Ω -cm) and less than 1 particle of 0.5 micrometer (um); the content is not limited to the description content according to the actual requirement;
the material of ultrasonic cleaning groove is stainless steel (SS316), and its specification: 250 liters in volume, 28 kilohertz (KHz), and room temperature to 90 degrees (DEG C) temperature control; the content is not limited to the description content according to the actual requirement;
the ultrasonic cleaning tank is made of polypropylene (PP) and has the specification: 250 liters in volume, 28 kilohertz (KHz), and room temperature to 90 degrees (DEG C) temperature control; the content is not limited to the description content according to the actual requirement;
drying device includes nitrogen gas, clean air and heating mechanism, and its specification: the air flow speed is 2.0 m/s, and the temperature is controlled between room temperature and 150 ℃ (DEG C); the content is not limited to the description content according to the actual requirement;
the above-mentioned devices and materials are determined by actual requirements and are not limited to the descriptions.
The utility model carries out the grinding process of the back of the wafer after the preorder step, the grinding process of the crystal back grinds the crystal back to reduce the thickness through the chemical mechanical grinding process, and the chemical mechanical grinding process can carry out the thinning treatment of the crystal back in a whole or partial way; the polishing head wafer holder 131 and the wafer retaining ring 132 are fixed wafers, and the retaining protrusion surface is polished and rotated by itself to perform the thinning process; the polishing table 141 and the polyurethane polishing pad 142 are used for fixing the polyurethane polishing pad 142 and keeping the slurry interface between the wafer and the polishing pad 163 for wafer polishing and thinning, and the thinning process is performed by the interaction of self-rotation and wafer rotation; the polishing pad dressing head 151 and diamond dressing device 152 are fixed diamond dressing devices and are rotated by self to interact with the polishing pad, so as to dress the roughness of the polishing pad and remove the polishing waste; the polishing slurry 161 is supplied by a polishing slurry supply line 162, and quantitatively supplies the required polishing slurry. The chemical mechanical polishing apparatus comprises a polyurethane polishing pad 142, a polishing pad dresser 152, a chemical polishing liquid 161 device, a wafer holder 131, a motor and transmission control device, and a wafer cleaning device; depending on the actual requirements, the description is not limited to this.
Step of forming metal layer or Metallization (Back Metallization) process on the Back surface of wafer
A method for manufacturing a wafer backside metallization structure comprises the steps of:
(1) carrying out protective glue layer arrangement on the surface of the wafer on the side provided with the integrated circuit;
(2) fixing the wafer protected by the adhesive on a wafer holder, wherein the back surface of the wafer is arranged in a protruding manner;
(3) thinning and grinding the back of the wafer by a grinding device;
(4) forming a metal layer on the thinned wafer surface;
(5) forming a protective layer on the back of the wafer on which the metal layer is formed;
(6) carrying out high-energy ion implantation on the back of the wafer;
(7) stripping the protective layer on the back of the wafer;
(8) and cutting chips and devices on the metallized wafer or directly packaging the metallized wafer by using a wafer level packaging technology, and performing a testing step.
According to the step (3), the specific process comprises:
(1) fixing the wafer through the wafer holding ring, wherein the back surface of the wafer protrudes towards the grinding pad;
(2) the wafer holder is rotated to drive the wafer holder to rotate, and the back of the wafer is contacted with the grinding pad;
(3) a polishing slurry supply system for supplying polishing slurry to the surface of the polishing pad;
(4) the grinding base spins to drive the grinding pad to rotate, so that the grinding pad and the back of the wafer are thinned alternately;
(5) during the wafer thinning process, the polishing pad dresser rotates to dress the surface of the polishing pad, so that the roughness of the polishing pad is dressed and the polishing waste is removed.
According to the step (4), the specific process is as follows: forming a metal seed layer on the back of the wafer by chemical vapor deposition, evaporation, sputtering, chemical plating or other suitable plating methods, and then forming a metal film layer on the back of the wafer by chemical electroless plating.
According to step (5), the ion implantation process first covers a protective layer or barrier layer 123 on the metal layer, and covers a protective layer or barrier layer 123 on the metal layer with silicon dioxide or other materials, wherein silicon dioxide is the most preferred scheme, i.e. any kind of glass can be used, such as soda-lime glass, alkali-free glass, quartz glass, borosilicate glass, etc.; the thickness of the glass substrate is 1.0mm as long as it can support the strength of the wafer substrate and prevent warpage, and the wafer and the glass substrate are preferably bonded with a double-sided tape, and the adhesive used for the double-sided tape is preferably acrylic, silicone, polyester, polyurethane, polyamide, methacrylic, ethylene and vinyl acetate polymer resin, and is preferably hardened by ultraviolet rays and is preferably an acrylic adhesive which is easily peeled off.
According to the step (6), the specific process is as follows: the p + or n + layer (p-n junction) is formed by implanting the above-mentioned doped ions into the back surface of the wafer with boron, phosphorus, arsenic or other materials, and entering the substrate, and low current, medium current, high current or low energy, high energy, etc. can be adopted, and the embodiment is implanted with high energy ions, and the specification is as follows: the implantation depth is 2200 nanometers (nm), the energy intensity is 2 million electron volts (MeV), and the ion concentration is 1.E +12 is the preferred scheme.
According to the step (7), the protective layer is stripped from the back of the wafer by ultraviolet light (UV), and the protective layer or the barrier layer is stripped from the back of the wafer by using a stripping device with developed mature technology; if Ultraviolet (UV) or Thermal (Thermal) curing or other adhesives are used, the adhesive strength can be reduced by using the same UV or Thermal or other adhesives, and the protective layer or barrier layer attached to the wafer can be easily peeled off completely. In this embodiment, the wafer and the glass substrate are preferably bonded by a double-sided tape, and the adhesive used in the double-sided tape may be acrylic, silicone, polyester, polyurethane, polyamide, methacrylic, ethylene and vinyl acetate polymer resin, and is preferably hardened by ultraviolet light, and is preferably an acrylic adhesive which is easily peeled, and the ultraviolet light peeling is most preferably used. Depending on the actual requirements, the description is not limited to this.
The utility model discloses carry out wafer back metallization or form metal level 122 processing procedure after the back of a wafer grinding step, back of a wafer metal level 122 or metallization carry out metal seed layer 121 and metallization processing procedure through electroless plating membrane processing procedure. The metal seed layer 121 is preferably formed by a nickel-silicon compound layer or a titanium layer; the metal seed layer 121 can be formed by any suitable metal plating method such as evaporation, sputtering, or chemical plating, and the like, preferably by electroless plating; the metal seed layer 121 may be a single layer or a plurality of layers, and includes at least one of the following conductive materials: titanium (Ti), nickel (Ni), copper (Cu), palladium (Pd), gold (Au), chromium (Cr), silver (Ag), carbon (C), tin (Sn), or the like. Then, a metal layer 122 is formed on the seed layer, wherein the metal layer may be a single layer or a plurality of layers, and includes at least one of the following metal layers: titanium (Ti), nickel (Ni), copper (Cu), palladium (Pd), gold (Au), chromium (Cr), silver (Ag), tin (Sn), or the like, and is preferably used in the electroless plating process. The thickness of the nickel silicide layer is preferably 150-200 nm, the thickness of the titanium layer is preferably 100-500 nm, and the thickness of the metal layer is preferably 100-1000 nm.
By the technical solution, the formation of the metal seed layer 121 and the metal layer 122 in this embodiment is preferably performed by an electroless plating process; the metal seed layer may be formed of titanium/copper (Ti/Cu), titanium/nickel (Ti/Ni), titanium/chromium (Ti/Cr), chromium/copper (Cr/Cu), chromium/nickel (Cr/Ni), chromium/silver (Cr/Ag), chromium/gold (Cr/Au), titanium/silver (Ti/Ag), or titanium/gold (Ti/Au), and a single layer or a plurality of metal layers of a conductive material is preferably used; the metal layer may be made of gold (Au), silver (Ag), copper/gold (Cu/Au), copper/silver (Cu/Ag), nickel/gold (Ni/Au), nickel/silver (Ni/Ag), nickel/palladium/gold (Ni/Pd/Au), or copper/nickel/gold (Cu/Ni/Au), and a single-layer or multi-layer metal layer having a low conductivity is preferably used; the thickness of the metal seed layer is preferably 200nm and the thickness of the metal layer is preferably 400 nm.
Before the electroless plating process, the wafer is cleaned, preferably by a soaking and cleaning method; among them, ultra-pure water cleaning, ultrasonic cleaning, soaking in alkaline or acidic solution for degreasing, soaking in surfactant solution, soaking in buffered etching solution, etc. are preferred treatment schemes.
In the electroless plating process, after the cleaning and purification, a metal compound having catalytic activity is preferably deposited on the back surface of the wafer from the electroless plating solution. The metal compound is a palladium compound, a zinc compound or the like. The palladium compound may be palladium chloride, hydroxide, sulfate, ammonium salt, etc. which can exhibit a catalytic effect, and the palladium compound may be an organic solvent solution, for example, methanol, ethanol, isopropanol, acetone, methyl ethyl ketone, toluene, ethylene glycol, polyethylene glycol, dimethyl diamide, dimethyl sulfoxide, or a mixture thereof. In the palladium compound of the present embodiment, after the metal compound is treated, 24 wafers in a whole batch are immersed in an electroless plating solution to perform an electroless plating treatment; the metal ion source in the electroless plating solution includes chloride or sulfuric acid compound, and the electroless plating solution may contain a reducing agent such as formaldehyde, sodium hypophosphite, sodium borohydride, glyoxylic acid, and the like, and may contain a complexing agent such as sodium acetate, malic acid, citric acid, glycine, and the like. In the electroless plating solution, although sodium hydroxide or potassium hydroxide, which are generally used, can be used as the pH adjuster, tetramethylammonium hydroxide is preferably used in the present embodiment in order to avoid contamination by alkali metal ions such as sodium and potassium in the conventional integrated circuit manufacturing.
The above-mentioned devices and materials are determined by actual requirements and are not limited to the descriptions.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. A thinning apparatus for a back surface of a wafer, comprising: the polishing device comprises a wafer holding device, a polishing device, a finishing device and a polishing slurry supply system, wherein the wafer holding device is used for fixing a wafer and maintaining the convex surface of the wafer to be ground, the polishing device is used for polishing the convex surface of the wafer, the finishing device is used for performing roughness finishing on a polishing pad of the polishing device and removing polishing wastes, and the polishing slurry supply system is used for quantitatively supplying polishing slurry between the polishing device and the convex surface of the wafer.
2. A thinning apparatus for a back surface of a wafer according to claim 1, wherein: the wafer holding device comprises a wafer holder and a wafer holding ring arranged on the wafer holder, wherein a wafer needing to be thinned is fixed on the wafer holding ring.
3. A thinning apparatus for a back surface of a wafer according to claim 1, wherein: the grinding device comprises a grinding base and a grinding pad, wherein the grinding pad is arranged on the grinding base, and the grinding surface of the grinding pad is matched with the wafer holding ring.
4. A thinning apparatus for a back surface of a wafer according to claim 1, wherein: the dressing device is a polishing pad dresser, and a dressing head of the polishing pad dresser is arranged towards the polishing surface of the polishing pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022055336.1U CN214411126U (en) | 2020-02-18 | 2020-02-18 | Thinning device for back of wafer |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022055336.1U CN214411126U (en) | 2020-02-18 | 2020-02-18 | Thinning device for back of wafer |
| CN202020179384.9U CN212062396U (en) | 2020-02-18 | 2020-02-18 | Metallization structure of wafer back |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020179384.9U Division CN212062396U (en) | 2020-02-18 | 2020-02-18 | Metallization structure of wafer back |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214411126U true CN214411126U (en) | 2021-10-15 |
Family
ID=73538923
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020179384.9U Active CN212062396U (en) | 2020-02-18 | 2020-02-18 | Metallization structure of wafer back |
| CN202022055336.1U Active CN214411126U (en) | 2020-02-18 | 2020-02-18 | Thinning device for back of wafer |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020179384.9U Active CN212062396U (en) | 2020-02-18 | 2020-02-18 | Metallization structure of wafer back |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN212062396U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111403314A (en) * | 2020-02-18 | 2020-07-10 | 北京芯之路企业管理中心(有限合伙) | Wafer back metallization structure, thinning device and metallization processing method |
-
2020
- 2020-02-18 CN CN202020179384.9U patent/CN212062396U/en active Active
- 2020-02-18 CN CN202022055336.1U patent/CN214411126U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111403314A (en) * | 2020-02-18 | 2020-07-10 | 北京芯之路企业管理中心(有限合伙) | Wafer back metallization structure, thinning device and metallization processing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN212062396U (en) | 2020-12-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111403314A (en) | Wafer back metallization structure, thinning device and metallization processing method | |
| CN104742007A (en) | Chemical mechanical grinding device and chemical mechanical grinding method | |
| CN106378671B (en) | A kind of reduction process of large-sized CdS single-chips | |
| CN103367552B (en) | A kind of manufacture method of light emitting semiconductor device | |
| WO2003065431A1 (en) | Method of spin etching wafers with an alkali solution | |
| TW201933438A (en) | Wafer producing method and wafer producing apparatus | |
| CN102403434B (en) | Method for manufacturing vertical LED chip | |
| CN214411126U (en) | Thinning device for back of wafer | |
| WO2007060837A1 (en) | Method of manufacturing semiconductor device | |
| CN111710648A (en) | Ultra-thin wafer back and double-side processing technology for bonded glass carrier plate | |
| CN108899268B (en) | Pretreatment method for improving bubble performance of wafer bonding process | |
| CN102814725B (en) | A kind of chemical and mechanical grinding method | |
| JP2003297786A (en) | Method for manufacturing semiconductor device | |
| CN113903656A (en) | Silicon carbide wafer processing technology | |
| TWI538034B (en) | Method for producing power device | |
| CN115938927B (en) | Ultrathin wafer thinning process | |
| WO2000067305A1 (en) | Wafer polishing method and cleaning method, and protection film | |
| CN111446151A (en) | Method for transferring crystal grains to blue film in batches after crystal grains are cut | |
| TW200525620A (en) | Method for processingSOI substrate | |
| CN101599452B (en) | Method for corroding edges of substrate with insulating buried layer | |
| CN114131434A (en) | Thinning and polishing method of indium phosphide | |
| CN112635322A (en) | Preparation method for improving heat dissipation of indium phosphide heterojunction bipolar transistor | |
| CN110783178B (en) | Semiconductor wafer and processing method thereof | |
| JPH07130685A (en) | Method of manufacturing semiconductor wafer | |
| CN116092929A (en) | Double-sided wafer chemical plating process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |