CN214384757U - Semiconductor element and packaging structure of semiconductor element - Google Patents
Semiconductor element and packaging structure of semiconductor element Download PDFInfo
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- CN214384757U CN214384757U CN202022305885.XU CN202022305885U CN214384757U CN 214384757 U CN214384757 U CN 214384757U CN 202022305885 U CN202022305885 U CN 202022305885U CN 214384757 U CN214384757 U CN 214384757U
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Abstract
The utility model discloses a semiconductor component and semiconductor component's packaging structure. The semiconductor element includes a first semiconductor layer and an insulating layer. The first semiconductor layer has a first surface. The insulating layer directly contacts a portion of the first surface and has a first sidewall and a second sidewall. The first side wall is inclined relative to the first surface by a first angle theta 1, the second side wall is inclined relative to the first surface by a second angle theta 2, the first angle theta 1 is different from the second angle theta 2, and the first angle theta 1 and the second angle theta 2 are not equal to 90 degrees.
Description
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor Light emitting device, such as a Light Emitting Diode (LED).
Background
The applications of semiconductor devices are very wide, and the development and research of related materials are continuously carried out. For example, III-V semiconductor materials containing group III and group V elements can be used in various optoelectronic semiconductor devices such as light emitting diodes (leds), Laser Diodes (LDs), photodetectors, Solar cells (Solar cells), etc., or can be power devices such as switches or rectifiers, and can be applied in the fields of illumination, medical treatment, display, communication, sensing, power systems, etc. A light emitting diode, which is one of semiconductor light emitting elements, has advantages of low power consumption, fast reaction speed, small size, long operating life, and the like, and thus is widely used in various fields.
SUMMERY OF THE UTILITY MODEL
An object of the present invention is to provide a semiconductor device and a package structure of the semiconductor device, which can improve the photoelectric characteristics such as light extraction efficiency, the production efficiency and the stability.
To achieve the above objective, the present invention provides a semiconductor device including a first semiconductor layer and an insulating layer. The first semiconductor layer has a first surface having a first portion. The insulating layer directly contacts the first portion and has a first sidewall and a second sidewall. The first side wall is inclined relative to the first surface by a first angle theta 1, the second side wall is inclined relative to the first surface by a second angle theta 2, the first angle theta 1 is different from the second angle theta 2, and the first angle theta 1 and the second angle theta 2 are not equal to 90 degrees.
According to an embodiment, the semiconductor device further includes a light emitting stack having a second surface, and the first semiconductor layer and the insulating layer are disposed on the second surface.
According to an embodiment, the insulating layer directly contacts the second surface.
According to an embodiment, the first semiconductor layer has a third sidewall and a fourth sidewall, and the insulating layer is continuously distributed on a portion of the second surface, a portion of the first surface, the third sidewall and the fourth sidewall.
According to an embodiment, the first semiconductor layer has a third sidewall and a fourth sidewall, and a third angle θ 3 between the third sidewall and the light emitting stack is greater than 90 °, and a fourth angle θ 4 between the fourth sidewall and the light emitting stack is greater than 90 °.
According to an embodiment, the third sidewall and the fourth sidewall are completely covered by an insulating layer.
According to an embodiment, the first angle θ 1 is greater than the second angle θ 2.
According to an embodiment, the first angle θ 1 is smaller than 90 ° and the second angle θ 2 is smaller than 90 °.
According to an embodiment, the first angle θ 1 is greater than 90 ° and the second angle θ 2 is less than 90 °.
According to an embodiment, the first angle θ 1 is greater than 90 ° and the second angle θ 2 is greater than 90 °.
According to an embodiment, the first angle θ 1 is smaller than the second angle θ 2.
According to an embodiment, the first angle θ 1 is smaller than 90 ° and the second angle θ 2 is larger than 90 °.
According to an embodiment, the first angle θ 1 is smaller than 90 ° and the second angle θ 2 is smaller than 90 °.
According to an embodiment, the first angle θ 1 is greater than 90 ° and the second angle θ 2 is greater than 90 °.
According to an embodiment, the insulating layer further has a third surface and a fourth surface, the first sidewall extends between the first surface and the third surface, and the first angle θ 1 is greater than 90 °.
According to an embodiment, the first semiconductor layer comprises a binary III-V semiconductor material.
According to an embodiment, the semiconductor device further includes a first electrode on the light emitting stack layer, and the first electrode and the first semiconductor layer do not overlap in a vertical direction.
According to one embodiment, the first electrode includes an electrode pad and a plurality of extension electrodes connected to the electrode pad.
According to an embodiment, the insulating layer and the electrode pad do not overlap in the vertical direction.
According to an embodiment, the first semiconductor layer has an inverted trapezoid cross section.
According to an embodiment, the semiconductor device further includes a second semiconductor layer between the first semiconductor layer or the insulating layer and the light emitting stack.
According to an embodiment, the second semiconductor layer includes a first portion and a second portion separated from each other, and the second portion has a stepped structure.
According to an embodiment, the light emitting stack includes a first semiconductor structure having a roughened structure.
According to an embodiment, the semiconductor device further includes a conductive layer directly contacting the first semiconductor layer and the insulating layer.
According to an embodiment, the semiconductor device further includes a second semiconductor layer disposed between the first semiconductor layer or the insulating layer and the light emitting stack, and a portion of the second semiconductor layer is in direct contact with the conductive layer.
The present invention also provides a semiconductor device package structure, which comprises a carrier and a semiconductor device as above, wherein the semiconductor device is located on the carrier.
The utility model has the advantages of, the packaging structure of a semiconductor component and semiconductor component that provides, its structural design helps improving like photoelectric characteristic such as light extraction efficiency, also can obtain improving in the aspect of production efficiency and stability. The utility model discloses a semiconductor element or semiconductor package structure can be applied to the product in fields such as illumination, medical treatment, demonstration, communication, sensing, electrical power generating system, for example lamps and lanterns, monitor, cell-phone, panel computer, automobile-used instrument board, TV, computer, dress device (like wrist-watch, bracelet, necklace etc.), traffic sign, outdoor display, medical equipment etc..
Drawings
Fig. 1 is a schematic cross-sectional view and a partial enlarged view of a semiconductor device according to an embodiment of the present invention;
fig. 2A to fig. 2C are schematic partial cross-sectional views of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a schematic structural view of a semiconductor device according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Fig. 7 is a schematic view of a package structure of a semiconductor device according to an embodiment of the present invention.
Description of the symbols
10. 20, 20', 20 ", 60: semiconductor device with a plurality of semiconductor chips
100: light emitting laminate
100 a: first semiconductor structure
100 b: second semiconductor structure
100 c: active structure
101: contact structure
102: first semiconductor layer
104: insulating layer
104 a: first region
104 b: second region
106: a first electrode
108: conductive layer
110: reflective layer
112: bonding layer
114: substrate
116: second electrode
118: a second semiconductor layer
118 a: the first part
118 b: the second part
600: packaging structure
61: package substrate
62: through hole
63: carrier
65: bonding wire
66: conductive structure
66 a: first contact pad
66 b: second contact pad
68: encapsulation layer
θ 1, θ 2, θ 3, θ 4: angle of rotation
A. B, R1, R2: region(s)
R: coarsening structure
S: stepped structure
s1, s2, s3, s4, s 5: surface of
w1, w2, w3, w 4: side wall
Detailed Description
In order to make the description of the present invention more detailed and complete, the present invention will be described in detail below with reference to the accompanying drawings, and it should be noted that the following embodiments are shown for illustrating the semiconductor device of the present invention, and the present invention is not limited to the following embodiments. In the drawings or the description, similar or identical members will be described using similar or identical reference numerals, and the shapes or sizes of the respective elements in the drawings are merely illustrative and not limited thereto if not particularly described. It is to be noted that elements not shown or described in the drawings may be of a type known to those skilled in the art. Moreover, unless specifically stated otherwise, a similar description of a "first layer (or structure) on a second layer (or structure)" may include embodiments in which the first layer (or structure) is in direct contact with the second layer (or structure), and may also include embodiments in which the first layer (or structure) and the second layer (or structure) have other structures therebetween that are not in direct contact with each other. In addition, it is to be understood that the upper and lower positional relationship of the layers (or structures), etc. may be changed as viewed from different orientations.
Fig. 1 is a schematic cross-sectional view of a semiconductor device 10 according to an embodiment of the present invention and an enlarged partial view of a region a and a region B therein. The semiconductor device 10 of the present embodiment includes a light emitting stack 100, a contact structure 101, an insulating layer 104, a first electrode 106, a conductive layer 108, a reflective layer 110, a bonding layer 112, a substrate 114, and a second electrode 116.
The substrate 114 may include a conductive material, such as Gallium Arsenide (GaAs), Indium Phosphide (InP), Silicon carbide (SiC), Gallium Phosphide (GaP), zinc oxide (ZnO), Gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge), Silicon (Si), or the like. In this embodiment, the base 114 is a support substrate that is bonded to the epitaxial structure after removal of the epitaxially grown substrate. In one embodiment, the base 114 may be an epitaxial growth substrate, and the semiconductor device 10 does not have the bonding layer 112 and/or the conductive layer 108.
The light emitting stack 100 is disposed on a substrate 114 and includes a first semiconductor structure 100a, a second semiconductor structure 100b, and an active structure 100 c. The second semiconductor structure 100b is located on the first semiconductor structure 100 a. The active structure 100c is located between the first semiconductor structure 100a and the second semiconductor structure 100 b. When the semiconductor device 10 is a light emitting device, such as a light emitting diode or a laser diode, the light emitting stack 100 emits a light during operation. The first semiconductor structure 100a and the second semiconductor structure 100b may have opposite conductivity types to provide electrons and holes, respectively. The first semiconductor structure 100a and the second semiconductor structure 100b may respectively include a single layer or multiple layers. In one embodiment, the first semiconductor structure 100a is n-type and the second semiconductor structure 100b is p-type. In one embodiment, the first semiconductor structure 100a is p-type and the second semiconductor structure 100b is n-type. The first semiconductor structure 100a, the second semiconductor structure 100b, and the active structure 100c may comprise the same series of binary, ternary, or quaternary III-V semiconductor materials, such as the AlInGaAs series, AlGaInP series, AlInGaN series, or InGaAsP series. Wherein the AlInGaAs series can be expressed as (Al)x1In(1-x1))1-x2Gax2As; the AlInGaP series can be expressed as (Al)y1In(1-y1))1-y2Gay2P, AlInGaN series can be expressed as (Al)z1In(1-z1))1-z2Gaz2N; the InGaAsP series can be expressed as Inz3Ga1-z3Asz4P1-z4(ii) a Wherein x1, y1, z1, x2, y2, z2, z3 and z4 are not more than 0 and not more than 1.
The contact structure 101 is located under the light emitting stack 100 and includes a first semiconductor layer 102. In the present embodiment, the contact structure 101 includes a plurality of first semiconductor layers 102. For convenience of description, the relative relationship between the components will be described below by taking the first semiconductor layer 102 as an example. As shown in fig. 1, the insulating layer 104 is located between the light emitting stack 100 and the conductive layer 108, and is in direct contact with a portion of the first semiconductor layer 102. As shown in fig. 1, the first semiconductor layer 102 has a first surface s1 and a second surface s2, and the first surface s1 is farther from the light emitting stack 100 than the second surface s 2. The insulating layer 104 is located under the first semiconductor layer 102 and formed on a portion of the first surface s 1. The insulating layer 104 has a first sidewall w1, a second sidewall w2, a third surface s3 and a fourth surface s 4. In the present embodiment, the first sidewall w1 extends between the first surface s1 and the third surface s3, and the second sidewall w2 extends between the third surface s3 and the fourth surface s 4. In a height direction (or vertical direction), the first surface s1 is located between the third surface s3 and the fourth surface s 4. The first sidewall w1 is inclined at a first angle θ 1 with respect to the first surface s1, and the second sidewall w2 is inclined at a second angle θ 2 with respect to the first surface s 1. Specifically, as shown in fig. 1, the first angle θ 1 may correspond to an included angle between the first sidewall w1 and the first surface s1, and the second angle θ 2 may correspond to an included angle between the second sidewall w2 and an imaginary extension line of the first surface s 1. The first angle theta 1 is different from the second angle theta 2, and the first angle theta 1 and the second angle theta 2 are not equal to 90 degrees. In the present embodiment, the first angle θ 1 is greater than the second angle θ 2, and the first angle θ 1 is greater than 90 ° and the second angle θ 2 is greater than 90 °. Thus, when the conductive layer 108 is formed on the surface of the insulating layer 104, the conductive layer 108 can easily conform to the contour of the insulating layer 104. In the present embodiment, as shown in the enlarged partial view of the region a in fig. 1, the cross-sectional profile of the insulating layer 104 presents a polygon, and the polygon can be divided into a first region 104a and a second region 104b by the imaginary extension line of the first surface s 1. In the present embodiment, the second region 104b has an inverted trapezoid shape.
The first semiconductor layer 102 has a third sidewall w3 and a fourth sidewall w 4. The light emitting stack 100 has a fifth surface s 5. As shown in fig. 1, the cross section of the first semiconductor layer 102 is an inverted trapezoid. The second surface s2 of the first semiconductor layer 102 is connected to the fifth surface s5 of the light emitting stack 100, and the third sidewall w3 and the fourth sidewall w4 (i.e., the inverted trapezoid waist) extend between the first surface s1 and the second surface s 2. In this embodiment, the third sidewall w3 and the fourth sidewall w4 are completely covered by the insulating layer 104. The third sidewall w3 has a third angle θ 3 with the second surface s2 of the first semiconductor layer 102, and the fourth sidewall w4 has a fourth angle θ 4 with the second surface s2 of the first semiconductor layer 102. In this embodiment, the third angle θ 3 is greater than 90 ° and the fourth angle θ 4 is greater than 90 °. In one embodiment, the third angle θ 3 and/or the fourth angle θ 4 may be less than or equal to 90 °. In some embodiments, when the third angle θ 3 is greater than 90 ° and the fourth angle θ 4 is greater than 90 °, the insulating layer 104 can more easily conform to the contour of the first semiconductor layer 102.
The method for forming the first semiconductor layer 102 and the insulating layer 104 of the above type includes the following steps: the first semiconductor layer 102 is formed on the fifth surface s5 of the light emitting stack 100, and then one or more sacrificial structures (not shown) are formed on the first semiconductor layer 102. Next, an insulating layer 104 is formed on the first semiconductor layer 102 and the sacrificial structure, and finally the sacrificial structure is removed. The sacrificial structures may be single or multi-layered, and the material of the sacrificial structures may comprise an oxide or nitride, such as SiNx、SiO2And the like. In addition, the width of the sacrificial structure may be smaller than the width of the first semiconductor layer 102. Through the above steps, the insulating layer 104 directly contacting a portion of the fifth surface s5 of the light emitting stack 100, a portion of the first surface s1 of the first semiconductor layer 102, and sidewalls of the first semiconductor layer 102 may be formed. Specifically, the insulating layer 104 may be continuously distributed on a portion of the fifth surface s5, a portion of the first surface s1, and sidewalls of the first semiconductor layer 102. The material of the first semiconductor layer 102 may comprise a group III-V semiconductor material, such as a binary group III-V semiconductor material, e.g., GaAs, GaP, GaN, etc. The insulating layer 104 may comprise a dielectric material such as an oxide or fluoride, for example silicon dioxide (SiO)x) Magnesium fluoride (MgF)2) And the like.
As shown in fig. 1, both the insulating layer 104 and the first semiconductor layer 102 are in direct contact with the light emitting stack 100, and in other words, a portion of the fifth surface s5 of the light emitting stack 100, which is not in direct contact with the first semiconductor layer 102, is in direct contact with the insulating layer 104. Since the insulating layer 104 and the conductive layer 108 have a relatively high resistance, the current path is mainly formed at the portion of the first semiconductor layer 102 directly contacting the conductive layer 108, and thus the semiconductor device can have different current path types by changing the relative distribution positions of the insulating layer 104 and the first semiconductor layer 102.
The conductive layer 108 is located on the reflective layer 110 and directly contacts the first semiconductor layer 102 and the insulating layer 104. The conductive layer 108 may be transparent to light emitted by the light emitting stack 100. Conductive layer 108 may comprise a transparent conductive material, metal, or alloy. Transparent conductive materials include, but are not limited to, Indium Tin Oxide (ITO), indium oxide (InO), tin oxide (SnO), Cadmium Tin Oxide (CTO), Antimony Tin Oxide (ATO), Aluminum Zinc Oxide (AZO), Zinc Tin Oxide (ZTO), Gallium Zinc Oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), Indium Cerium Oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), Indium Zinc Oxide (IZO), Indium Gallium Oxide (IGO), Gallium Aluminum Zinc Oxide (GAZO), graphene, or combinations thereof. Metals include, but are not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), or the like. The alloy may include at least two selected from the group consisting of the above metals.
The reflective layer 110 is disposed on the bonding layer 112 and reflects light emitted from the light emitting stack 100. The material of the reflective layer 110 is electrically conductive and may comprise a metal or an alloy. Metals such as copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W). The alloy may include at least two selected from the group consisting of the above metals. In one embodiment, the reflective layer 110 may have a Distributed Bragg Reflector (DBR) structure.
The bonding layer 112 is disposed on the substrate 114 for connecting the substrate 114 and the reflective layer 110. The material of the bonding layer 112 is electrically conductive and may include a transparent conductive material, metal, or alloy. Transparent conductive materials include, but are not limited to, Indium Tin Oxide (ITO), indium oxide (InO), tin oxide (SnO), Cadmium Tin Oxide (CTO), Antimony Tin Oxide (ATO), Aluminum Zinc Oxide (AZO), Zinc Tin Oxide (ZTO), Gallium Zinc Oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), Indium Cerium Oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), Indium Zinc Oxide (IZO), Indium Gallium Oxide (IGO), Gallium Aluminum Zinc Oxide (GAZO), graphene, or combinations thereof. Metals include, but are not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), or the like. The alloy may include at least two selected from the group consisting of the above metals.
The first electrode 106 and the second electrode 116 are respectively disposed on two sides of the substrate 114 to be electrically connected to an external power source and the light emitting stack 100. The first electrode 106 is located on the light emitting stack 100, and the second electrode 116 is located under the substrate 114. The material of the first electrode 106 and the second electrode 116 may comprise a metal oxide material, a metal, or an alloy. The metal oxide material includes, for example, Indium Tin Oxide (ITO), indium oxide (InO), tin oxide (SnO), Cadmium Tin Oxide (CTO), Antimony Tin Oxide (ATO), Aluminum Zinc Oxide (AZO), Zinc Tin Oxide (ZTO), Gallium Zinc Oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or Indium Zinc Oxide (IZO). Examples of the metal include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni), and copper (Cu). The alloy may include at least two selected from the group consisting of the above metals, such as gold nickel germanium (GeAuNi), gold beryllium (BeAu), gold germanium (GeAu), gold zinc (ZnAu), and the like.
Fig. 2A to fig. 2C are schematic partial cross-sectional views of a semiconductor device according to an embodiment of the present invention. Specifically, fig. 2A to 2C show different embodiments of the first angle θ 1 and the second angle θ 2. For convenience of inspection, the orientations of fig. 2A to 2C are opposite to those of fig. 1, and only the relative positions of the first semiconductor layer 102, the insulating layer 104 and the light emitting stack 100 are shown.
In the embodiment of fig. 2A, the first angle θ 1 is greater than the second angle θ 2, and the first angle θ 1 is less than 90 ° and the second angle θ 2 is also less than 90 °. In another embodiment, the first angle θ 1 is greater than the second angle θ 2, and the first angle θ 1 is greater than 90 ° and the second angle θ 2 is less than 90 °. In the embodiment of fig. 2B, the first angle θ 1 is less than the second angle θ 2, and the first angle θ 1 is less than 90 ° and the second angle θ 2 is greater than 90 °. In another embodiment, the first angle θ 1 is smaller than the second angle θ 2, and the first angle θ 1 is smaller than 90 ° and the second angle θ 2 is also smaller than 90 °. In the embodiment of fig. 2C, the first angle θ 1 is less than the second angle θ 2, and the first angle θ 1 is greater than 90 ° and the second angle θ 2 is also greater than 90 °.
Fig. 3 is a schematic top view of a semiconductor device 20 according to an embodiment of the present invention; fig. 4 is a schematic cross-sectional view of the semiconductor device 20 of fig. 3 along the line X-X'.
In the present embodiment, the first electrode 106 includes an electrode pad 106a and a plurality of extension electrodes 106b connected to the electrode pad 106 a. The electrode pad 106a and the extension electrode 106b may be the same or different materials. As shown in fig. 3, the contact structure 101 may be in a plurality of dot-shaped arrays. It should be noted that since the contact structure 101 is located inside the semiconductor device 20, the contact structure 101 cannot be directly observed from the external appearance of the semiconductor device 20, so that fig. 3 is a top perspective view of the semiconductor device 20 and is drawn by solid lines. As shown in fig. 3, the first semiconductor layer 102 may be distributed between the electrode pad 106a and the extension electrode 106b, or between the extension electrode 106b and the edge of the semiconductor element 20.
As shown in fig. 4, the main differences between the cross-sectional structures of the semiconductor device 20 and the semiconductor device 10 are: in the semiconductor element 20, the second semiconductor layer 118 is further included between the first semiconductor layer 102 or the insulating layer 104 and the light emitting stack 100, and the first electrode 106 and the contact structure 101 do not overlap in the vertical direction. In other words, the first electrode 106 and the first semiconductor layer 102 do not overlap in the vertical direction.
The second semiconductor layer 118 can be used as a current diffusion layer to improve current diffusion, and can also be used as a light extraction layer to improve the light emitting efficiency of the device. The second semiconductor layer 118 may have a thickness greater than the first semiconductor layer 102. The material of the second semiconductor layer 118 may comprise a group III-V semiconductor material, such as a binary group III-V semiconductor material, e.g., GaAs, GaP, GaN, etc. The composition material of the second semiconductor layer 118 may be the same as or different from that of the first semiconductor layer 102. In one embodiment, when the two constituent materials are the same, the interface between the first semiconductor layer 102 and the second semiconductor layer 118 may not be obvious when observed with a Scanning Electron Microscope (SEM). In addition, the first semiconductor structure 100b has a roughened structure R on the surface near the first electrode 106 side. In some embodiments, the first semiconductor structure 100b having the roughened structure R can further improve the light extraction efficiency of the semiconductor device 20.
In some embodiments, the semiconductor element 20 may have a form in which the second semiconductor layer 118 is not included and the first electrode 106 and the contact structure 101 do not overlap in the vertical direction, or a form in which the second semiconductor layer 118 is included and the first electrode 106 and the contact structure 101 overlap in the vertical direction. The position, relative relationship, material composition and other contents of other layers or structures and structural variations in this embodiment have also been described in detail in the previous embodiments, and are not repeated herein.
Fig. 5 is a schematic cross-sectional view of a semiconductor device 20' according to an embodiment of the present invention.
The main difference between the semiconductor device 20' of the present embodiment and the semiconductor device 20 is: the insulating layer 104 and the electrode pad 106a in the semiconductor element 20' do not overlap in the vertical direction. Therefore, as shown in fig. 5, the insulating layer 104 does not directly contact the second semiconductor layer 118 at a position corresponding to the electrode pad 106a in the vertical direction, i.e., a portion of the second semiconductor layer 118 in the semiconductor element 20' is directly contacted with the conductive layer 108. In some embodiments, when the insulating layer 104 and the electrode pad 106a do not overlap in the vertical direction, the semiconductor device may have better Electrostatic Discharge (ESD) characteristics, and the light emitting efficiency may be further improved.
The position, relative relationship, material composition and other contents of other layers or structures and structural variations in this embodiment have also been described in detail in the previous embodiments, and are not repeated herein.
Fig. 6 is a schematic cross-sectional view of a semiconductor device 20 ″ according to an embodiment of the present invention.
The semiconductor device 20 ″ of the present embodiment differs from the semiconductor device 20' mainly in that: the semiconductor element 20 "has a patterned second semiconductor layer 118. Specifically, as shown in fig. 6, the second semiconductor layer 118 includes a first portion 118a and a second portion 118 b. The first portion 118a and the second portion 118b are separated from each other. In this embodiment, in the vertical direction, the first portion 118a overlaps the electrode pad 106a and does not overlap the first semiconductor layer 102, and the second portion 118b does not overlap the electrode pad 106a and overlaps the first semiconductor layer 102. The insulating layer 104 directly contacts the first semiconductor layer 102 and the second portion 118b of the second semiconductor layer 118. The insulating layer 104 does not overlap with the electrode pad 106a in the vertical direction. In the sectional view, the second portion 118b may have a stepped structure S. In detail, as shown in fig. 6, the second portion 118b may include a region R1 closer to the first semiconductor layer 102 and a region R2 closer to the light emitting stack 100, and the width of the region R2 is greater than the width of the region R1. In some embodiments, the patterned second semiconductor layer 118 can avoid the problem that the material of the second semiconductor layer 118 absorbs the light emitted from the light emitting stack 100, which reduces the light emitting efficiency of the semiconductor device.
The position, relative relationship, material composition and other contents of other layers or structures and structural variations in this embodiment have also been described in detail in the previous embodiments, and are not repeated herein.
Fig. 7 is a schematic cross-sectional view of a package structure 600 of a semiconductor device according to an embodiment of the present invention. Referring to fig. 7, the package structure 600 includes a semiconductor device 60, a package substrate 61, a carrier 63, a bonding wire 65, a conductive structure 66, and an encapsulation layer 68. The package substrate 61 may include a ceramic or glass material. The package substrate 61 has a plurality of through holes 62 therein. The vias 62 may be filled with a conductive material, such as a metal, to facilitate electrical conduction and/or heat dissipation. The carrier 63 is located on a surface of one side of the package substrate 61 and also includes a conductive material, such as a metal. The conductive structure 66 is located on the surface of the other side of the package substrate 61. In the embodiment, the conductive structure 66 includes a first contact pad 66a and a second contact pad 66b, and the first contact pad 66a and the second contact pad 66b are electrically connected to the carrier 63 through the through hole 62. In one embodiment, the conductive structure 66 may further include a thermal pad (not shown), for example, between the first contact pad 66a and the second contact pad 66 b.
The semiconductor element 60 is located on a carrier 63. The semiconductor device 60 may be a semiconductor device (e.g., a semiconductor device) according to any embodiment of the present invention. In this embodiment, the carrier 63 includes a first portion 63a and a second portion 63b, and the semiconductor element 60 is electrically connected to the second portion 63b of the carrier 63 by a bonding wire 65. The material of the bonding wire 65 may include a metal, such as gold, silver, copper, aluminum, or an alloy containing at least any of the above elements. The encapsulation layer 68 covers the semiconductor element 60, and has an effect of protecting the semiconductor element 60. Specifically, the encapsulation layer 68 may include a resin material such as epoxy resin (epoxy), silicone resin (silicone), and the like. The encapsulation layer 68 may further include a plurality of wavelength conversion particles (not shown) for converting the first light emitted from the semiconductor device 60 into a second light. The second light has a wavelength greater than the wavelength of the first light.
In view of the above, the present invention can provide a semiconductor device, which is improved in photoelectric characteristics such as light extraction efficiency by its structural design, and can be improved in production efficiency and stability. The utility model discloses a semiconductor element or semiconductor package structure can be applied to the product in fields such as illumination, medical treatment, demonstration, communication, sensing, electrical power generating system, for example lamps and lanterns, monitor, cell-phone, panel computer, automobile-used instrument board, TV, computer, dress device (like wrist-watch, bracelet, necklace etc.), traffic sign, outdoor display, medical equipment etc..
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims. The foregoing embodiments may be combined with or substituted for those described, where appropriate, and are not intended to be limited to the specific embodiments shown. For example, parameters related to specific components or connection relationships between specific components and other components disclosed in one embodiment can be applied to other embodiments, and all of the embodiments fall within the scope of the present invention.
Claims (26)
1. A semiconductor device, comprising:
a first semiconductor layer having a first surface with a first portion; and
an insulating layer directly contacting the first portion and having a first sidewall and a second sidewall;
wherein the first sidewall is inclined by a first angle θ 1 relative to the first surface, the second sidewall is inclined by a second angle θ 2 relative to the first surface, the first angle θ 1 is different from the second angle θ 2, and both the first angle θ 1 and the second angle θ 2 are not equal to 90 °.
2. The semiconductor device of claim 1, further comprising a light emitting stack having a second surface, wherein the first semiconductor layer and the insulating layer are disposed on the second surface.
3. The semiconductor device of claim 2, wherein the insulating layer directly contacts the second surface.
4. The semiconductor device as claimed in claim 2, wherein the first semiconductor layer has a third sidewall and a fourth sidewall, and the insulating layer is continuously disposed on a portion of the second surface, a portion of the first surface, the third sidewall and the fourth sidewall.
5. The semiconductor device as claimed in claim 2, wherein the first semiconductor layer has a third sidewall and a fourth sidewall, and a third angle θ 3 between the third sidewall and the light emitting stack is greater than 90 °, and a fourth angle θ 4 between the fourth sidewall and the light emitting stack is greater than 90 °.
6. The semiconductor device of claim 5, wherein the third sidewall and the fourth sidewall are completely covered by an insulating layer.
7. The semiconductor device as claimed in claim 1, wherein the first angle θ 1 is greater than the second angle θ 2.
8. The semiconductor device as claimed in claim 7, wherein the first angle θ 1 is smaller than 90 ° and the second angle θ 2 is smaller than 90 °.
9. The semiconductor device as claimed in claim 7, wherein the first angle θ 1 is greater than 90 ° and the second angle θ 2 is less than 90 °.
10. The semiconductor device as claimed in claim 7, wherein the first angle θ 1 is greater than 90 ° and the second angle θ 2 is greater than 90 °.
11. The semiconductor device as claimed in claim 1, wherein the first angle θ 1 is smaller than the second angle θ 2.
12. The semiconductor device as claimed in claim 11, wherein the first angle θ 1 is smaller than 90 ° and the second angle θ 2 is larger than 90 °.
13. The semiconductor device as claimed in claim 11, wherein the first angle θ 1 is smaller than 90 ° and the second angle θ 2 is smaller than 90 °.
14. The semiconductor device as claimed in claim 11, wherein the first angle θ 1 is greater than 90 ° and the second angle θ 2 is greater than 90 °.
15. The semiconductor device of claim 1, wherein the insulating layer further has a third surface and a fourth surface, the first sidewall extending between the first surface and the third surface.
16. The semiconductor device of claim 1, wherein the first semiconductor layer comprises a binary III-V semiconductor material.
17. The semiconductor device of claim 2, further comprising a first electrode on the light emitting stack layer, wherein the first electrode and the first semiconductor layer do not overlap in a vertical direction.
18. The semiconductor device of claim 17, wherein the first electrode comprises an electrode pad and a plurality of extension electrodes connected to the electrode pad.
19. The semiconductor device of claim 18, wherein the insulating layer and the electrode pad do not overlap in the vertical direction.
20. The semiconductor device as claimed in claim 1, wherein the first semiconductor layer has an inverted trapezoidal cross-section.
21. The semiconductor device according to claim 2, further comprising a second semiconductor layer between the first semiconductor layer or the insulating layer and the light emitting stack.
22. The semiconductor device as claimed in claim 21, wherein the second semiconductor layer comprises a first portion and a second portion separated from each other, and the second portion has a stepped structure.
23. The semiconductor device according to claim 2, wherein the light emitting stack comprises a first semiconductor structure, and the first semiconductor structure has a roughened structure.
24. The semiconductor device of claim 2, further comprising a conductive layer directly contacting the first semiconductor layer and the insulating layer.
25. The semiconductor device according to claim 24, further comprising a second semiconductor layer between the first semiconductor layer or the insulating layer and the light emitting stack, wherein a portion of the second semiconductor layer is in direct contact with the conductive layer.
26. A semiconductor device package comprising a carrier and the semiconductor device of any one of claims 1-25, wherein the semiconductor device is disposed on the carrier.
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