CN214380078U

CN214380078U - Electric impact current suppression circuit on airborne display

Info

Publication number: CN214380078U
Application number: CN202023104812.0U
Authority: CN
Inventors: 卢小军; 段士龙; 杨粤涛; 张传森; 于杰; 高伟松
Original assignee: Suzhou Changfeng Aviation Electronics Co Ltd
Current assignee: Suzhou Changfeng Avionics Co Ltd; Suzhou Changfeng Aviation Electronics Co Ltd
Priority date: 2020-12-21
Filing date: 2020-12-21
Publication date: 2021-10-08
Anticipated expiration: 2030-12-21

Abstract

The embodiment of the disclosure provides a power-on impact current suppression circuit for an airborne display, which comprises a first thermistor (R1), a first P-channel MOSFET (Q1), a first PNP transistor (Q2), a second NPN transistor (Q3), a first capacitor (C1), a second capacitor (C2), a first resistor (R2), a second resistor (R3), a third resistor (R4), a fourth resistor (R5) and a fifth resistor (R6). The utility model provides a circuit can be applicable to all avionic equipment, establishes ties this circuit between power input and filter capacitance/energy storage capacitor, can effectively restrain the power-on impulse current to improve avionic equipment's reliability and stability.

Description

Electric impact current suppression circuit on airborne display

Technical Field

The disclosure relates to the technical field of avionic devices, in particular to an on-board display power-on impact current suppression circuit.

Background

In the field of avionics, avionic equipment obtains electricity from an aircraft power supply system, the avionic equipment is electric equipment for the aircraft power supply system, most avionic equipment is designed with a filter circuit, and a large-capacity capacitor or an energy storage capacitor is generally designed at a power supply input end. At present, all airborne displays have a power failure holding function, so that a large energy storage capacitor is arranged inside the airborne display when a product is designed to meet the power failure holding function of the display. Excessive surge currents can place significant stress on the aircraft power system. It may cause the device to fail to start, or even cause damage to the power system.

In order to avoid the above problems, the inrush current of the avionics equipment at power-on must be controlled, and many mandatory aviation standards are set for this purpose, in which the power-on inrush current of the avionics equipment is specified, and the avionics equipment must be designed to ensure that the relevant standards are met. At present, no effective method is available for solving the problem of suppression of power-on surge current, and the traditional methods of connecting a fixed resistor in series, a thermistor and the like have defects, such as the fact that the contradiction between a suppression current peak value and a normal steady-state value cannot be solved, the problems that the current-limiting resistor has overlarge dissipation power during steady-state operation and the current-limiting resistor has overlarge voltage drop cannot be solved, and particularly the problems that the surge current peak value cannot be accurately suppressed, so that the operation of a circuit has uncertainty. Another conventional method is to use a resistor to limit current and delay a short-circuit resistor, which cannot determine the charging state of a load capacitor at the rear stage, and simply force the short-circuit resistor after delay, which still may cause a large surge current and damage the switch, and cannot adapt to capacitive loads with different capacities.

SUMMERY OF THE UTILITY MODEL

In view of this, the embodiments of the present disclosure provide a circuit for suppressing power-on impact current of an airborne display, where the circuit can effectively suppress damage to a circuit and a power supply system caused by impact current generated at the moment of power-on of an avionic device, and improve reliability of the avionic device.

In order to achieve the above object, the present invention provides the following technical solutions:

a power-on impact current suppression circuit for an airborne display comprises a first thermistor (R1), a first P-channel MOSFET (Q1), a first PNP transistor (Q2), a second NPN transistor (Q3), a first capacitor (C1), a second capacitor (C2), a first resistor (R2), a second resistor (R3), a third resistor (R4), a fourth resistor (R5) and a fifth resistor (R6);

the first thermistor (R1) has one end connected with the s source electrode of the first P-channel MOSFET (Q1) and the other end connected with the D drain electrode of the first P-channel MOSFET (Q1); the grid G of the first P-channel MOSFET (Q1) is connected with one end of the second resistor (R3), and the drain D is connected with the other end of the second resistor (R3); the gate G of the first P-channel MOSFET (Q1) is connected to the collector C of the first PNP transistor (Q2), and the source S is connected to the emitter E of the first PNP transistor (Q2); one end of the first resistor (R2) is connected with the base B of the first PNP transistor (Q2), and the other end is connected with the a end of the first thermistor (R1), the emitter E of the first PNP transistor (Q2) and the S source of the first P-channel MOSFET (Q1); one end of a third resistor (R4) is connected with a base terminal B of the first PNP transistor (Q2), the other end of the third resistor is connected with a collector terminal C of the second NPN transistor (Q3), a collector terminal C of the second NPN transistor (Q3) is connected with the anode of the second capacitor (C2), an emitting stage terminal of the second NPN transistor (Q3) is connected with the cathode of the second capacitor (C2), one end of a fifth resistor (R6) is connected with the grid G of the first P-channel MOSFET (Q1), the other end of the fifth resistor (R6) is connected with the cathode of the second capacitor (C2) and the emitter terminal E of the second NPN transistor (Q3) and is grounded, the anode of the first capacitor (C1) is connected with the terminal B of the first thermistor (R1), the cathode of the first capacitor (C1) is connected with one end of a base terminal of a fourth resistor (R5), and the other end of the fourth resistor (R5) is connected with the base terminal B3.

Further, the power supply further comprises a first voltage regulator tube (D1), the grid G of the first P-channel MOSFET (Q1) is connected with the positive electrode of the first voltage regulator tube (D1), the drain D of the first P-channel MOSFET (Q1) is connected with the negative electrode of the first voltage regulator tube (D1), the negative electrode of the first voltage regulator tube (D1) is connected with one end of a second resistor (R3), and the positive electrode of the first voltage regulator tube (D1) is connected with the other end of the second resistor (R3).

Further, the first thermistor (R1) is a PTC thermistor.

Furthermore, the input end of the suppression circuit is connected with a power supply.

Further, the output end of the suppression circuit is provided with a large-capacity capacitor, wherein the capacity value of the large-capacity capacitor is not less than the capacity values of the first capacitor (C1) and the second capacitor (C2).

Furthermore, the large-capacity capacitor arranged at the output end of the suppression circuit is a filter capacitor or an energy storage capacitor.

The utility model discloses an on-machine display electric impulse current suppression circuit, its beneficial effect lies in: the utility model provides a circuit can be applicable to all avionic equipment, because the input of these electronic equipment all can connect large capacity filter capacitor, and electric capacity is equivalent to the short circuit when going up, causes to go up electric impulse current very big, consequently establishes ties this circuit between power input and filter capacitor/energy storage capacitor, can effectively restrain and go up electric impulse current to improve avionic equipment's reliability and stability.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of an embodiment of an electrical impact current suppression circuit of the present invention;

fig. 2 is a schematic diagram of charging a capacitor according to an embodiment of the present invention.

Detailed Description

The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.

The embodiment of the disclosure provides a power-on impact current suppression circuit for an airborne display, which includes a first thermistor R1, a first P-channel MOSFET Q1, a first voltage regulator tube D1, a first PNP transistor Q2, a second NPN transistor Q3, a first capacitor C1, a second capacitor C2, a first resistor R2, a second resistor R3, a third resistor R4, a fourth resistor R5 and a fifth resistor R6.

As shown in fig. 1, one end of the first thermistor R1 is connected to the S-source of the first P-channel MOSFET Q1, the other end of the first thermistor R1 is connected to the drain of the first P-channel MOSFET Q1D, the gate G of the first P-channel MOSFET Q1 is connected to the positive electrode of the first regulator D1, the drain D of the first P-channel MOSFET Q1 is connected to the negative electrode of the first regulator D1, the negative electrode of the first regulator D1 is connected to one end of the second resistor R3, the positive electrode of the first regulator D1 is connected to the other end of the second resistor R3, the PNP gate G of the first P-channel MOSFET Q1 is connected to the collector C of the first P-channel transistor Q2, the source S of the first P-channel MOSFET Q1 is connected to the emitter E of the first PNP transistor Q2, one end of the first resistor R2 is connected to the base B of the first PNP transistor Q2, the other end of the first thermistor R2 is connected to the emitter a of the first PNP transistor Q1, and the emitter E of the first PNP transistor Q1 is connected to the emitter E, The source electrode of the first P-channel MOSFET Q1 is connected, one end of a third resistor R4 is connected with the base electrode B end of the first PNP transistor Q2, the other end of the third resistor R4 is connected with the collector electrode C end of the second NPN transistor Q3, the collector electrode C end of the second NPN transistor Q3 is connected with the anode of the second capacitor C2, the emitter electrode day end of the second NPN transistor Q3 is connected with the cathode of the second capacitor C2, one end of a fifth resistor R6 is connected with the grid electrode G of the first P-channel MOSFET Q1, the other end of the fifth resistor R6 is connected with the cathode of the second capacitor C2 and the emitter electrode E end of the second NPN transistor Q3 and is grounded, the anode of the first capacitor C1 is connected with the B end of the first thermistor R1, the cathode of the first capacitor C1 is connected with one end of the fourth resistor R5, and the other end of the fourth resistor R5 is connected with the base electrode B end of the second PNP transistor Q3.

The present invention will be further described with reference to the accompanying drawings and examples.

As shown in fig. 1-2, the power-up process:

a)V_interminal (point A) is connected to the input voltage of the power supply, because of V_outThe output end of the point B is connected with a large-capacity capacitor in a post-stage mode, and the voltage of the point B is 0V. The voltage at the two ends of the capacitor cannot change suddenly, and the voltage at the two ends of the capacitors Cl and C2 is 0V;

b) the input voltage charges the capacitor C2 through the resistors R2 and R4, and the capacitor charging waveform is shown in fig. 2. The switch Q2 is turned on, and the switch Q1 is turned off;

c) the input voltage is limited by a resistor R1(PTC thermistor) and then is applied to V_outCharging a high-capacity capacitor at the rear stage, and rapidly increasing the voltage at the point B;

d) since the voltage at the point B rises rapidly, a current flows through the capacitor C1 and the resistor R5, so that the switch Q3 is turned on, and the voltage across the capacitor C2 drops to 0V. The switch Q3 is turned on to further keep the switch Q2 in a turned-on state, and the switch Q1 in a turned-off state;

e) as the input voltage charges a high-capacity capacitor externally connected to the rear stage through the resistor R1, the voltage at the point B is higher and higher, the rising slope of the voltage at the point B is smaller and smaller, and the current passing through the capacitor C1 is smaller and smaller until the switch Q3 is disconnected;

f) the input voltage charges the capacitor C2 through the resistors R2 and R4, turns on the switch Q2, and maintains the off state of the switch Q1. Thereafter, as the charging current of C2 becomes smaller, switch Q2 turns off;

g) the voltage at the point B and the voltage at the point C are divided by resistors R3 and R6, so that the voltage at the point C is lower than that at the point A, the switch Q1 is conducted, and the resistor R1(PTC thermistor) is short-circuited.

The power up process is now complete.

The utility model discloses a design constraint condition as follows:

a) the output end of the circuit is designed with a large-capacity capacitor:

b) the output end of the circuit is designed with a capacitor with large capacity, and the capacitance value of the capacitor is not less than that of the capacitors Cl and C2;

c) the switch Q1 selects the MOS transistor with lower on-resistance to reduce the loss.

The utility model provides a circuit can be applicable to all avionic equipment, establishes ties this circuit between power input and filter capacitance/energy storage capacitor, can effectively restrain the power-on impulse current to improve avionic equipment's reliability and stability.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A power-on impact current suppression circuit for an airborne display is characterized by comprising a first thermistor (R1), a first P-channel MOSFET (Q1), a first PNP transistor (Q2), a second NPN transistor (Q3), a first capacitor (C1), a second capacitor (C2), a first resistor (R2), a second resistor (R3), a third resistor (R4), a fourth resistor (R5) and a fifth resistor (R6);

2. The power-on surge current suppression circuit for the airborne display according to claim 1, further comprising a first voltage regulator tube (D1), wherein the gate G of the first P-channel MOSFET (Q1) is connected with the positive electrode of the first voltage regulator tube (D1), the drain D of the first P-channel MOSFET (Q1) is connected with the negative electrode of the first voltage regulator tube (D1), the negative electrode of the first voltage regulator tube (D1) is connected with one end of a second resistor (R3), and the positive electrode of the first voltage regulator tube (D1) is connected with the other end of the second resistor (R3).

3. The on-board display power-on rush current suppression circuit of claim 1, characterized in that the first thermistor (R1) is a PTC thermistor.

4. The power-on rush current suppression circuit for an on-board display of claim 1, wherein the input of the suppression circuit is connected to a power source.

5. The power-on rush current suppression circuit for on-board displays according to claim 1, characterized in that the output of the suppression circuit is provided with a bulk capacitor, wherein the bulk capacitor has a capacitance value not less than the capacitance values of the first capacitor (C1) and the second capacitor (C2).

6. The power-on rush current suppression circuit for on-board display of claim 5, wherein the large capacitance provided at the output of the suppression circuit is a filter capacitor or an energy storage capacitor.