CN214354945U

CN214354945U - Inkjet printer device with multiple printing heads

Info

Publication number: CN214354945U
Application number: CN202022607431.8U
Authority: CN
Inventors: 薛祥川; 袁旭光; 陈再敏; 曹勇
Original assignee: Shanghai Rongyue Electronic Technology Co ltd
Current assignee: Shanghai Rongyue Electronic Technology Co ltd
Priority date: 2020-11-12
Filing date: 2020-11-12
Publication date: 2021-10-08
Anticipated expiration: 2030-11-12

Abstract

The utility model discloses a multi-printing head inkjet printer device, which comprises a PCIe core card, a head board and a multifunctional interface board; the PCIe core card is connected with a plurality of headboards and a multifunctional interface board through optical fibers to complete the distribution of image data to be printed and the output of a queue of control instructions; the head board is connected with at least one printing head and drives the printing head to work; the multifunctional interface board transmits the state information of each IO interface and each sensor and a plurality of groups of motor control and coding signals back to the PCIe core card. The utility model connects a plurality of head boards through the PCIe core card, and utilizes the high transmission rate of the PCIe interface to match the data transmission requirements of a plurality of printing heads connected under the plurality of head boards; the FPGA with the embedded SerDes is used for connecting the SFP optical module, so that the characteristics of adjustable receiving and transmitting speed and large range are realized, and the application range of data transmission with different rates is expanded; the bicycle head board can be adapted to the bicycle head boards with different rates at the hand, the cost is saved, the design difficulty of the board card is simplified, and the area of the board card is reduced.

Description

Inkjet printer device with multiple printing heads

Technical Field

The utility model relates to a printer field especially relates to a printer device is beaten to printer head more.

Background

The inkjet printer is a product of a large-scale printer series, and has no printing and high definition of a photo printer, but the definition of the inkjet printer which is proposed at present is greatly improved. The inkjet printer uses solvent type or UV curing type ink, wherein the solvent type ink has strong smell and corrosivity, and the ink permeates into the interior of a printing material through corrosion in the printing process, so that an image is not easy to fade, and the inkjet printer has the characteristics of water resistance, ultraviolet resistance, scratch resistance and the like.

At present, no inkjet printer system for controlling multiple printing heads to print simultaneously in multiple paths exists in the market, and the multiple printing heads have higher requirements on data transmission bandwidth and transmission speed in the multiple-path simultaneous printing; in addition, since the number of the print heads is not fixed, how to match the transmission data according to the number of the print heads is also a problem to be solved. It is therefore desirable to design a multiple printhead inkjet printer apparatus that meets the above requirements.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a main aim at provides a printer device is beaten printer head more, the printer head quantity that beats that configures head board quantity and required support according to the on-the-spot condition that can be nimble.

In order to achieve the above object, the utility model provides a multi-printhead inkjet printer device, which comprises a PCIe core card, a head board and a multifunctional interface board;

the PCIe core card is respectively connected with one or more headboards and a multifunctional interface board through optical fibers to complete the distribution of image data to be printed and the output of a queue of control instructions;

the head board is connected with at least one printing head and drives the printing head to work;

and the multifunctional interface board transmits the state information of each IO interface and each sensor and a plurality of groups of motor control and coding signals back to the PCIe core card.

As a further improvement, be equipped with FPGA module, memory module, optical module interface on the PCIe core card, the FPGA module handles the output of the image data that needs to print and the queue of control command, the memory module with FPGA module electric connection is used for data cache, the FPGA module passes through optical module interface transmission data extremely the head board.

As a further improvement of the present invention, all be equipped with on head board and the multi-function interface board with PCIe core card complex optical module interface.

As a further improvement of the present invention, the optical module interface is an SFP interface.

As a further improvement, be equipped with 5 optical module interfaces on the PCIe core card to have 4 head boards and 1 multi-function interface board through fiber connection.

As a further improvement of the present invention, the PCIe core card is provided with all the sum of the data transmission speeds of the optical module interfaces is smaller than the PCIe bus data transmission bandwidth of the PCIe core card is limited.

As a further improvement of the utility model, the FPGA module is embedded with the SerDes.

As a further improvement of the present invention, the memory module is a DDR3 memory.

The utility model provides a printer device is beaten printer head more has following advantage at least:

in the technical scheme of the utility model, a plurality of head boards are connected through a PCIe core card, and the high transmission rate of a PCIe interface is utilized to match the data transmission requirements of a plurality of printing heads connected under the plurality of head boards; the FPGA with the embedded SerDes is used for connecting the SFP optical module, so that the characteristics of adjustable receiving and transmitting speed and large range are realized, and the application range of data transmission with different rates is expanded; the bicycle head board can be adapted to the bicycle head boards with different rates at the hand, the cost is saved, the design difficulty of the board card is simplified, and the area of the board card is reduced.

Drawings

Fig. 1 is a schematic diagram of a system according to an embodiment of the present invention.

The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

PCI-express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, originally named "3 GIO", which was proposed by Intel in 2001, to replace the old PCI, PCI-X and AGP bus standards.

An FPGA (Field-Programmable Gate Array), i.e., a Field-Programmable Gate Array, is a product of further development based on Programmable devices such as PAL and GAL. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited. The basic structure of the FPGA comprises a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, wiring resources, an embedded special hard core and a bottom layer embedded functional unit. The FPGA has the characteristics of abundant wiring resources, high repeatable programming and integration level and low investment, and is widely applied to the field of digital circuit design. The design process of the FPGA comprises algorithm design, code simulation, design and board machine debugging, wherein an algorithm framework is established by a designer and actual requirements, an EDA (electronic design automation) is used for establishing a design scheme or an HD (high definition) for compiling design codes, the code simulation is used for ensuring that the design scheme meets the actual requirements, finally, board level debugging is carried out, related files are downloaded into an FPGA chip by a configuration circuit, and the actual operation effect is verified.

Referring to fig. 1, the system includes a PCIe core card 1, a headboard 2, and a multifunction interface board 3. In this embodiment, the PCIe core card 1 is connected to 4 headboards 2 and 1 multi-function interface board 3 through optical fibers, and a plurality of print heads can be connected under each headboard 2. The number of headboards 2 and print heads can be configured according to actual needs.

The PCIe core card 1 is plugged in a computer mainboard through a PCIe interface to be used as a main controller, so that the distribution of image data to be printed and the output of a control command queue are completed, and 4 headboards 2 and 1 multi-function interface board 3 are used for inputting various sensors and printer states of 5 secondary controllers, so that the interaction and distribution of data, control commands and state information among all boards are completed. The headboard 2 drives the printing head to work, and the multifunctional interface board 3 transmits the state information of each IO interface and each sensor and a plurality of groups of motor control and coding signals back to the PCIe core card. The cards are connected through optical fiber interfaces, and different optical module models can be selected to be matched with each other according to the requirements of different system data transmission rates at the optical fiber speed. The optical module interface can be an SFP interface or an SFP + interface as required.

The PCIe core card 1 is provided with 5 optical module interfaces and is connected with 4 headboards 2 and 1 multifunctional interface board 3 through optical fibers. The sum of the data transmission speeds of all the optical module interfaces on the PCIe core card 1 should be less than the PCIe bus data transmission bandwidth limit of the PCIe core card 1, otherwise, the result that the data is not transmitted in time is caused. Speed matching of optical fiber transmission between the board cards is required to be done, and a protocol can be used for making a self-adaptive optical fiber speed matching mode to establish a connection relation with 4 head boards 2 and 1 multifunctional interface board 3. The transmission speed of a single SFP optical module on the PCIe core card 1 is the same as that of the correspondingly connected head board 2 optical module. Each head plate 2 can be designed to support the head plate of a single or multiple print heads within the allowable range of the optical fiber transmission speed, and the sum of the maximum data transmission speeds of all the print heads should be less than the effective data transmission speed of the head plate optical module.

For the headboard 2, the speed of travel of the optical module determines how many print heads the board can carry. The sum of the maximum data requirements of the printheads must be less than the effective data transfer bandwidth requirements of the optical modules. In addition, the optical modules on the headboard 2 select optical modules of different packages and types according to the difference of the price of the optical modules and the area of the PCB, and are not limited to the interface mode that only SFP type can be selected, but the design requirement of matching the speed and wavelength of the SFP optical modules on the PCIe core card 1 needs to be confirmed. The rate of all the headboard 2 can be the same or different, and can be flexibly configured according to the existing headboard at hand.

For the multifunctional interface board 3, the main functions are to transmit back status information of each IO interface and sensor, etc., and multiple sets of motor control and coding signals, and the requirement for data transmission bandwidth is not high. In addition, the optical module on the multifunctional interface board 3 selects optical modules of different packages and types according to the price of the optical module and the difference of the area of the PCB, and is not limited to the interface mode that only SFP type can be selected, but the design requirement of matching the speed and wavelength of the SFP optical module on the PCIe core card 1 needs to be confirmed.

The PCIe core card 1 is provided with an FPGA module and a memory module, the FPGA module processes output of image data to be printed and a queue of control instructions, the memory module is electrically connected with the FPGA module and used for data caching, the memory module can select a DDR3 memory, and certain memory capacity is configured according to system requirements. As a preferred mode, the FPGA with the embedded SerDes is used to connect the SFP optical module, so that the characteristics of adjustable transceiving speed and large range are realized, the application range of data transmission with different rates is expanded, and a board card connected with the FPGA and provided with an external SerDes chip is provided, but the speed adjustable range is small. The utility model discloses the cost has been saved to the head board of the different speed in the current hand of can the adaptation, has simplified the design degree of difficulty of integrated circuit board, has reduced the area of integrated circuit board.

The FPGA chips with SerDes of different manufacturers and different models can be selected to achieve different transmission rates. The PCIe communication method comprises the following steps of selecting different PCIe lanes, wherein the number of PCIe lanes currently comprises X1, X2, X4, X8 and X16, and achieving different board cards and computer data transmission bandwidths; different PCIe standards are selected, currently GEN1, GEN2, GEN3, GEN4 and GEN5 are adopted, and different board cards and computer data transmission bandwidths are achieved, see Table 1. The SFP interface may be an SFP + interface.

TABLE 1

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above embodiment numbers of the present invention are only for description, and do not represent the advantages and disadvantages of the embodiments.

The above is only the preferred embodiment of the present invention, and not the scope of the present invention, all the equivalent structures or equivalent flow changes made by the contents of the specification and the drawings or the direct or indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A multi-print-head inkjet printer device is characterized by comprising a PCIe core card, a head board and a multifunctional interface board;

2. The multi-printhead inkjet printer device according to claim 1, wherein an FPGA module, a memory module, and an optical module interface are disposed on the PCIe core card, the FPGA module processes output of queues of image data and control instructions to be printed, the memory module is electrically connected to the FPGA module and is used for data caching, and the FPGA module transmits data to the headboard through the optical module interface.

3. The multi-printhead inkjet printer device of claim 2 wherein the head board and the multi-function interface board each have an optical module interface that mates with the PCIe core card.

4. The multi-printhead inkjet printer device of claim 3 wherein the optical module interface is an SFP interface.

5. The multi-printhead inkjet printer device of claim 3 wherein the PCIe core card has 5 optical module interfaces and is connected to 4 headboards and 1 multi-function interface board through optical fibers.

6. The multi-printhead inkjet printer device of claim 5 wherein the sum of the data transfer speeds of all of the light module interfaces on the PCIe core card is less than the PCIe bus data transfer bandwidth limit of the PCIe core card.

7. The multi-printhead inkjet printer device of claim 2 wherein the FPGA module is embedded with a SerDes.

8. The multi-printhead inkjet printer device of claim 2 wherein said memory module is a DDR3 memory.