CN214337880U

CN214337880U - Differential demodulation circuit and receiving end circuit

Info

Publication number: CN214337880U
Application number: CN202120381238.9U
Authority: CN
Inventors: 邵滨
Original assignee: Shanghai Sillumin Semiconductor Co ltd
Current assignee: Shanghai Sillumin Semiconductor Co ltd
Priority date: 2021-02-20
Filing date: 2021-02-20
Publication date: 2021-10-01
Anticipated expiration: 2031-02-20

Abstract

The utility model provides a differential demodulation circuit and receiving terminal circuit, differential demodulation circuit wherein, include: the device comprises a first filtering module, a second filtering module, a first signal conversion module, a second signal conversion module, a signal detection module and a signal output module; the third end of the first signal conversion module is connected with the first end of the signal detection module, the first end and the second end of the second signal conversion module are respectively connected with the first input signal and the second input signal, the third end of the second signal conversion module is connected with the second end of the signal detection module, and the output end of the signal detection module is connected with the signal output module; whether the first input signal and the second input signal are differential signals or not can be judged, the signal output module is controlled to output corresponding levels, and then the differential signals are demodulated.

Description

Differential demodulation circuit and receiving end circuit

Technical Field

The utility model relates to a communication system technical field especially relates to a differential demodulation circuit and receiving end circuit.

Background

In a communication system, signals received by a receiving end can couple various interference signals in a transmission environment in a signal transmission process, so that the receiving end cannot obtain accurate signals.

The receiving-end circuit generally includes an amplifying circuit and a differential demodulating circuit, and the amplifier amplifies a received signal; the differential demodulation circuit is a circuit which filters the received signals to remove the same interference signals, amplifies the original signals and then demodulates the signals.

SUMMERY OF THE UTILITY MODEL

The utility model provides a differential demodulation circuit and receiving terminal circuit has broken the demodulation circuit solution among the prior art, provides the technical basis for more application environment.

According to the utility model discloses a first aspect provides a differential modulation circuit, include: the device comprises a first filtering module, a second filtering module, a first signal conversion module, a second signal conversion module, a signal detection module and a signal output module;

the first filtering module is configured to: filtering the accessed first input signal, and feeding the filtered first input signal back to the first end of the first signal conversion module; the second filtering module is configured to: filtering the accessed second input signal, and feeding the filtered second input signal back to the second end of the first signal conversion module;

the third end of the first signal conversion module is connected to the first end of the signal detection module, and is configured to amplify the filtered first input signal and the filtered second input signal, convert the amplified first input signal and the filtered second input signal into a single-ended first target signal, and feed the first target signal back to the signal detection module;

a first end and a second end of the second signal conversion module are respectively connected to the first input signal and the second input signal, and a third end of the second signal conversion module is connected to the second end of the signal detection module, and is used for converting the first input signal and the second input signal into a single-ended second target signal after being amplified, and feeding the second target signal back to the signal detection module;

the output end of the signal detection module is connected with the signal output module, and the signal output module is used for:

if the first input signal and the second input signal are detected to be differential signals according to the first target signal and the second target signal, controlling the signal output module to output a first level signal to a terminal of a receiving end;

if the first input signal and the second input signal are detected to be non-differential signals according to the first target signal and the second target signal, controlling the signal output module to output a second level signal to a terminal of a receiving end;

the first level signal is at a low level, and the second level signal is at a high level; or: the first level signal is at a high level and the second level signal is at a low level.

Optionally, the first signal conversion module includes a first transistor and a second transistor;

a control electrode of the first transistor is connected with a first end of the first filtering module, a first electrode of the first transistor is connected with a first electrode of the second transistor and a first end of the signal detection module, and a second electrode of the first transistor is connected with a second electrode of the second transistor;

and the control electrode of the second transistor is connected with the first end of the second filtering module.

Optionally, the second signal conversion module includes a third transistor and a fourth transistor;

a control electrode of the third transistor is connected to the first input signal, a first electrode of the third transistor is connected to a first electrode of the fourth transistor and a first end of the signal detection module, and a second electrode of the third transistor is connected to a second electrode of the fourth transistor;

a control electrode of the fourth transistor is connected to the second input signal.

Optionally, the signal detection module includes a charging unit and a capacitor,

the first end of the charging unit is connected with the third end of the first signal conversion module, the second end of the charging unit is connected with the third end of the second signal conversion module, the output end of the charging unit is connected with the first end of the capacitor, and the charging unit charges the capacitor if detecting that the first input signal and the second input signal are differential signals;

the first end of the capacitor is connected with the signal output module, and if the voltage of the capacitor is higher than a first threshold voltage, the signal output module outputs the first level signal;

and if the voltage of the capacitor is lower than a first threshold voltage and higher than a second threshold voltage, the signal output module outputs the second level signal.

Optionally, the charging unit includes a first charging transistor, a second charging transistor, a third charging transistor, and a fourth charging transistor;

the control electrode and the first electrode of the first charging transistor are connected with the third end of the first signal conversion module, and the control electrode of the first charging transistor is connected with the control electrode of the second charging transistor;

a first pole of the second charging transistor is connected with a third end of the second signal conversion module, and a second pole of the second charging transistor is connected with a second pole of the first charging transistor;

a control electrode and a first electrode of the third charging transistor are connected with a third end of the second signal conversion module, a control electrode of the third charging transistor is connected with a control electrode of the fourth charging transistor, and a second electrode of the third charging transistor is connected with a second electrode of the second charging transistor;

a first pole of the fourth charging transistor is connected to the first end of the signal output module, a second pole of the fourth charging transistor is connected to the second pole of the third charging transistor, and the fourth charging transistor is configured to amplify the received current of the third charging transistor.

Optionally, a ratio of current amplification factors of the first charging transistor and the second charging transistor is 1:1, and a ratio of current amplification factors of the third charging transistor and the fourth charging transistor is 1: N, where N is greater than 0.

Optionally, the signal detection module further includes a bias unit, two ends of the bias unit are respectively connected to the first end and the second end of the capacitor, and the bias unit generates a bias current for the capacitor.

Optionally, the bias unit includes a second current source and a bias resistor;

two ends of the second current source are respectively connected with the first end and the second end of the capacitor;

and two ends of the bias resistor are respectively connected with the first end and the second end of the capacitor.

Optionally, the signal output module includes a schmitt trigger, an input end of the schmitt trigger is connected to the third end of the signal detection module, and an output end of the schmitt trigger is configured to output the first level signal or the second level signal under the control of the signal detection module.

Optionally, the first filtering module includes a first filtering resistor and a first filtering capacitor;

a first end of the first filter resistor receives the first input signal, and a second end of the first filter resistor is connected with a first end of the first signal conversion module;

and two ends of the first filter capacitor are respectively connected with the first end of the first signal conversion module and the ground.

Optionally, the second filtering module includes a second filtering resistor and a second filtering capacitor;

a first end of the second filter resistor receives the second input signal, and a second end of the second filter resistor is connected with a second end of the second signal conversion module;

and two ends of the second filter capacitor are respectively connected with the second end of the second signal conversion module and the ground.

Optionally, the differential demodulation circuit further includes a first current source, one end of the first current source is connected to the fourth terminal of the first signal conversion module and the fourth terminal of the second signal conversion module, respectively, and the other end of the first current source is connected to ground.

According to a second aspect of the present invention, there is provided a receiving end circuit, comprising a first capacitor, a second capacitor, M amplifiers and the differential demodulation circuit of the first aspect and its alternatives, wherein M is greater than or equal to 1;

the M amplifiers are connected in series, and a first input end and a second input end of a first amplifier along the signal transmission direction are respectively connected with the first capacitor and the second capacitor;

the first output end and the second output end of the Mth amplifier along the signal transmission direction respectively output the first input signal and the second input signal to the differential demodulation circuit.

Optionally, the first input terminal and the second input terminal of at least one of the amplifiers are respectively connected to the first clamping module and the second clamping module.

Optionally, the first clamping module includes a first clamping diode and a second clamping diode, and the second clamping module includes a third clamping diode and a fourth clamping diode;

the anode of the first clamping diode is connected with the ground, and the cathode of the first clamping diode is connected with the first input end of the corresponding amplifier;

the anode of the second clamping diode is connected with the first input end of the corresponding amplifier, and the cathode of the second clamping diode is connected with the ground;

the anode of the third clamping diode is connected to the ground, and the cathode of the third clamping diode is connected to the second input end of the corresponding amplifier;

the anode of the fourth clamping diode is connected with the second input end of the corresponding amplifier, and the cathode of the fourth clamping diode is connected with the ground.

Optionally, the first clamping module comprises a first clamping transistor, and the second clamping module comprises a second clamping transistor;

the control electrode and the first electrode of the first clamping transistor are connected with the first input end of the corresponding amplifier, and the second electrode of the first clamping transistor is grounded;

and the control electrode and the first electrode of the second clamping transistor are connected with the second input end of the corresponding amplifier, and the second electrode of the second clamping transistor is grounded.

Optionally, the first clamping module further comprises a third clamping transistor, and the second clamping module further comprises a fourth clamping transistor;

the control electrode and the first electrode of the third clamping transistor are connected with the ground, and the second electrode of the third clamping transistor is connected with the first input end of the corresponding amplifier;

the control electrode and the first electrode of the fourth clamping transistor are connected to the ground, and the second electrode of the fourth clamping transistor is connected to the second input end of the corresponding amplifier.

Optionally, any one of the amplifiers includes a first amplifying transistor, a second amplifying transistor, an isolation capacitor, a third current source, a fourth current source and a load unit,

a control electrode of the first amplifying transistor is connected with a first output end of a previous amplifier or a first capacitor along the signal transmission direction, a first electrode of the first amplifying transistor is connected with a first input end or a first input node of a next amplifier along the signal transmission direction, and a second electrode of the first amplifying transistor is connected with a first end of the third current source;

a control electrode of the second amplifying transistor is connected with a second output end of a previous amplifier or a second capacitor along the signal transmission direction, a first electrode of the second amplifying transistor is connected with a second input end or a second input node of a next amplifier along the signal transmission direction, and a second electrode of the second amplifying transistor is connected with a first end of the fourth current source;

the second end of the third current source is connected with the second end of the fourth current source;

two ends of the isolation capacitor are respectively connected with the second pole of the first amplifying transistor and the second pole of the second amplifying transistor;

two ends of the load unit are respectively connected with the first pole of the first amplifying transistor and the first pole of the second amplifying transistor, and the load unit provides a load for the amplifier.

The utility model provides a differential demodulation circuit and receiving end circuit, among the differential demodulation circuit, signal detection module can judge whether first input signal and second input signal are differential signal through the first target signal and the second target signal that obtain, and control signal output module exports the level that corresponds, and then can realize the demodulation to differential signal, is different from the demodulation circuit solution among the prior art, provides the technical basis for more application environment.

The utility model discloses an in the alternative, increase the clamp module respectively to the input of receiving end circuit to make the voltage of receiving end circuit input within the rated voltage of all kinds of devices, the device among the protection circuit.

The utility model discloses an among the alternative, in the amplifier, adopt isolation capacitor, isolation capacitor coupling common source level amplifier has improved the common mode rejection ability of circuit, and when signal frequency did not reach the carrier frequency, isolation capacitor opened circuit in other words, and the amplifier has the rejection ability to common mode level change, and then realizes only responding to high frequency signal.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

Fig. 1 is a first schematic structural diagram of a differential demodulation circuit according to an embodiment of the present invention;

fig. 2 is a first schematic circuit diagram of a differential demodulation circuit according to an embodiment of the present invention;

fig. 3 is a second schematic circuit diagram of the differential demodulation circuit according to an embodiment of the present invention;

fig. 4 is a third schematic circuit diagram of the differential demodulation circuit according to an embodiment of the present invention;

fig. 5 is a signal waveform diagram of a differential demodulation circuit according to an embodiment of the present invention;

fig. 6 is a fourth schematic circuit diagram of the differential demodulation circuit according to an embodiment of the present invention;

fig. 7 is a fifth schematic circuit diagram of the differential demodulation circuit according to an embodiment of the present invention;

fig. 8 is a sixth schematic circuit diagram of a differential demodulation circuit according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a differential demodulation circuit according to an embodiment of the present invention;

fig. 10 is a seventh schematic circuit diagram of a differential demodulation circuit according to an embodiment of the present invention;

fig. 11 is a circuit schematic diagram eight of the differential demodulation circuit according to an embodiment of the present invention;

fig. 12 is a first schematic diagram illustrating a structure of a receiving-end circuit according to an embodiment of the present invention;

fig. 13 is a signal waveform diagram of a receiving end circuit according to an embodiment of the present invention;

fig. 14 is a schematic diagram of a partial structure of a receiving end circuit according to an embodiment of the present invention;

fig. 15 is a schematic diagram of a part of a circuit of a receiving end circuit according to an embodiment of the present invention;

fig. 16 is a second schematic circuit diagram of a part of a receiving end circuit according to an embodiment of the present invention;

fig. 17 is a schematic diagram of a part of a circuit of a receiving end circuit according to an embodiment of the present invention;

fig. 18 is a circuit diagram of an amplifier according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the description of the present invention, it should be understood that the terms "upper portion", "lower portion", "upper end", "lower surface", "upper surface", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.

In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

In the description of the present invention, "plurality" means a plurality, such as two, three, four, etc., unless specifically limited otherwise.

In the description of the present invention, unless explicitly stated or limited otherwise, the terms "connected" and the like are to be understood broadly, and may for example be fixedly connected, detachably connected, or integrated; can be mechanically connected, electrically connected or can communicate with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

The technical solution of the present invention will be described in detail with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

Referring to fig. 1, the differential demodulation circuit 11 includes: a first filtering module 111, a second filtering module 112, a first signal conversion module 113, a second signal conversion module 114, a signal detection module 115, and a signal output module 116;

the first filtering module 111 is configured to: filtering the accessed first input signal VINP, and feeding back the filtered first input signal VINP to the first end of the first signal conversion module 113; the second filtering module 112 is configured to: filtering the accessed second input signal VINN, and feeding back the filtered second input signal VINN to the second end of the first signal conversion module 113;

the third end of the first signal conversion module 113 is connected to the first end of the signal detection module 115, and is configured to amplify the filtered first input signal and the filtered second input signal, convert the amplified first input signal and the filtered second input signal into a single-ended first target signal, and feed the first target signal back to the signal detection module 115;

a first end and a second end of the second signal conversion module 114 are respectively connected to the first input signal VINP and the second input signal VINN, and a third end of the second signal conversion module 114 is connected to a second end of the signal detection module 115, and is configured to amplify the first input signal VINP and the second input signal VINN, convert the amplified signals into a single-ended second target signal, and feed the second target signal back to the signal detection module 115;

the output end of the signal detection module 115 is connected to the signal output module 116, which is configured to:

if the first input signal VINP and the second input signal VINN are detected to be differential signals according to the first target signal and the second target signal, controlling the signal output module 116 to output a first level signal to a terminal of a receiving end;

if the non-differential signals of the first input signal VINP and the second input signal VINN are detected according to the first target signal and the second target signal, controlling the signal output module 116 to output a second level signal to a terminal of a receiving end;

The first filtering module 111 and the second filtering module 112 may filter a differential signal in the first input signal and the second input signal, so that the signals output by the first signal conversion module 113 and the second signal conversion module 114 are different.

In an example, when the first input signal VINP and the second input signal VINN are differential signals, since the first target signal and the second target signal received by the signal detection module 115 are different, the signal detection module 115 outputs a current, so that the voltage at the input end of the signal output module 116 is increased, and when the voltage reaches a certain value, the signal output module 116 outputs a first level signal;

when the first input signal VINP and the second input signal VINN are not differential signals, since the first target signal and the second target signal received by the signal detection module 115 are the same, the signal detection module 115 does not output current, so that the voltage at the input end of the signal output module 116 is low, and the signal output module 116 outputs a second level signal.

In one example, the first level signal is at a high level, and the second level signal is at a low level; in another example, the first level signal is at a low level, and the second level signal is at a high level; it can be seen that the magnitude relationship between the first level signal and the second level signal is related to the specific design of the signal output module 116, and the signal output module 116 can be designed according to the actual situation.

As described above, the signal detection module 115 may determine whether the first input signal VINP and the second input signal VINN are differential signals through the obtained first target signal and the second target signal, and control the signal output module 116 to output corresponding levels, so as to implement demodulation of the differential signals.

Referring to fig. 2, in one embodiment, the first signal conversion module 113 includes a first transistor M1 and a second transistor M2;

a control electrode of the first transistor M1 is connected to the first terminal of the first filtering module 111, a first electrode of the first transistor M1 is connected to the first electrode of the second transistor M2 and the first terminal of the signal detection module 115, and a second electrode of the first transistor M1 is connected to the second electrode of the second transistor M2;

the control electrode of the second transistor M2 is connected to the first end of the second filtering module 112.

Referring to fig. 3, in one embodiment, the second signal conversion module 114 includes a third transistor M3 and a fourth transistor M4;

a control electrode of the third transistor M3 is coupled to the first input signal VINP, a first electrode of the third transistor M3 is coupled to a first electrode of the fourth transistor M4 and a first end of the signal detection module 115, and a second electrode of the third transistor M3 is coupled to a second electrode of the fourth transistor M4;

a control electrode of the fourth transistor M3 is connected to the second input signal VINN.

Referring to fig. 4, in one embodiment, the signal detection module 115 includes a charging unit 1151 and a capacitor Cr,

a first end of the charging unit 1151 is connected to the third end of the first signal conversion module 113, a second end of the charging unit 1151 is connected to the third end of the second signal conversion module 114, an output end of the charging unit 1151 is connected to the first end of the capacitor Cr, and if the charging unit 1151 detects that the first input signal VINP and the second input signal VINN are differential signals, the capacitor Cr is charged;

a first end of the capacitor Cr is connected to the signal output module 116, and if the voltage of the capacitor Cr is higher than a first threshold voltage, the signal output module 116 outputs a first level signal;

if the voltage of the capacitor Cr is lower than the first threshold voltage and higher than the second threshold voltage, the signal output module 116 outputs a second level signal, and further, the output signal VOUT of the signal output module 116 includes the second level signal and the first level signal.

The working principle of the charging unit 1151 and the capacitor Cr in one embodiment is described below with reference to fig. 4 and 5:

wherein the signal waveform corresponding to VINP is the signal waveform corresponding to the first input signal, the signal waveform corresponding to VINN is the signal waveform corresponding to the second input signal, the signal waveform corresponding to VDEM is the signal waveform corresponding to the output terminal of the charging unit 1151, and the signal waveform corresponding to VOUT is the signal waveform corresponding to the output signal of the signal output module 116; the dashed line corresponding to Vth1 has a first threshold voltage, and the dashed line corresponding to Vth2 has a second threshold voltage;

when the first input signal VINP and the second input signal VINN are differential signals, the charging unit 1151 has an excessive current flowing out to charge the capacitor Cr, and at time t1, the voltage across the capacitor Cr reaches the first threshold voltage Vth1, and at this time, the output signal VOUT of the signal output module 116 starts to turn over and becomes a first level signal.

Referring to fig. 6, the charging unit 1151 includes a first charging transistor M5, a second charging transistor M6, a third charging transistor M7 and a fourth charging transistor M8;

the control electrode and the first electrode of the first charging transistor M5 are connected to the third terminal of the first signal conversion module 113, and the control electrode of the first charging transistor M5 is connected to the control electrode of the second charging transistor M6;

a first pole of the second charging transistor M6 is connected to the third terminal of the second signal conversion module 114, and a second pole of the second charging transistor M6 is connected to the second pole of the first charging transistor M5;

the control electrode and the first electrode of the third charging transistor M7 are connected to the third terminal of the second signal conversion module 114, the control electrode of the third charging transistor M7 is connected to the control electrode of the fourth charging transistor M8, and the second electrode of the third charging transistor M7 is connected to the second electrode of the second charging transistor M6;

a first pole of the fourth charging transistor M8 is connected to the first end of the capacitor Cs, a second pole of the fourth charging transistor is connected to the second pole of the third charging transistor M7, and the fourth charging transistor M8 is configured to amplify the received current of the third charging transistor M7.

In one embodiment, the current amplification ratio of the first charge transistor M5 to the second charge transistor M6 is 1:1, and the current amplification ratio of the third charge transistor M7 to the fourth charge transistor M8 is 1: N, where N > 0.

Where N > 0, it is understood that:

when N is more than 0 and less than 1, the current amplification factor of the third charging transistor M7 is more than that of the fourth charging transistor M8;

when N is 1, the current amplification factor of the third charging transistor M7 is the same as that of the fourth charging transistor M8;

when N > 1, the current amplification factor of the third charging transistor M7 is smaller than that of the fourth charging transistor M8.

In an example, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 have the same size (it can be understood that current amplification factors are the same), when the first input signal VINP and the second input signal VINN are differential signals, the first filtering module 111 and the second filtering module 112 will filter the differential signals, and then the differential signals are amplified only in the third transistor M3 and the fourth transistor M4, because of the current mirror relationship between the first charging transistor M5 and the second charging transistor M6, an excessive current will flow into the third charging transistor M7, a corresponding fourth charging transistor M8 will also have a current, and the capacitor Cr starts to charge;

when the first input signal VINP and the second input signal VINN are non-differential signals, the currents flowing to the first charging transistor M5 and the second charging transistor M6 are the same, no additional current flows into the third charging transistor M7, and the capacitor Cr starts to discharge.

The transistors may be NFETs, i.e., pairs of complementary N-channel MOSFETs, or PFETs, i.e., pairs of complementary P-channel MOSFETs, whether NFETs or PFETs, the control electrodes of the transistors may be understood as the gates of the field effect transistors, and the first and second electrodes of the transistors may be understood as the sources and drains of the field effect transistors.

Referring to fig. 7, in one embodiment, the first filtering module 111 includes a first filtering resistor R1 and a first filtering capacitor C1;

a first terminal of the first filter resistor R1 receives the first input signal VINP, and a second terminal of the first filter resistor R1 is connected to a first terminal of the first signal conversion module 113;

two ends of the first filter capacitor C1 are respectively connected to the first end of the first signal conversion module 113 and ground.

In one embodiment, the second filtering module 112 includes a second filtering resistor R2 and a second filtering capacitor C2;

a first end of the second filter resistor R2 receives the second input signal VINN, and a second end of the second filter resistor R2 is connected to a second end of the second signal conversion module 114;

two ends of the second filter capacitor C2 are respectively connected to the second end of the second signal conversion module 114 and ground.

The filter resistor and the filter capacitor can filter out the differential signal at the input end of the differential demodulation circuit, so that the purpose of differential demodulation is realized.

Referring to fig. 8, in one embodiment, the signal output module 116 includes a schmitt trigger U1, an input terminal of the schmitt trigger U1 is connected to the third terminal of the signal detection module 115, and an output terminal of the schmitt trigger U1 is configured to output the output signal VOUT under the control of the signal detection module.

In one example, the schmitt trigger U1 can be replaced by other devices with level shifting and output functions to convert the slow rising or falling signal of the voltage during the charging and discharging of the capacitor Cr into a square wave signal.

Referring to fig. 9, the differential demodulation circuit 11 further includes a first current source I1, one end of the first current source I1 is connected to the fourth terminal of the first signal conversion module 113 and the fourth terminal of the second signal conversion module 114, respectively, and the other end of the first current source I1 is connected to ground.

The first current source provides a bias current for the first signal conversion module 113 and the second signal conversion module 114.

Referring to fig. 10, the signal detection module 115 further includes a bias unit 1152, two ends of the bias unit 1152 are respectively connected to the first end and the second end of the capacitor Cr, and the bias unit 1152 generates a bias current for the capacitor Cr.

Referring to fig. 5 and 10, the bias unit 1152 may further implement a discharging function for the capacitor Cr, when the first input signal VINP and the second input signal VINN are non-differential signals, the bias unit 112 and the capacitor Cr form a discharging loop, the capacitor Cr starts to discharge, and at time t2, after the voltage across the capacitor Cr drops to the second threshold voltage Vth2, the output signal VOUT of the signal output module 116 is inverted again and becomes the second level signal.

Referring to fig. 11, the bias unit 1152 includes a second current source I2 and a bias resistor R3;

two ends of the second current source I2 are respectively connected to a first end and a second end of the capacitor Cr;

two ends of the bias resistor R3 are respectively connected with the first end and the second end of the capacitor Cr.

In one example, the second current source I2 may be designed to be process and temperature dependent, thereby reducing the effect of process and temperature variations on propagation delays in the circuit.

Referring to fig. 12, the receiving end circuit includes a first capacitor, a second capacitor, M amplifiers and the differential demodulation circuit described above, where M is greater than or equal to 1;

the M amplifiers are connected in series, and a first input end and a second input end of a first amplifier (such as the amplifier at the leftmost end in the signal transmission direction in FIG. 12) are respectively connected with the first capacitor C3 and the second capacitor C4;

the first output terminal and the second output terminal of the mth amplifier in the signal transmission direction (e.g., the rightmost amplifier in fig. 12) output the first input signal and the second input signal, respectively, to the differential demodulation circuit.

The M amplifiers amplify the received signals by M stages.

Referring to fig. 13, a waveform corresponding to DATA is a waveform of information during signal transmission and reception, a waveform corresponding to DRVP is a waveform of a signal received by a first input terminal of the receiving end circuit, and a waveform corresponding to DRVN is a waveform of a signal received by a second input terminal of the receiving end circuit.

Referring to fig. 14, a first input terminal and a second input terminal of at least one amplifier are respectively connected to the first clamping module 13 and the second clamping module 14.

In the above embodiment, the clamping modules are respectively added to the input ends of the receiving end circuits, so that the voltages at the input ends of the receiving end circuits are within the rated voltages of various devices, the devices in the circuits are protected, and the stability of the circuits is improved.

Referring to fig. 15, in one embodiment, the first clamping module 13 includes a first clamping diode D1 and a second clamping diode D2, and the second clamping module 14 includes a third clamping diode D3 and a fourth clamping diode D4;

the anode of the first clamping diode D1 is connected to the ground, and the cathode of the first clamping diode D1 is connected to the first input end of the corresponding amplifier;

the anode of the second clamping diode D2 is connected with the first input end of the corresponding amplifier, and the cathode of the second clamping diode D2 is connected with the ground;

the anode of the third clamping diode D3 is connected to the ground, and the cathode of the third clamping diode D3 is connected to the second input end of the corresponding amplifier;

the anode of the fourth clamping diode D4 is connected with the second input end of the corresponding amplifier, and the cathode of the fourth clamping diode D4 is connected with the ground. Referring to fig. 16, in one embodiment, the first clamp module 13 includes a first clamp transistor N1, and the second clamp module 14 includes a second clamp transistor N2;

the control electrode and the first electrode of the first clamping transistor N1 are connected with the first input end of the corresponding amplifier 12, and the second electrode of the first clamping transistor N1 is grounded;

the control and first poles of the second clamp transistor N2 are connected to the second input of the corresponding amplifier 12, and the second pole of the second clamp transistor N2 is grounded.

In the above embodiment, when the signal transmitting end has a large common mode level change to the receiving end circuit, if the signal transmitting end sinks current to the receiving end circuit through the first capacitor C3 and the second capacitor C4, the first clamp transistor N1 and the first clamp transistor N2 connected to the gate and the drain may clamp voltage; if the signal transmitting terminal draws current to the receiving terminal circuit through the first capacitor C3 and the second capacitor C4, the body diodes of the first clamp transistor N1 and the first clamp transistor N2 can clamp voltage. Thereby ensuring that the voltage seen at the receiving end does not exceed the rated voltage that the device can withstand.

The sink current can be understood as a current from a signal transmitting end to a receiving end circuit, and the pump current can be understood as a current from the receiving end circuit to the signal transmitting end.

Referring to fig. 17, the first clamping module 13 further includes a third clamping transistor N3, and the second clamping module 14 further includes a fourth clamping transistor N4;

the control electrode and the first electrode of the third clamping transistor N3 are connected with the ground, and the second electrode of the third clamping transistor N3 is connected with the first input end of the corresponding amplifier 12;

the control and first poles of the fourth clamp transistor N4 are connected to ground, and the second pole of the fourth clamp transistor N4 is connected to the second input terminal of the corresponding amplifier 12.

In the above embodiment, when the signal sending end has a large common mode level change to the receiving end circuit:

if the signal sending end feeds current to the receiving end circuit through the first capacitor C3 and the second capacitor C4, the body diodes of the first clamp transistor N1 and the first clamp transistor N2 which are connected in a grid-drain mode, and the third clamp transistor N3 and the fourth clamp transistor N4 can also clamp voltage;

if the signal transmitting end draws current to the receiving end circuit through the first capacitor C3 and the second capacitor C4, the body diodes of the first clamp transistor N1 and the first clamp transistor N2, and the third clamp transistor N3 and the fourth clamp transistor N4 connected in a grid-drain mode can clamp voltage. Thereby ensuring that the voltage seen at the receiving end does not exceed the rated voltage that the device can withstand.

Unlike the example of the above embodiment in which the gates and drains of the first clamp transistor N1 and the first clamp transistor N2 are connected to ground and the gates and drains of the third clamp transistor N3 and the fourth clamp transistor N4 are connected to ground and the first input terminal and the second input terminal of the receiving-side circuit are connected to ground, respectively, it can be seen that the first clamp transistor N1 and the third clamp transistor N3 may be interchanged and the second clamp transistor N2 and the fourth clamp transistor N4 may be interchanged.

Referring to fig. 18, any one of the amplifiers includes a first amplifying transistor M9, a second amplifying transistor M10, an isolation capacitor C, a third current source I3, a fourth current source I4, and a load unit 121,

a control electrode of the first amplifying transistor M9 is connected to a first output end of a previous amplifier or a first capacitor C3 in the signal transmission direction, a first electrode of the first amplifying transistor M9 is connected to a first input end of a next amplifier or a first input node in the signal transmission direction, and a second electrode of the first amplifying transistor M9 is connected to a first end of the third current source I3;

a control electrode of the second amplifying transistor M10 is connected to the second output terminal or the second capacitor of the previous amplifier along the signal transmission direction, a first electrode of the second amplifying transistor M10 is connected to the second input terminal or the second input node of the next amplifier along the signal transmission direction, and a second electrode of the second amplifying transistor M10 is connected to the first terminal of the fourth current source I4;

a second terminal of the third current source I3 is connected to a second terminal of the fourth current source I4;

two ends of the isolation capacitor C are respectively connected with the second pole of the first amplifying transistor M9 and the second pole of the second amplifying transistor M10;

two ends of the load unit 121 are respectively connected to the first pole of the first amplifying transistor M9 and the first pole of the second amplifying transistor M10, and the load unit 121 provides a load for the amplifier 12.

The third current source I3 and the fourth current source 14 provide bias currents for the first amplifying transistor M9 and the second amplifying transistor M10.

In the above embodiment, in the amplifier, the isolation capacitor C is adopted, and the isolation capacitor C is coupled to the common-source amplifier, so that the common-mode rejection capability of the circuit is improved, when the signal frequency does not reach the carrier frequency, the isolation capacitor C is equivalent to a broken circuit, the amplifier 12 has the rejection capability on common-mode level change, and further, the response only on high-frequency signals is realized.

In the description herein, references to the description of the term "one embodiment," "an embodiment," or the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims

1. A differential demodulation circuit, comprising: the device comprises a first filtering module, a second filtering module, a first signal conversion module, a second signal conversion module, a signal detection module and a signal output module;

2. The differential demodulation circuit according to claim 1, wherein the first signal conversion block includes a first transistor and a second transistor;

3. The differential demodulation circuit according to claim 1, wherein the second signal conversion block includes a third transistor and a fourth transistor;

4. The differential demodulation circuit of claim 1 wherein the signal detection module comprises a charging unit and a capacitor,

5. The differential demodulation circuit according to claim 4, wherein the charging unit includes a first charging transistor, a second charging transistor, a third charging transistor, and a fourth charging transistor;

6. The differential demodulation circuit according to claim 5, wherein a ratio of current amplification of the first charge transistor to the second charge transistor is 1:1, and a ratio of current amplification of the third charge transistor to the fourth charge transistor is 1: N, where N > 0.

7. The differential demodulation circuit of claim 4 wherein the signal detection module further comprises a bias unit,

the two ends of the bias unit are respectively connected with the first end and the second end of the capacitor, and the bias unit generates bias current for the capacitor.

8. The differential demodulation circuit according to claim 7, wherein the bias unit includes a second current source and a bias resistor;

9. The differential demodulation circuit according to claim 1, wherein the signal output module comprises a schmitt trigger, an input terminal of the schmitt trigger is connected to the third terminal of the signal detection module, and an output terminal of the schmitt trigger is configured to output the first level signal or the second level signal under the control of the signal detection module.

10. The differential demodulation circuit of claim 1 wherein the first filtering module comprises a first filtering resistor and a first filtering capacitor;

11. The differential demodulation circuit of claim 1 wherein the second filtering module comprises a second filtering resistor and a second filtering capacitor;

12. The differential demodulation circuit according to claim 1, further comprising a first current source, one end of the first current source is connected to the fourth terminal of the first signal conversion module and the fourth terminal of the second signal conversion module, respectively, and the other end of the first current source is connected to ground.

13. A receiving end circuit, comprising a first capacitor, a second capacitor, M amplifiers and the differential demodulation circuit of any one of claims 1 to 12, wherein M ≧ 1;

14. The receiver circuit of claim 13, wherein the first input terminal and the second input terminal of at least one of the amplifiers are connected to the first clamping module and the second clamping module, respectively.

15. The receiving end circuit of claim 14, wherein the first clamping module comprises a first clamping diode and a second clamping diode, and the second clamping module comprises a third clamping diode and a fourth clamping diode;

16. The receiving end circuit of claim 14, wherein the first clamping block comprises a first clamping transistor and the second clamping block comprises a second clamping transistor;

17. The receiving end circuit of claim 16, wherein the first clamping block further comprises a third clamping transistor, and wherein the second clamping block further comprises a fourth clamping transistor;

18. The receiving-end circuit of claim 13, wherein any one of the amplifiers comprises a first amplifying transistor, a second amplifying transistor, an isolation capacitor, a third current source, a fourth current source, and a load unit,