CN214335060U - Frequency detection circuit - Google Patents

Abstract

The utility model discloses a frequency detection circuit contains reference oscillator, counter, timer, register and comparator. The utility model provides a store reference digital signal in the register, this reference digital signal represents the reference frequency, the comparator can acquire different second digital signal, every second digital signal represents the product of the frequency of input signal in the second time quantum and coefficient, like this, through comparing reference digital signal and different second digital signal, can obtain the variable quantity of input signal's frequency, promptly, to be transferred to the input signal with the comparison threshold value, thereby indirectly produce fundamental frequency's variable quantity. The utility model provides a frequency detection circuit has advantages such as detect the precision height, simple structure, operating speed height.

Description

Frequency detection circuit

Technical Field

The utility model relates to a frequency detection technique, in particular to frequency detection circuit belongs to integrated circuit technical field.

Background

The frequency detection technology is widely applied and is generally used for processing an external analog signal of a chip, namely, the external analog signal is converted into a digital signal containing frequency information, and then the digital signal is subjected to data processing. The frequency detection technology can also detect the tiny change of an external analog signal and amplify the external analog signal so as to realize certain operation. For example, in an electronic cigarette, if the magnitude and direction of the blowing and sucking airflow are represented by the change of the capacitance, the capacitance can be converted into a digital signal carrying frequency information, and the digital signal is processed to obtain the capacitance and the change thereof, so as to obtain the magnitude and direction of the blowing and sucking current.

In order to reduce the influence of the change of environment, temperature and the like on frequency detection, a basic frequency can be set, and the basic frequency does not change greatly when influenced by the environment, the temperature and the like, so that the reliability of the system is improved. However, when a certain condition causes a drastic change in the fundamental frequency, additional data is required to indicate the degree of the change, so that the frequency status can be expressed comprehensively and accurately. In the prior art, arithmetic circuits such as multipliers and dividers are generally used to obtain the variation of the fundamental frequency. As shown in fig. 1, the frequency detection circuit includes a threshold operation device and a plurality of operation comparators, and the threshold operation device is used for realizing the function of multiplying or dividing the signal of the register unit by a coefficient.

The existing frequency detection circuit comprises an arithmetic circuit, and the arithmetic circuit can greatly increase the complexity of the circuit and simultaneously reduce the arithmetic speed of the circuit.

Disclosure of Invention

The utility model provides a frequency detection circuit can reduce frequency detection circuit's complexity, promotes the operational speed of circuit simultaneously to solve the technical problem that frequency detection circuit's among the correlation technique complexity is high, operational speed is slow.

The utility model discloses specifically adopt following technical scheme to solve above-mentioned technical problem:

a frequency detection circuit, comprising: the device comprises a reference oscillator, a counter, a timer, a register and a comparator;

the first input end of the counter is the input end of the frequency detection circuit, the second input end of the counter is connected with the third output end of the timer, and the output end of the counter is respectively connected with the first input end of the register and the first input end of the comparator;

the output end of the reference oscillator is connected with the first input end of the timer;

the second input end of the timer is connected with the output end of the comparator, the first output end of the timer is connected with the second input end of the register, and the second output end of the timer is connected with the second input end of the comparator;

the output end of the register is connected with the third input end of the comparator, and the output end of the register is the output end of the frequency detection circuit;

wherein the frequency detection circuit is configured to determine an amount of change in a frequency of the input signal.

Compared with the prior art, the utility model discloses a technical scheme have following advantage and show the effect:

(1) the traditional frequency detection precision is limited by the number of digits of the coefficient, the higher the number of digits of the coefficient is, the higher the precision is, and the frequency detection precision in the utility model is not influenced by the number of digits of the coefficient;

(2) the structure is simpler, so that the complexity and the area of a circuit are reduced;

(3) the circuit has higher working speed without a complex multiplier or divider.

Drawings

Fig. 1 is a structure of a frequency detection circuit in the prior art;

fig. 2 is a structure of a frequency detection circuit provided by the present invention;

fig. 3 is a diagram of the working state of the frequency detection circuit provided by the present invention;

fig. 4 is a waveform diagram of the operation of the frequency detection circuit provided by the present invention.

Detailed Description

A frequency detection circuit as shown in fig. 2 includes a reference oscillator 210, a counter 220, a timer 230, a register 240, and a comparator 250. Wherein, the first input terminal of the counter 220 is the input terminal of the frequency detection circuit, the second input terminal of the counter 220 is connected to the third output terminal of the timer 230, and the output terminals of the counter 220 are respectively connected to the first input terminal of the register 240 and the first input terminal of the comparator 250; an output of the reference oscillator 210 is coupled to a first input of the timer 230; a second input terminal of the timer 230 is connected to the output terminal of the comparator 250, a first output terminal of the timer 230 is connected to a second input terminal of the register 240, and a second output terminal of the timer 230 is connected to a second input terminal of the comparator 250; the output end of the register 240 is connected to the third input end of the comparator 250, and the output end of the register 240 is the output end of the frequency detection circuit; the frequency detection circuit is used for determining the variation of the frequency of the input signal.

The operation of the frequency detection circuit is described below.

1) The timer is clocked according to a clock provided by a reference oscillator.

2) The timer outputs the generated clear signal to the counter.

The clear signal is a signal periodically output by a third output end of the timer.

In this embodiment, the clear signal is represented as a Pclr signal, and the generation cycle of the clear signal is Tclr, the generation frequency of the clear signal is 1/Tclr.

3) The counter carries out zero clearing operation according to the zero clearing signal, counts the number of pulses of the input signal, and obtains a first digital signal and M second digital signals, wherein the first digital signal represents the frequency of the input signal in a first time period, the second digital signal represents the product of the frequency of the input signal in a second time period and a coefficient, the second time period and the coefficient corresponding to different second digital signals are different, and M is larger than or equal to 2.

The digital signal a in the counter is gradually increased, and the digital signal a is cleared by a clear signal at the beginning or the end of each period. After the zero clearing operation is finished, the counter starts to count the number of pulses of the input signal and generates a new digital signal A. Wherein the digital signal a comprises a first digital signal and M second digital signals.

In this embodiment, M second time periods may be set in advance. Specifically, M/2 second time periods are set to be smaller than the duration of the first time period, M/2 second time periods are set to be larger than the duration of the first time period, and M is an even number.

Assuming that the first time period is denoted as TA, and the second time periods are denoted as T1, T2, T3, etc., respectively, half of the second time period is shorter than the time period of TA, and the other half of the second time period is longer than the time period of TA.

Please refer to fig. 3 and 4, f_ARepresenting the frequency, f, of the input signal (IN)₀Indicating a reference frequency, which may be said to be f_AAverage value over a certain period of time, f₁-f₄Representing multiples of the frequency of the input signal, i.e. f₁＝f_A*x1，f₂＝f_A*x₂，f₃＝f_A*x₃，f₄＝f_A*x₄. Wherein the first digital signal is according to f_AThe second digital signal being according to f₁Or f₂Or f₃Or f₄The generated digital signal. The reference digital signal has the same number of bits as the first digital signal, and the reference digital signal has the same number of bits as each of the second digital signals.

In this embodiment, a coefficient may also be preset, and the magnitude of the coefficient and the length of the corresponding duration of the second time period form a positive correlation. As can be seen from FIG. 3, f₁And f_ACoefficient x of₁Is TA/T1, f₂And f_ACoefficient x of₂Is TA/T2, f₃And f_ACoefficient x of₃Is TA/T3, f₄And f_ACoefficient x of₄Is TA/T4.

4) The counter sequentially outputs the M second digital signals to the comparator, and the timer sequentially outputs the generated M control signals to the comparator.

The counter outputs a second digital signal to the comparator after each second digital signal is generated.

The second output terminal of the timer may periodically generate a control signal and output the control signal to the comparator.

5) The comparator compares a second digital signal with a reference digital signal in the register every time a control signal is received, and outputs a comparison result, the reference digital signal representing a reference frequency.

The comparison times of the comparator are equal to the times of the control signal output by the timer. That is, if the timer only outputs one control signal in one period, the comparator only needs to perform comparison once; if the timer outputs a plurality of control signals in one period, the comparator needs to perform a plurality of comparisons.

The comparator is operated under the control of the control signal after receiving the control signal every time, the reference digital signal in the register is compared with a second digital signal output by the counter, and a comparison result is obtained and is used for indicating the magnitude of the reference digital signal and the second digital signal.

Suppose according to f₁The second digital signal generated is A1, according to f₂The second digital signal generated is A2, according to f₃The second digital signal generated is A3, according to f₄The generated second digital signal is A4, and the reference digital signal is F, the comparator compares F with A1 when receiving the control signal for the first time, and a comparison result is obtained; when the control signal is received for the second time, comparing F with A2 to obtain a comparison result; when the control signal is received for the third time, comparing the F with A3 to obtain a comparison result; when the control signal is received for the fourth time, F is compared with A4 to obtain a comparison result, and finally 4 comparison results are obtained.

When the frequency detection circuit is activated, the timer outputs the generated refresh signal to the register, the counter outputs the first digital signal to the register, and the register determines the first digital signal as the reference digital signal. Subsequently, the reference digital signal may be updated according to the frequency of the input signal, as described in detail below.

6) And determining the variation of the frequency of the input signal according to the M comparison results output by the comparator.

Specifically, if the M comparison results indicate that the M/2 second digital signals are greater than the first digital signals and the M/2 second digital signals are less than the first digital signals, it is determined that the variation of the frequency of the input signal is less than the predetermined threshold; otherwise, it is determined that the amount of change in the frequency of the input signal is greater than a predetermined threshold.

In this embodiment, if it is determined that the variation of the frequency of the input signal is greater than the predetermined threshold, the variation of the frequency of the input signal is continuously detected; if the variation of the frequency of the input signal is continuously larger than the predetermined threshold value in the predetermined period, the timer outputs the generated refresh signal to the register, the counter outputs the first digital signal counted currently to the register, and the register updates the reference digital signal into the first digital signal.

As shown in fig. 3, the predetermined period may be Tfre, and if the amount of change in the frequency of the input signal between Tfre is continuously greater than the predetermined threshold, it is determined that the reference frequency has changed, and then the reference frequency may be updated. Specifically, the first output terminal of the timer may output the generated refresh signal (Pfre signal) to the register, and the timer outputs the first digital signal to the register, and the register updates the reference digital signal in the register with the first digital signal.

The above description is only a preferred example of the present invention, and is not limited to the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (1)

1. A frequency detection circuit, comprising: the device comprises a reference oscillator, a counter, a timer, a register and a comparator;

the first input end of the counter is the input end of the frequency detection circuit, the second input end of the counter is connected with the third output end of the timer, and the output end of the counter is respectively connected with the first input end of the register and the first input end of the comparator;

the output end of the reference oscillator is connected with the first input end of the timer;

the second input end of the timer is connected with the output end of the comparator, the first output end of the timer is connected with the second input end of the register, and the second output end of the timer is connected with the second input end of the comparator;

the output end of the register is connected with the third input end of the comparator, and the output end of the register is the output end of the frequency detection circuit;

wherein the frequency detection circuit is configured to determine an amount of change in a frequency of the input signal.

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