CN214314663U - Drive circuit, integrated device, battery management chip and battery management system - Google Patents

Abstract

The present disclosure provides a driving circuit for providing control signals to a charge control transistor and a discharge control transistor that control charging and discharging of a battery pack, including: the first driving unit provides a voltage control signal for the discharge control transistor so as to control the on and off of the discharge control transistor through the voltage control signal; and the second driving unit provides a current control signal for the charging control transistor so as to control the on and off of the discharging control transistor through the current control signal, wherein a first resistor is connected between the grid and the source of the charging control transistor, and the on and off of the charging control transistor are controlled through the current control signal and the voltage generated by the first resistor. The disclosure also provides an integrated device, a battery management chip and a battery management system.

Description

Drive circuit, integrated device, battery management chip and battery management system

Technical Field

The disclosure provides a driving circuit, an integrated device, a battery management chip and a battery management system.

Background

In a Battery Management System (BMS), the charging and discharging of a battery pack are generally controlled by a charging switch and a discharging switch. And the charge switch and the discharge switch are driven by their driving circuits.

The charge switch and the discharge switch are usually formed by MOS transistors, and when they are controlled, it is necessary to ensure that they are not damaged. Furthermore, for an integrated driving circuit or a battery management system, it is necessary to reduce power consumption while ensuring system efficiency.

SUMMERY OF THE UTILITY MODEL

In order to solve one of the above technical problems, the present disclosure provides a driving circuit, an integrated device, a battery management chip and a battery management system.

According to an aspect of the present disclosure, a driving circuit for providing control signals to a charge control transistor and a discharge control transistor that control charging and discharging of a battery pack, includes:

a first driving unit providing a voltage control signal to the discharge control transistor so as to control the discharge control transistor to be turned on and off by the voltage control signal; and

and the second driving unit provides a current control signal for the charging control transistor so as to control the on and off of the discharging control transistor through the current control signal, wherein a first resistor is connected between a grid electrode and a source electrode of the charging control transistor, and the on and off of the charging control transistor are controlled through the current control signal and the voltage generated by the first resistor.

According to a driving circuit of at least one embodiment of the present disclosure, the charge control transistor and the discharge control transistor are NMOS transistors or PMOS transistors.

According to the driving circuit of at least one embodiment of the present disclosure, a source of a charging control transistor is connected to a charger/load terminal, a gate of the charging control transistor receives the current control signal, a drain of the charging control transistor is connected to a drain of the discharging control transistor, a gate of the discharging control transistor receives the voltage control signal, and a source of the discharging control transistor is connected to a battery pack terminal.

According to the driving circuit of at least one embodiment of the present disclosure, the driving voltage of the driving circuit is formed by a voltage converting unit that down-converts the highest voltage of the battery pack into the first voltage, and the first voltage is up-converted into the driving voltage.

According to the driving circuit of at least one embodiment of the present disclosure, the first voltage is boosted to be converted into the driving voltage by a charge pump or a boosting circuit.

According to the driving circuit of at least one embodiment of the present disclosure, the first driving unit is: a source of the first PMOS transistor is connected with a driving voltage of the driving circuit and a source of the second PMOS transistor is connected with the driving voltage, a gate of the first PMOS transistor is connected with a gate of the second PMOS transistor, a drain of the first PMOS transistor is connected with a gate of the first PMOS transistor, a drain of the first PMOS transistor is connected with a source of the third transistor, a drain of the second PMOS transistor is connected with a source of the fourth PMOS transistor, a gate of the third PMOS transistor is connected with a gate of the fourth PMOS transistor, a drain of the third PMOS transistor is connected with a gate of the third PMOS transistor, a drain of the third PMOS transistor is connected with a first end of the second resistor, a drain of the fourth PMOS transistor is connected with a cathode of the first Zener diode, a second end of the second resistor is connected with a drain of the first NMOS transistor, a source of the first NMOS transistor is connected with a reference ground, a gate of the first NMOS transistor is connected with an enable signal, the first NMOS transistor is controlled to be turned on or turned off by the enable signal, an anode of the first zener diode is connected with a cathode of the second zener diode, an anode of the second zener diode is connected with a reference ground, a gate of the second NMOS transistor is connected with a drain of the fourth PMOS transistor through a third resistor, a drain of the second NMOS transistor is connected with the driving voltage, a source of the second NMOS transistor is connected with a first end of the fourth resistor, a gate and a source of the second NMOS transistor are connected through a third zener diode, an anode of the third zener diode is connected with a source of the second NMOS transistor, a cathode of the third zener diode is connected with a gate of the second NMOS transistor, a drain of the third NMOS transistor is connected with a drain of the fourth PMOS transistor, a source of the third NMOS transistor is connected with the reference ground, a gate of the third NMOS transistor is connected with the enable signal through an inverter, and an output end of the inverter is further connected with a gate of the fourth NMOS transistor, the source electrode of the fourth NMOS transistor is connected with the reference ground, the drain electrode of the fourth NMOS transistor is connected with the second end of the fifth resistor, the first end of the fifth resistor is connected with the second end of the fourth resistor, and the connection point of the fourth resistor and the fifth resistor serves as the output end of the voltage control signal.

According to the driving circuit of at least one embodiment of the present disclosure, the second driving unit is: the source electrode of the fifth PMOS transistor is connected with the driving voltage, the source electrode of the sixth PMOS transistor is connected with the driving voltage, the grid electrode of the fifth PMOS transistor is connected with the grid electrode of the sixth PMOS transistor, the grid electrode of the fifth PMOS transistor is connected with the drain electrode of the fifth PMOS transistor, the drain electrode of the fifth PMOS transistor is connected with the source electrode of the seventh PMOS transistor, the drain electrode of the sixth PMOS transistor is connected with the source electrode of the eighth PMOS transistor, the grid electrode of the seventh PMOS transistor is connected with the grid electrode of the eighth PMOS transistor, the drain electrode of the seventh PMOS transistor is connected with the first end of the sixth resistor, the drain electrode of the fourth PMOS transistor is connected with the first end of the seventh resistor, the drain electrode of the fifth NMOS transistor is connected with the second end of the sixth resistor, the source electrode of the fifth NMOS transistor is connected with the reference ground, the grid electrode of the fifth NMOS transistor is connected with the enable signal, and the second end of the seventh resistor provides the current control signal.

According to the driving circuit of at least one embodiment of the present disclosure, the current control signal is provided through a drain of the fourth PMOS transistor.

According to an aspect of the present disclosure, an integrated device is integrated with the driving circuit as described in any one of the above.

According to one aspect of the present disclosure, a battery management chip includes:

a drive circuit as claimed in any one of the above;

a voltage conversion unit converting a highest voltage of the battery pack into a driving voltage of a driving circuit.

According to the battery management chip of at least one embodiment of the present disclosure, the voltage conversion unit down-converts the highest voltage of the battery pack into the first voltage, and the first voltage is up-converted into the driving voltage.

The battery management chip according to at least one embodiment of the present disclosure further includes: a control logic unit generating a control signal provided to the driving circuit according to a current detection signal, a temperature detection signal, and/or a battery voltage detection signal, and the driving circuit providing the current control signal and the voltage control signal according to the control signal.

The battery management chip according to at least one embodiment of the present disclosure further includes a voltage collecting unit capable of collecting a voltage of each battery in a battery pack and supplying the collected voltage to the control logic unit as a battery voltage detection signal.

According to one aspect of the present disclosure, a battery management system includes:

a drive circuit as claimed in any one of the above; and

the driving circuit provides a current control signal to the charging control transistor and provides a voltage control signal to the discharging control transistor to control the on and off of the charging control transistor and the discharging control transistor.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 shows a schematic diagram of charge and discharge switch control according to an embodiment of the present disclosure.

Fig. 2 shows a schematic diagram of charge and discharge switch control according to an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of a discharge switch control circuit according to one embodiment of the present disclosure.

Fig. 4 shows a schematic diagram of a charge switch control circuit according to one embodiment of the present disclosure.

FIG. 5 shows a schematic diagram of voltage conversion according to one embodiment of the present disclosure.

FIG. 6 shows a schematic diagram of voltage conversion according to one embodiment of the present disclosure.

FIG. 7 shows a schematic diagram of voltage conversion according to one embodiment of the present disclosure.

FIG. 8 shows a schematic diagram of voltage conversion according to one embodiment of the present disclosure.

FIG. 9 shows a schematic diagram of voltage conversion according to one embodiment of the present disclosure.

FIG. 10 shows a schematic diagram of voltage conversion according to one embodiment of the present disclosure.

Fig. 11 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.

When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., as in "side wall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.

A Battery Management (BMS) chip 10 is provided according to one embodiment of the present disclosure. As shown in fig. 1, wherein the chip 10 may be in the form of an integrated device. The battery management chip may include a driving circuit therein, and the driving circuit may provide control signals to the discharge control transistor 20 and the charge control transistor 30 to control the on and off of the discharge control transistor 20 and the charge control transistor 30, thereby performing charge and discharge control of the battery pack.

Further, as shown in fig. 2, only the driving circuit device 100 may be in the form of an integrated device.

As shown in fig. 1 and 2, a series circuit of the discharge control transistor 20 and the charge control transistor 30 is connected between one end of the battery and one end of the load/charger. Wherein the discharge control transistor 20 and the charge control transistor 30 may be NMOS transistors or PMOS transistors, and the series circuit may be connected between the battery and the positive terminal of the load/charger, and may be connected between the battery and the negative terminal of the load/charger.

In the present disclosure, the charge control transistor and the discharge control transistor are explained taking an NMOS transistor and a negative terminal connected between the battery and the load/charger as an example.

The source of the discharge control transistor 20 is connected to the battery terminal, the drain of the discharge control transistor 20 is connected to the drain of the charge control transistor 30, and the source of the charge control transistor 30 is connected to the load/charger terminal.

The battery management chip 10 or the driving circuit device 100 may provide a control signal to the gate of the discharge control transistor 20 through the pin DSG to control the on or off thereof, and may provide a control signal to the gate of the charge control transistor through the pin CHG to control the on or off thereof.

In the present disclosure, the control signal provided to the discharge control transistor 20 is a voltage control signal by which the controller is turned on or off. The control signal supplied to the charge control transistor 30 is a current control signal, and a first resistor 40 is connected between the source and the gate of the charge control transistor 30, and a voltage signal generated at the first resistor 40 by the current control signal is used as a gate-source voltage of the charge control transistor 30, thereby controlling the on/off of the charge control transistor 30.

Fig. 3 discloses a drive circuit for the discharge control transistor. As shown in fig. 1, the driving circuit may receive the driving voltage Vdrv and an enable signal EN to generate a voltage control signal (DSG pin) of the discharge control transistor.

As shown in fig. 3, the source of the first PMOS transistor 111 is connected to the driving voltage Vdrv and the source of the second PMOS transistor 112 is connected to the driving voltage Vdrv, the gate of the first PMOS transistor 111 is connected to the gate of the second PMOS transistor 112, and the drain of the first PMOS transistor 111 is connected to the gate. The drain of the first PMOS transistor 111 may be connected to a first end of the second resistor 121, and the drain of the second PMOS transistor 112 may be connected to a cathode of the first zener diode 122. As shown in fig. 3, the drain of the first PMOS transistor 111 is connected to the source of the third PMOS transistor 113, the drain of the second PMOS transistor 112 is connected to the source of the fourth PMOS transistor 114, the gate of the third PMOS transistor 113 is connected to the gate of the fourth PMOS transistor 114, the drain of the third PMOS transistor 113 is connected to the gate, the drain of the third PMOS transistor 113 is connected to the first end of the second resistor 121, and the drain of the fourth PMOS transistor 114 is connected to the cathode of the first zener diode 122.

The second end of the second resistor 121 is connected to the drain of the first NMOS transistor 123, and the source of the first NMOS transistor 123 is connected to the ground. The gate of the first NMOS transistor 123 is connected to an enable signal EN, and is controlled to be turned on or off by the enable signal EN.

An anode of the first zener diode 122 may be connected to a cathode of the second zener diode 124, and an anode of the second zener diode 124 may be connected to the ground reference.

The gate of the second NMOS transistor 131 may be connected to the drain of the fourth PMOS transistor 114, or the drain of the fourth PMOS transistor 114 may be connected through the third resistor 132. And may be connected to the drain of the second PMOS transistor when the fourth PMOS transistor is not present.

The drain of the second NMOS transistor 131 may be connected to the driving voltage Vdrv, and the source of the second NMOS transistor 131 may be connected to a first end of the fourth resistor 133, the gate and the source of the second NMOS transistor 131 being connected through a third zener diode 134, wherein the anode of the third zener diode 134 is connected to the source of the second NMOS transistor 131, and the cathode of the third zener diode 134 is connected to the gate of the second NMOS transistor 131.

The drain of the third NMOS transistor 135 may be connected to the drain of the fourth PMOS transistor 114. And may be connected to the drain of the second PMOS transistor when the fourth PMOS transistor is not present. The source of the third NMOS transistor 135 may be connected to the ground reference, and the gate of the third NMOS transistor 135 may be connected to the enable signal EN via the inverter 136. This controls the third NMOS transistor 135 to be turned on or off by the inverse of the enable signal EN.

The output terminal of the inverter 136 is also connected to the gate of the fourth NMOS transistor 137, and the fourth NMOS transistor 137 is controlled to be turned on or off by the inverted signal of the enable signal EN.

The source of the fourth NMOS transistor 137 is connected to ground, the drain of the fourth NMOS transistor 137 is connected to the second terminal of the fifth resistor 138, and the first terminal of the fifth resistor 138 is connected to the second terminal of the fourth resistor 133. And a connection point of the fourth resistor 133 and the fifth resistor 138 may serve as an output terminal of the voltage control signal (DSG pin).

Fig. 4 shows a driving circuit of the charge control transistor. In the driving circuit, the source of the fifth PMOS transistor 141 is connected to the driving voltage Vdrv, and the source of the sixth PMOS transistor 142 is connected to the driving voltage Vdrv. The gate of the fifth PMOS transistor 141 is connected to the gate of the sixth PMOS transistor 142, and the gate of the fifth PMOS transistor 141 is connected to the drain of the fifth PMOS transistor 141. A drain of the fifth PMOS transistor 141 may be connected to a first terminal of the sixth resistor 145, and a drain of the sixth PMOS transistor 142 may be connected to a first terminal of the seventh resistor 146. As shown in fig. 4, the drain of the fifth PMOS transistor 141 is connected to the source of the seventh PMOS transistor 143, the drain of the sixth PMOS transistor 142 is connected to the source of the eighth PMOS transistor 144, the gate of the seventh PMOS transistor 143 is connected to the gate of the eighth PMOS transistor 144, the drain of the seventh PMOS transistor 143 is connected to the gate, the drain of the seventh PMOS transistor 143 is connected to the first end of the sixth resistor 145, and the drain of the fourth PMOS transistor 114 is connected to the first end of the seventh resistor 146.

The drain of the fifth NMOS transistor 147 is connected to the second terminal of the sixth resistor 145, the source of the fifth NMOS transistor 147 is connected to the ground, and the gate of the fifth NMOS transistor 147 is connected to the enable signal EN, so that the fifth NMOS transistor 147 is controlled to be turned on or off by the enable signal EN.

Thus, by means of the driver circuit, a current control signal (pin CHG) can be provided.

Note that, the charge control driver circuit may be provided with no separate circuit, and the drain terminal of the fourth PMOS transistor 114 of the discharge control driver circuit (fig. 3) may be provided as the current control signal (pin CHG).

In the present disclosure, to reduce power consumption of a chip or integrated device. In the present disclosure, the driving voltage Vdrv is generated not by the highest voltage VCC of the battery but by converting the highest voltage VCC of the battery to the intermediate voltage VDD and then by the intermediate voltage VDD. For example, the intermediate voltage VDD may be about 6V, and the driving voltage Vdrv may be about 12V.

Fig. 5 shows a schematic diagram of voltage conversion. The voltage VDD may be converted into the driving voltage Vdrv by a charge pump circuit, or by a boosting circuit, for example.

Wherein various implementations are given in fig. 6-10 for VCC to VDD conversion.

Fig. 6 shows a voltage converter according to a first embodiment of the present disclosure.

As shown in fig. 6, the inductance-type buck conversion unit may buck the battery voltage VCC to a voltage VDDM, and the plurality of LDO buck conversion units may buck the voltage VDDM to voltages V1, V2, … …, Vn, respectively.

Generally, the conversion efficiency of the inductive buck conversion unit can be nearly 100%. The battery voltage can thus be efficiently converted to a low voltage VDDM, for example VDDM equals 12V, by the inductive buck conversion unit. The voltage VDDM is then converted to a lower voltage, e.g. 5.5V, by the LDO buck converter unit. Thus, when the battery voltage is, for example, 48V, the conversion efficiency of the voltage converter may be 12/5.5. However, when the voltage converter only adopts the LDO step-down conversion unit, the conversion efficiency is 48/5.5. Therefore, the conversion efficiency can be obviously improved by the voltage converter of the present disclosure. In the present disclosure, the voltage value of VDDM may be 5V to 12V.

And different devices (or an external MCU or the like) in the battery management system can be supplied with different voltages by the generated plurality of voltages V1, V2, … …, Vn, the voltage values of which may be 1.8V, 3.3V, 5V, or the like. For example, the operating voltage of some devices is 1.8V, some is 3.3V, and some is 5V, so that different operating voltages can be generated according to the requirement so as to provide the devices requiring different voltages.

Fig. 7 shows a voltage converter according to a second embodiment of the present disclosure.

As shown in fig. 7, the inductive buck converter unit may buck the battery voltage VCC to a voltage VDDM, and the plurality of LDO buck converter units may buck the voltage VDDM to voltages V2, V3, V4 (which may be more), respectively, and the inductive boost converter may boost the voltage VDDM to a voltage V1 (which may be more).

Wherein the voltage value of the voltage VDDM may be 5V to 12V, the voltage value of the voltage V1 may be 12V, and the voltage values of the voltages V2, V3, V4 may be 1.8V, 3.3V, 5V, etc.

By the generated voltages V1, V2, V3 and V4, different voltages can be provided for different devices (or external MCUs and the like) in the battery management system, for example, the working voltage of some devices is 1.8V, some devices are 3.3V, and some devices are 5V or 12V, so that different working voltages can be generated according to needs and provided for devices requiring different voltages.

Fig. 8 shows a voltage converter according to a third embodiment of the present disclosure.

As shown in fig. 8, the inductive buck converter unit may buck the battery voltage VCC to a voltage VDDM, and the plurality of LDO buck converter units may buck the voltage VDDM to voltages V2, V3, V4 (which may be more), respectively, and the charge pump boost converter may boost the voltage VDDM to a voltage V1 (which may be more).

Wherein the voltage value of the voltage VDDM may be 5V to 12V, the voltage value of the voltage V1 may be 12V, and the voltage values of the voltages V2, V3, V4 may be 1.8V, 3.3V, 5V, etc.

By the generated voltages V1, V2, V3 and V4, different voltages can be provided for different devices (or external MCUs and the like) in the battery management system, for example, the working voltage of some devices is 1.8V, some devices are 3.3V, and some devices are 5V or 12V, so that different working voltages can be generated according to needs and provided for devices requiring different voltages.

Fig. 9 shows a voltage converter according to a fourth embodiment of the present disclosure.

As shown in fig. 9, the inductance-type buck converter unit may buck the battery voltage VCC to a voltage VDDM1, and the inductance-type buck converter unit may buck the voltage VDDM1 to VDDM 2.

And the plurality of LDO buck conversion units may buck the voltage VDDM2 to voltages V3, V4, V5 (which may be more), respectively. VDDM1 may be referred to as V1 and VDDM2 may be referred to as V2.

Wherein the voltage value of the voltage VDDM1 can be 12V, the voltage value of the voltage VDDM2 can be 5.5V, and the voltage values of the voltages V3, V4 and V5 can be 1.8V, 3.3V, 5V and the like.

By generating a plurality of voltages V1, V2, V3, V4 and V5, different voltages can be provided for different devices (or external MCUs, etc.) in the battery management system, for example, some devices have an operating voltage of 1.8V, some devices have an operating voltage of 3.3V, and some devices have an operating voltage of 5V or 12V, so that different operating voltages can be generated as required to provide the devices requiring different voltages.

Fig. 10 shows a voltage converter according to a fifth embodiment of the present disclosure.

As shown in fig. 10, the inductance-type buck converter unit may buck the battery voltage VCC to a voltage VDDM1, and the charge pump buck converter unit may buck the voltage VDDM1 to VDDM 2.

And the plurality of LDO buck conversion units may buck the voltage VDDM2 to voltages V4, V5 (which may be more), respectively. VDDM1 may be referred to as V1 and VDDM2 may be referred to as V2.

Wherein the voltage value of the voltage VDDM1 can be 12V, the voltage value of the voltage VDDM2 can be 6V, and the voltage values of the voltages V3, V4 and V5 can be 1.8V, 3.3V, 5V and the like.

By generating a plurality of voltages V1, V2, V3, V4 and V5, different voltages can be provided for different devices (or external MCUs, etc.) in the battery management system, for example, some devices have an operating voltage of 1.8V, some devices have an operating voltage of 3.3V, and some devices have an operating voltage of 5V or 12V, so that different operating voltages can be generated as required to provide the devices requiring different voltages.

Although in the embodiments of fig. 6 to 10, a plurality of VDD can be converted, a conversion unit may be used to obtain a VDD voltage as required by the driving circuit.

Fig. 11 provides a battery management system. The voltage collecting unit 200 may be used to collect voltages of the respective batteries, and the VDD generating unit (corresponding to the embodiments of fig. 6 to 10) may generate a VDD voltage to supply power to the respective components. The control logic unit 300 may receive the voltage collected by the voltage collecting unit 200, and the control logic unit 300 generates a control signal (e.g., an enable signal EN) according to the current detection signal, the temperature detection signal, and/or the voltage signal collected by the voltage collecting unit 200 to provide to the driving unit 100, and controls the charge control transistor and the discharge control transistor through the driving unit 100. A charger or load 400 may be connected across the battery.

In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims (14)

1. A drive circuit for providing control signals to a charge control transistor and a discharge control transistor that control charging and discharging of a battery pack, comprising:

a first driving unit providing a voltage control signal to the discharge control transistor so as to control the discharge control transistor to be turned on and off by the voltage control signal; and

and the second driving unit provides a current control signal for the charging control transistor so as to control the on and off of the discharging control transistor through the current control signal, wherein a first resistor is connected between a grid electrode and a source electrode of the charging control transistor, and the on and off of the charging control transistor are controlled through the current control signal and the voltage generated by the first resistor.

2. The driving circuit of claim 1, wherein the charge control transistor and the discharge control transistor are NMOS transistors or PMOS transistors.

3. The driving circuit as claimed in claim 2, wherein the source of the charging control transistor is connected to the charger/load terminal, the gate of the charging control transistor receives the current control signal, the drain of the charging control transistor is connected to the drain of the discharging control transistor, the gate of the discharging control transistor receives the voltage control signal, and the source of the discharging control transistor is connected to the battery pack terminal.

4. The drive circuit according to any one of claims 1 to 3, wherein a drive voltage of the drive circuit is formed by a voltage conversion unit that down-converts a highest voltage of the battery pack into a first voltage, and the first voltage is up-converted into the drive voltage.

5. The drive circuit according to claim 4, wherein the first voltage is up-converted into the drive voltage by a charge pump or a voltage boosting circuit.

6. The drive circuit of claim 1, wherein the first drive unit is: a source of the first PMOS transistor is connected with a driving voltage of the driving circuit and a source of the second PMOS transistor is connected with the driving voltage, a gate of the first PMOS transistor is connected with a gate of the second PMOS transistor, a drain of the first PMOS transistor is connected with a gate of the first PMOS transistor, a drain of the first PMOS transistor is connected with a source of the third transistor, a drain of the second PMOS transistor is connected with a source of the fourth PMOS transistor, a gate of the third PMOS transistor is connected with a gate of the fourth PMOS transistor, a drain of the third PMOS transistor is connected with a gate of the third PMOS transistor, a drain of the third PMOS transistor is connected with a first end of the second resistor, a drain of the fourth PMOS transistor is connected with a cathode of the first Zener diode, a second end of the second resistor is connected with a drain of the first NMOS transistor, a source of the first NMOS transistor is connected with a reference ground, a gate of the first NMOS transistor is connected with an enable signal, the first NMOS transistor is controlled to be turned on or turned off by the enable signal, an anode of the first zener diode is connected with a cathode of the second zener diode, an anode of the second zener diode is connected with a reference ground, a gate of the second NMOS transistor is connected with a drain of the fourth PMOS transistor through a third resistor, a drain of the second NMOS transistor is connected with the driving voltage, a source of the second NMOS transistor is connected with a first end of the fourth resistor, a gate and a source of the second NMOS transistor are connected through a third zener diode, an anode of the third zener diode is connected with a source of the second NMOS transistor, a cathode of the third zener diode is connected with a gate of the second NMOS transistor, a drain of the third NMOS transistor is connected with a drain of the fourth PMOS transistor, a source of the third NMOS transistor is connected with the reference ground, a gate of the third NMOS transistor is connected with the enable signal through an inverter, and an output end of the inverter is further connected with a gate of the fourth NMOS transistor, the source electrode of the fourth NMOS transistor is connected with the reference ground, the drain electrode of the fourth NMOS transistor is connected with the second end of the fifth resistor, the first end of the fifth resistor is connected with the second end of the fourth resistor, and the connection point of the fourth resistor and the fifth resistor serves as the output end of the voltage control signal.

7. The drive circuit according to claim 1 or 6, wherein the second drive unit is: the source electrode of the fifth PMOS transistor is connected with the driving voltage, the source electrode of the sixth PMOS transistor is connected with the driving voltage, the grid electrode of the fifth PMOS transistor is connected with the grid electrode of the sixth PMOS transistor, the grid electrode of the fifth PMOS transistor is connected with the drain electrode of the fifth PMOS transistor, the drain electrode of the fifth PMOS transistor is connected with the source electrode of the seventh PMOS transistor, the drain electrode of the sixth PMOS transistor is connected with the source electrode of the eighth PMOS transistor, the grid electrode of the seventh PMOS transistor is connected with the grid electrode of the eighth PMOS transistor, the drain electrode of the seventh PMOS transistor is connected with the first end of the sixth resistor, the drain electrode of the fourth PMOS transistor is connected with the first end of the seventh resistor, the drain electrode of the fifth NMOS transistor is connected with the second end of the sixth resistor, the source electrode of the fifth NMOS transistor is connected with the reference ground, the grid electrode of the fifth NMOS transistor is connected with the enable signal, and the second end of the seventh resistor provides the current control signal.

8. The driver circuit of claim 6, wherein the current control signal is provided through a drain of a fourth PMOS transistor.

9. An integrated device characterized in that the drive circuit as claimed in any one of claims 1 to 8 is integrated.

10. A battery management chip, comprising:

a drive circuit according to any one of claims 1 to 8;

a voltage conversion unit converting a highest voltage of the battery pack into a driving voltage of a driving circuit.

11. The battery management chip according to claim 10, wherein the voltage conversion unit down-converts the highest voltage of the battery pack into a first voltage, and the first voltage is up-converted into the driving voltage.

12. The battery management chip of claim 10, further comprising: a control logic unit generating a control signal provided to the driving circuit according to a current detection signal, a temperature detection signal, and/or a battery voltage detection signal, and the driving circuit providing the current control signal and the voltage control signal according to the control signal.

13. The battery management chip of claim 12, further comprising a voltage acquisition unit capable of acquiring a voltage of each battery in a battery pack and providing the acquired voltage to the control logic unit as a battery voltage detection signal.

14. A battery management system, comprising:

a drive circuit according to any one of claims 1 to 8; and

the driving circuit provides a current control signal to the charging control transistor and provides a voltage control signal to the discharging control transistor to control the on and off of the charging control transistor and the discharging control transistor.

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