CN214313210U - Display panel and display device - Google Patents
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- CN214313210U CN214313210U CN202120652162.9U CN202120652162U CN214313210U CN 214313210 U CN214313210 U CN 214313210U CN 202120652162 U CN202120652162 U CN 202120652162U CN 214313210 U CN214313210 U CN 214313210U
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Abstract
The embodiment of the utility model discloses a display panel and display device, display panel include the display area and lie in the non-display area of display area one side, the non-display area includes first non-display area and second non-display area; the display panel further includes: a substrate; a voltage signal line located at one side of the substrate and located in the first non-display region; the flat layer is positioned on one side of the substrate and at least positioned in the second non-display area; and the frame glue is positioned on one side of the voltage signal line and the flat layer, which is far away from the substrate, and is positioned in the non-display area, and covers the voltage signal line and the flat layer. The technical problem that cracks are easily caused due to the fact that the difference between the packaging surface above the voltage signal wire and the packaging surface above the peripheral area of the voltage signal wire is large, the data wire below the voltage wiring is broken, and finally the display performance of the OLED display panel is invalid is solved.
Description
Technical Field
The embodiment of the utility model provides a relate to and show technical field, especially relate to a display panel and display device.
Background
An Organic Light-Emitting Display (OLED) is an active Light-Emitting device, has the advantages of high contrast, wide viewing angle, low power consumption, thinner volume, and the like, is expected to become the next generation of mainstream flat panel Display technology, is one of the most concerned technologies in the flat panel Display technology at present, and has a good market prospect.
An important component of an electronic device that implements a display function is a display panel. In the existing display panel, glass cement encapsulation needs to be carried out on a non-display area of the display panel, in the prior art, a cathode voltage wiring line and an anode voltage wiring line which are connected with an external voltage signal exist in the non-display area of an OLED display screen, when glass cement encapsulation is carried out on the area, the area where the cathode voltage wiring line and the anode voltage wiring line are covered by glass cement, the number of the wiring lines is large, the thickness of the wiring lines is different, and the distance exists between the wiring lines, so that a large height offset exists between a glass cement plane packaged in a wiring area and a glass cement plane on a peripheral area easily, cracks easily occur in the place where the offset exists in the glass cement, the glass cement cracks can extend along a film layer to a data line below the glass cement, data line cracks are caused, and finally performance failure of the OLED display panel is caused.
SUMMERY OF THE UTILITY MODEL
In view of this, the embodiment of the present invention provides a display panel and a display device, which solves the technical problem that the OLED display panel finally fails in display performance due to the crack easily caused by the large break between the package surface above the voltage signal line and the package surface above the peripheral area of the voltage signal line, which results in the data line under the voltage wiring to be broken.
In a first aspect, an embodiment of the present invention provides a display panel, including a display area and a non-display area located on one side of the display area, where the non-display area includes a first non-display area and a second non-display area;
the display panel further includes:
a substrate;
a voltage signal line located at one side of the substrate and located in the first non-display region;
a flat layer located at one side of the substrate and at least located in the second non-display area;
and the frame glue is positioned on one side of the voltage signal line and the flat layer, which is far away from the substrate, and is positioned in the non-display area, and covers the voltage signal line and the flat layer.
Optionally, the thickness of the planarization layer is less than or equal to the thickness of the voltage signal line along the light emitting direction of the display panel.
Optionally, along the light emitting direction of the display panel, the thickness of the planarization layer is greater than that of the voltage signal line, and the thickness difference between the planarization layer and the voltage signal line is smaller than that of the voltage signal line.
Optionally, the flat layer is located in the second non-display area.
Optionally, the flat layer is located in the first non-display area and the second non-display area, and a vertical projection of the flat layer on a plane of the substrate covers a vertical projection of the voltage signal line on the plane of the substrate.
Optionally, the display panel further includes a data signal line source line between the substrate and the film layer where the planarization layer is located;
the data signal line source line comprises a first data signal line source line and a second data signal line source line, the first data signal line source line and the second data signal line source line are arranged in different layers, and the vertical projection of the first data signal line source line on the plane of the substrate and the vertical projection of the second data signal line source line on the plane of the substrate are at least partially staggered.
Optionally, the planarization layer comprises an inorganic layer.
Optionally, the inorganic layer comprises SiOx and/or SiNx.
Optionally, the voltage signal lines include an anode voltage signal line and/or a cathode voltage signal line.
In a second aspect, an embodiment of the present invention further provides a display device, including the display panel of the first aspect.
The embodiment of the utility model provides a display panel, including the display area and be located the non-display area of display area one side, the non-display area includes first non-display area and second non-display area; the display panel further includes: a substrate; a voltage signal line located at one side of the substrate and located in the first non-display region; the flat layer is positioned on one side of the substrate and at least positioned in the second non-display area; and the frame glue is positioned on one side of the voltage signal line and the flat layer, which is far away from the substrate, and is positioned in the non-display area, and covers the voltage signal line and the flat layer. The technical problem that due to the fact that cracks are easily caused due to the fact that the breaking difference between the packaging surface above the voltage signal wire and the packaging surface above the peripheral area of the voltage signal wire is large, the data wire below the voltage wiring is broken, and finally the display performance of the OLED display panel is failed is solved.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
FIG. 1 is a schematic diagram of a display panel according to the prior art;
FIG. 2 is a schematic cross-sectional view of a display panel in the area A of FIG. 1 along the direction BB';
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a display panel along the direction CC' in the region D shown in FIG. 3;
FIG. 5 is a schematic cross-sectional view of another display panel along the direction CC' in the area D shown in FIG. 3;
fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be described in detail through the following embodiments with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some embodiments of the present invention, not all embodiments, and all other embodiments obtained by those skilled in the art without creative efforts based on the embodiments of the present invention all fall into the protection scope of the present invention.
Examples
FIG. 1 is a schematic diagram of a display panel according to the prior art; fig. 2 is a schematic cross-sectional view of a display panel in the direction BB' in the region a shown in fig. 1. Referring to fig. 1-2, in the prior art, a display panel 10 includes a display area 11 and a non-display area 12 located on one side of the display area, where the non-display area 12 is usually provided with a large number of voltage signal lines 14, and in the process of packaging the display panel, due to the large number of wires, different thicknesses, and the spaces between the wires, a large height offset easily exists between a glass glue plane packaged in a wire area and a glass glue plane on a peripheral area, and in actual production, as shown in fig. 2, an offset height h1 can reach up to 0.75um, and due to the existence of the offset, the glass glue is easily cracked at an offset inflection point, so that a data line below the voltage wire is broken, and finally, the display performance of the OLED display panel is disabled.
Based on the above technical problem, an embodiment of the present invention provides a display panel, and fig. 3 is a schematic structural diagram of a display panel provided by an embodiment of the present invention; fig. 4 is a schematic cross-sectional view of a display panel along the direction CC' in the region D shown in fig. 3. With reference to fig. 3 and 4, the display panel 20 according to the embodiment of the present invention includes a display area 21 and a non-display area 22 located at one side of the display area 21, where the non-display area 22 includes a first non-display area 221 and a second non-display area 222;
the display panel 20 further includes:
a substrate 23;
a voltage signal line 24 located at one side of the substrate 23 and located in the first non-display region 221;
a planarization layer 25 on one side of the substrate 23 and at least in the second non-display region 222;
the sealant 26 is disposed on the side of the voltage signal line 24 and the planarization layer 25 away from the substrate 23 and in the non-display region 22, and the sealant 26 covers the voltage signal line 24 and the planarization layer 25.
As shown in fig. 3-4, the display panel 20 according to an embodiment of the present invention includes a display area 21 and a non-display area 22 located on one side of the display area, wherein the non-display area 22 generally has a greater number of voltage signal lines 24, and further, the non-display area 22 includes a first non-display area 221 and a second non-display area 222 according to the distribution of the voltage signal lines 24.
With reference to fig. 3 and 4, according to the actual packaging process, glass sealant packaging may be performed along the periphery of the display area 21 of the display panel 20 to form sealant 26, and then the display panel may be prepared by other processes. When the sealant 26 region overlaps the voltage signal line 24 region of the non-display region 22, the planarization layer 25 is added between the voltage signal lines 24 to reduce the surface variation of the sealant 26. Specifically, the voltage signal lines 24 are located on the substrate 23 side of the display panel 20 and located in the first non-display region 221, that is, the region where the voltage signal lines 24 are located may be set as the first non-display region 221, and the additional flat layer 25 is located on the substrate 23 side of the display panel 20 and located in at least the second non-display region 222 by adding a film layer, that is, before the sealant 26 is encapsulated, the flat layer 25 is added in the region between the voltage signal lines 24 or in the region between the voltage signal lines 24 and in the region above the voltage signal lines 24.
Taking the schematic diagrams of the cross sections in the direction of the region CC' in fig. 3 and fig. 4 along the D region in fig. 3 as an example, the sealant 26 at the side of the voltage signal line 24 and the flat layer 25 far from the substrate 23 and located in the non-display region 22 is encapsulated, the sealant 26 covers the voltage signal line 24 and the flat layer 25, the surface of the sealant 26 layer formed above the voltage signal line 24 is relatively flat, a large break formed between the surface of the sealant 26 layer above the voltage signal line 24 and the surface of the sealant 26 layer above the peripheral region of the voltage signal line 24 can be effectively reduced, and the generation of cracks is effectively slowed or avoided, so that the data line below the voltage trace 24 is prevented from being broken, and the display performance of the OLED display panel is ensured.
The substrate 23 may be a flexible substrate, and the material of the substrate may include at least one of polyimide, polyethylene terephthalate, polycarbonate, polyarylate, and polyethersulfone; the substrate 23 may also be a rigid substrate, specifically, a glass substrate or other rigid substrates, which is not limited in the embodiment of the present invention. It should be noted that the display panel provided in this embodiment further includes other film layers, which together function to realize the display function of the display panel, and the description is not provided here.
To sum up, the embodiment of the present invention provides a display panel, which includes a display area and a non-display area located at one side of the display area, wherein the non-display area includes a first non-display area and a second non-display area; the display panel further includes: a substrate; a voltage signal line located at one side of the substrate and located in the first non-display region; the flat layer is positioned on one side of the substrate and at least positioned in the second non-display area; and the frame glue is positioned on one side of the voltage signal line and the flat layer, which is far away from the substrate, and is positioned in the non-display area, and covers the voltage signal line and the flat layer. The method has the advantages that the flat layer is filled in the peripheral area of the voltage signal wire or the peripheral area of the voltage signal wire and the peripheral area of the non-display area in advance, and then glass cement packaging is carried out on the non-display area, so that the height difference between the packaging surface above the voltage signal wire and the packaging surface above the peripheral area of the voltage signal wire is relieved, the packaging surface above the voltage signal wire tends to be flat, and the technical problem that cracks are easily caused due to the fact that the breaking difference between the packaging surface above the voltage signal wire and the packaging surface above the peripheral area of the voltage signal wire is large, the data wire below the voltage wiring is broken, and finally the display performance of the OLED display panel is failed is solved.
As a possible implementation, with continued reference to fig. 4, the planarization layer 25 is optionally located in the second non-display area 222. Illustratively, on a spatial scale, the second non-display region 222, in which the flat layer 25 is located at the periphery of the voltage signal line 24, is arranged, and the flat layer 25 is prepared by adding a film layer preparation process to fill the second non-display region 222 at the periphery of the voltage signal line 24, so that the surface fault of the sealant 26 layer of the voltage signal line 24 and the surrounding second non-display region 222 can be effectively alleviated, and the problem of performance failure of the display panel caused by sealant 26 cracks due to the fault can be reduced or avoided.
As another possible implementation, fig. 5 is a schematic cross-sectional view of another display panel along the CC' direction in the area D shown in fig. 3, and as shown in fig. 5, optionally, the flat layer 25 is located in the first non-display area 221 and the second non-display area 222, and a vertical projection of the flat layer 25 on the plane of the substrate 23 covers a vertical projection of the voltage signal line 24 on the plane of the substrate 23.
Illustratively, on a spatial scale, the flat layer 25 is disposed in the first non-display region 221 including the voltage signal line 24 and the second non-display region 222 around the voltage signal line 24, and a vertical projection of the flat layer 25 on a plane of the substrate 23 is disposed to cover a vertical projection of the voltage signal line 24 on the plane of the substrate 23. Through the structural design, on one hand, the process preparation can be simplified, the first non-display area 221 containing the voltage signal line 24 and the second non-display area 222 around the voltage signal line 24 are covered by the flat layer 25, the film preparation is simple, and on the other hand, the flat layer 25 is arranged above the first non-display area 221 and the second non-display area 222, so that the fault difference of the surface of the rubber frame 26 above the voltage signal line 24 can be avoided, the generation of cracks is prevented, and the effect of protecting the display panel is achieved.
In one possible implementation, with continued reference to fig. 4, optionally, the thickness h2 of the planarization layer 25 is less than or equal to the thickness h3 of the voltage signal line 24 along the light-emitting direction (as shown by the X direction in the figure) of the display panel 20.
Illustratively, with continued reference to fig. 4, in the light emitting direction of the display panel 20 (as shown in the X direction), in consideration of the actual film layer preparation process, the planarization layer 25 may be filled between the voltage signal lines 24, and the thickness h2 of the planarization layer 25 is ensured to be less than or equal to the thickness h3 of the voltage signal lines 24, so as to reduce the height difference between the surface of the voltage signal lines 24 and the surface of the surrounding area. Preferably, the thickness h2 of the planarization layer 25 is equal to the thickness h3 of the voltage signal line 24. Through the structural arrangement, when the frame adhesive 26 is further packaged above the voltage signal line 24, the break difference of the surface of the frame adhesive 26 of the voltage signal line 24 and the surrounding area can be effectively reduced, so that the frame adhesive 26 cracks caused by the break difference can be effectively reduced or avoided, and the problem that the display panel performance fails due to the fact that the cracks extend to a data line layer below the film layer is avoided.
In one possible implementation manner, with reference to fig. 5, alternatively, in the light emitting direction (as shown in the X direction) of the display panel 20, the thickness h2 of the planarization layer 25 is greater than the thickness h3 of the voltage signal line 24, and the thickness difference δ h between the planarization layer 25 and the voltage signal line 24 is smaller than the thickness h3 of the voltage signal line 24.
For example, as shown in fig. 5, in the case that the planarization layer 25 is filled in the peripheral region of the voltage signal line 24 and the upper region of the voltage signal line 24, so that the thickness h2 of the planarization layer 25 is greater than the thickness h3 of the voltage signal line 24, the requirement that the value of the thickness difference δ h between the planarization layer 25 and the voltage signal line 24 is less than the thickness h3 of the voltage signal line 24 is satisfied. Through the structural design, on one hand, as long as the flat layer 25 effectively fills the peripheral area of the voltage signal line 24 and the upper area of the voltage signal line 24, the film layer is simple and easy to prepare, on the other hand, the thickness difference δ h between the flat layer 25 and the voltage signal line 24 is smaller than the thickness h3 of the voltage signal line 24, and by controlling the thickness of the flat layer 25, the height difference between the upper area of the voltage signal line 24 and the peripheral area caused by the introduction of the flat layer 25 is reduced, so that the difference of the surface of the rubber frame 26 is further reduced, and in sum, the phenomenon of cracks caused by the large difference of the surface of the rubber frame 26 is effectively avoided.
Optionally, the planarization layer comprises an inorganic layer. When the display panel frame is sealed, a mode that the packaging adhesive is irradiated by a laser beam with higher energy to melt the packaging adhesive is generally adopted, an inorganic material is selected as the flat layer, the thermal property of the inorganic material is stable, and the problems that the flat layer structure is changed in performance due to too high energy of the laser beam, and then the lower voltage signal line, the lower data line and the like are influenced when the frame is sealed can be effectively avoided.
Optionally, the inorganic layer comprises SiOx and/or SiNx. Illustratively, one or a combination of more than two of SiOx and SiNx, for example, SiO, may be used2、SiN、Si3N4Etc., without being particularly limited thereto.
Optionally, the voltage signal lines include an anode voltage signal line and/or a cathode voltage signal line.
Illustratively, the voltage signal lines are important wirings for realizing voltage driving of the display panel, the voltage signal lines in this embodiment include anode voltage signal lines and/or cathode voltage signal lines, specific positions are not limited here, when the anode voltage signal lines or the cathode voltage signal lines and surrounding areas thereof are encapsulated by the sealant, the sealant surface is prone to generate a break difference, and by filling the flat layer, the break difference can be effectively reduced, and the function of protecting the panel is achieved. Alternatively, the voltage signal line may be made of at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, and Ca.
Optionally, as shown in fig. 4 and 5, the display panel 20 further includes a data signal line source line 27 located between the substrate 23 and the film layer where the planarization layer 25 is located;
the data signal line source line 27 includes a first data signal line source line 271 and a second data signal line source line 272, the first data signal line source line 271 and the second data signal line source line 272 are arranged in different layers, and a vertical projection of the first data signal line source line 271 on the plane of the substrate 23 and a vertical projection of the second data signal line source line 272 on the plane of the substrate 23 are at least partially staggered.
For example, as shown in fig. 4 and fig. 5, the display panel 20 further includes data signal line source lines 27 located between the substrate 23 and the film layer where the flat layer 25 is located, along with the improvement of the display panel function and the display resolution and the narrow frame design of the display panel 20, the number of the data signal line source lines 27 is increasing, and in the film layer preparation of the display panel 20, the distance, the arrangement, the number, and the like of the data signal line source lines 27 directly affect the preparation height of the film layer in the X direction in the drawing in the film layer preparation process, and finally affect whether there is a break difference on the surface of the frame glue 26 layer of the display panel. Further, by reasonably designing the arrangement of the data signal line source lines 27, the break of the display panel frame glue 26 layer above the data signal line source lines 27 and the voltage signal lines 24 can be effectively reduced.
Specifically, in fig. 4 and 5, the data signal line source line 27 includes a first data signal line source line 271 and a second data signal line source line 272. According to the type of the data signal line source line 27, the first data signal line source line 271 and the second data signal line source line 272 are arranged in different layers, and the vertical projection of the first data signal line source line 271 on the plane of the substrate 23 is at least partially staggered with the vertical projection of the second data signal line source line 272 on the plane of the substrate 23. The first data signal line source line 271 may be a data signal line or a scanning signal line, the second data signal line source 272 may be a data signal line or a scanning signal line, specific routing arrangement is not described in detail here, and the data signal line sources are connected to each other, so that intelligent display of the display panel is achieved. By adopting the structural arrangement, the first data signal line source line 271 and the second data signal line source line 272 are staggered in the X direction, so that the surface of the insulating layer between the first data signal line source line 271 and the second data signal line source line 272 can be effectively prevented from having a break difference, the surface of the insulating layer between the second data signal line source line 272 and the voltage signal line 24 can be effectively prevented from having a break difference, the phenomenon that the surface of the frame adhesive 26 layer of the display panel is broken is further avoided, and the data signal transmission performance of the display panel is further improved.
Based on same utility model concept, the embodiment of the utility model provides a still provide a display device, fig. 6 is the embodiment of the utility model provides a display device's schematic structure diagram. As shown in fig. 6, the display device 100 includes the display panel 20 according to any embodiment of the present invention, and therefore, the display device 100 provided by the embodiment of the present invention has the technical effects of the technical solutions in any of the embodiments, and the explanation of the same or corresponding structures and terms as those in the embodiments is not repeated herein. The embodiment of the present invention provides a display device 100, which can be a mobile phone as shown in fig. 6, and also can be any electronic product with a display function, including but not limited to the following categories: TV set, notebook computer, desktop display, panel computer, digital camera, intelligent bracelet, intelligent glasses, vehicle-mounted display, medical equipment, industry control equipment, touch interaction terminal etc. the embodiment of the utility model provides a do not do special restriction to this.
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the specific embodiments illustrated herein, and that the embodiments and features of the embodiments may be combined without conflict. Numerous obvious variations, rearrangements, combinations, and substitutions will now occur to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.
Claims (10)
1. A display panel is characterized by comprising a display area and a non-display area positioned on one side of the display area, wherein the non-display area comprises a first non-display area and a second non-display area;
the display panel further includes:
a substrate;
a voltage signal line located at one side of the substrate and located in the first non-display region;
a flat layer located at one side of the substrate and at least located in the second non-display area;
and the frame glue is positioned on one side of the voltage signal line and the flat layer, which is far away from the substrate, and is positioned in the non-display area, and covers the voltage signal line and the flat layer.
2. The display panel according to claim 1, wherein the thickness of the planarization layer is less than or equal to the thickness of the voltage signal line in a light exit direction of the display panel.
3. The display panel according to claim 1, wherein a thickness of the planarization layer is greater than a thickness of the voltage signal line, and a difference in thickness between the planarization layer and the voltage signal line is less than the thickness of the voltage signal line in a light emitting direction of the display panel.
4. The display panel according to claim 1, wherein the flat layer is located in the second non-display region.
5. The display panel according to claim 4, wherein the flat layer is located in the first non-display area and the second non-display area, and a vertical projection of the flat layer on a plane of the substrate covers a vertical projection of the voltage signal line on the plane of the substrate.
6. The display panel according to claim 1, further comprising a data signal line source line between the substrate and the film layer in which the planarization layer is located;
the data signal line source line comprises a first data signal line source line and a second data signal line source line, the first data signal line source line and the second data signal line source line are arranged in different layers, and the vertical projection of the first data signal line source line on the plane of the substrate and the vertical projection of the second data signal line source line on the plane of the substrate are at least partially staggered.
7. The display panel of claim 1, wherein the planarization layer comprises an inorganic layer.
8. The display panel according to claim 7, wherein the inorganic layer comprises SiOx and/or SiNx.
9. The display panel according to claim 1, wherein the voltage signal lines include an anode voltage signal line and/or a cathode voltage signal line.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120652162.9U CN214313210U (en) | 2021-03-30 | 2021-03-30 | Display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120652162.9U CN214313210U (en) | 2021-03-30 | 2021-03-30 | Display panel and display device |
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| CN214313210U true CN214313210U (en) | 2021-09-28 |
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