CN214205498U

CN214205498U - Selection device applied to multiplexer, processor, network-on-chip system and parallel computing system

Info

Publication number: CN214205498U
Application number: CN202120212875.3U
Authority: CN
Inventors: 不公告发明人
Original assignee: Beijing Yuanqi Advanced Microelectronics Co ltd
Current assignee: Hangzhou Yuanhe Technology Co ltd
Priority date: 2021-01-26
Filing date: 2021-01-26
Publication date: 2021-09-14
Anticipated expiration: 2031-01-26

Abstract

The embodiment of the application provides a selection device applied to a multiplexer, the multiplexer, a processor, a network-on-chip system and a parallel computing system. The multiplexer is used for accessing m enabling signals EN [ m-1: 0%]And n-way data D₀‑D_n‑1M enable signals are used for indicating the gating state of n paths of data, and m and n are positive integers larger than 1; the selection device comprises n selection units corresponding to the n paths of data one by one, wherein the input end of the jth selection unit is connected with the jth data D_j‑1The control terminal of the jth selection unit is used for accessing a control signal SEL [ j-1]The control signal is used for controlling the selection unit to be in a gating state, wherein j is [1, n ]]And j is an integer, control signal SEL [ j-1 ]]According to gating priority higher than and equal to D_j‑1Generating an enable signal corresponding to the data of (1); the output ends of the n selection units are connected with the output stage of the selection device.

Description

Selection device applied to multiplexer, processor, network-on-chip system and parallel computing system

Technical Field

The present application relates to the field of electronic circuit technologies, and in particular, to a selection device applied to a multiplexer, a processor, a network on chip system, and a parallel computing system.

Background

The multiplexer, also called data selector, can select any path of data through the multiplexer in the transmission process of the multi-path data.

The prior multi-path selector is usually integrated in an FPGA device, when a user uses the multi-path selector with priority, the structure of the multi-path selector needs to be described through codes to complete parametric design, the FPGA can form a cascade structure according to the parametric design based on a lookup table LUT, and the priority of each path of signal is judged through the lookup table LUT and the like to realize the multi-path selector with priority.

However, the multiplexer with priority implemented in the above manner implements selection of priority by using a plurality of cascaded look-up tables LUT, and thus the circuit structure is complicated and logic confusion is likely to occur.

SUMMERY OF THE UTILITY MODEL

Embodiments of the present application provide a selection device applied to a multiplexer, a processor, a network-on-chip system, and a parallel computing system, so as to overcome at least some of the above problems.

In a first aspect, to achieve the above object, embodiments of the present application provide a selection device applied to a multiplexer for accessing m enable signals EN [ m-1: 0%]And n-way data D₀-D_n-1M enable signals are used for indicating the gating state of n paths of data, and m and n are positive integers larger than 1; the selection device comprises n selection units corresponding to the n paths of data one by one, wherein the input end of the jth selection unit is accessed to the jth path of data D_j-1The control end of the jth selection unit is used for accessing a control signal SEL [ j-1 ]]The control signal is used for controlling the selection unit to be in a gating state, wherein j is [1, n ]]And j is an integer, control signal SEL [ j-1 ]]According to gating priority higher than and equal to SEL_j-1Generating an enable signal corresponding to the data of (1); the output ends of the n selection units are connected with the output stage of the selection device.

Optionally, in any embodiment of the present application, the output ends of the n selection units are connected in parallel to implement a line and logic, and the output ends of the n parallel selection units are connected to the output stage of the selection device, so as to use the line and result as the output of the multiplexer.

Optionally, in any embodiment of the present application, the selecting unit includes: the control signal is used for controlling the tri-state gate to be in a high-impedance state so that the selection unit is in a non-gating state, or the control signal is used for controlling the tri-state gate to be in a non-high-impedance state so that the selection unit is in a gating state;

optionally, in any embodiment of the present application, the selecting unit includes: and the control signal is used for controlling the transmission gate to be disconnected so as to enable the selection unit to be in a non-gating state, or the control signal is used for controlling the transmission gate to be connected so as to enable the selection unit to be in a gating state.

Optionally, in any embodiment of the present application, the output stage of the selection device is a CMOS inverter.

In a second aspect, to achieve the above object, embodiments of the present application provide a multiplexer including the selection device as described above.

Optionally, in any embodiment of the present application, each of the n paths of data is divided into at least two paths of sub-data, so as to obtain at least two sub-data sets; the number of the selected devices is at least two, each group of the sub data sets is input into one of the selected devices, and at least two of the selected devices share one group of the control signals.

In a third aspect, to achieve the above object, an embodiment of the present application provides a processor, including the multiplexer as described above, and a control module, where the control module is configured to generate an enable signal and input the enable signal to the multiplexer.

In a fourth aspect, an embodiment of the present application provides an on-chip network system, including the multiplexer as described above.

In a fifth aspect, embodiments of the present application provide a parallel computing system comprising a multiplexer as described above.

The selection device provided in this embodiment is higher than and equal to the jth data D according to the gating priority_j-1Is generated according to the enable signal of the data generating control signal SEL [ j-1 ]]The control signals SEL [ n-1:0]And then the voltage is controlled by a control signal SEL [ n-1:0]Control and n-way data D₀-D_n-1Whether n corresponding selection units are in a gating state or not, wherein the output ends of the n selection units are connected with the output stage of the selection device, and after a certain selection unit is in the gating state, the input of the selection unit can be transmitted to the output stage of the selection device, so that the selection unit corresponding to n paths of data one by one is adopted, and one path of data can be directly selected from the n paths of data for output. The volume is more compact.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a multiplexer according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a controller in a multiplexer according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a controller in a 1-out-of-7 multiplexer according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a selection device in a multiplexer according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a selection device according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a selection device using tri-state gates according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a selection apparatus using a transmission gate according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of another multiplexer provided in the embodiment of the present application;

fig. 9 is a schematic structural diagram of a processor including a multiplexer according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 1 is a schematic structural diagram of a multiplexer according to an embodiment of the present disclosure.

As shown in FIG. 1, a multiplexer is used to access m enable signals EN [ m-1:0]]And n-way data D₀-D_n-1Wherein m enable signals are used for indicating n-way data D₀-D_n-1M, n is a positive integer greater than 1, n is less than or equal to 2^m。

As shown in fig. 1, the multiplexer includes a controller and a selection device.

In this embodiment, m enable signals EN [ m-1:0]]Can be input to a controller which can be used for controlling the output of the controller according to m enable signals EN [ m-1:0]Can output data D of n paths₀-D_n-1N control signals SEL [ n-1:0] in one-to-one correspondence]。

Specifically, the controller includes n logic gate circuit groups corresponding to the n data paths one by one.

Wherein, the i-th data D in the controller_i-1Corresponding toThe input end of the logic gate circuit group is connected with the data D with the gating priority higher than and equal to the ith path_i-1The output end outputs an enable signal for controlling the ith data D_i-1Control signal SEL [ i-1 ] of the gating state]，i＝[1， n]And i is an integer. Therefore, the logic gate circuit groups in the controller correspond to the n paths of data one to one, the enable signals input to each logic gate circuit group can be directly determined according to the truth table of the multi-path selector, and the control signal for indicating gating can be output only when the enable signals meet the output conditions of the logic gate circuit groups.

In the whole process, n control signals SEL [ n-1:0] output by the n logic gate circuit groups at least comprise n-1 control signals for controlling a certain path of data to be in a non-gating state, and 1 path of data is selected from the n paths of data to serve as the output of the multiplexer.

In this embodiment, the enable signal corresponding to a certain way of data refers to the enable signal used for indicating the gating state of the way of data in the m enable signals EN [ m-1:0 ].

n-way data D₀-D_n-1N control signals SEL [ n-1:0] input to the input of the selection means]Input to the control terminal of the selection device, wherein the control signal SEL [ j-1 ]]For controlling the j-th data D_j-1Is equal to [1, n ]]And j is an integer.

In this embodiment, i and j may be the same or different, and this embodiment does not limit this.

In this embodiment, the controller may directly output the control signal SEL [ n-1:0] corresponding to the n paths of data one by one, and the controller may directly select one path from the n paths of data to output through the control signal corresponding to the selection unit one by one, without performing logic judgment, thereby avoiding a logic disorder condition occurring when judging the priority.

Of course, in other implementation manners, the controller may have other structures as long as it can output the control signals corresponding to the n channels of data one by one according to the enable signal; alternatively, the selection device may have another configuration as long as it can perform selection in one-to-one correspondence with n-channel data, and this embodiment is not limited to this.

The controller in the multiplexer is explained in detail below.

Fig. 2 is a schematic structural diagram of a controller in a multiplexer according to an embodiment of the present disclosure.

Referring to fig. 2, the controller includes n logic gate circuit groups in one-to-one correspondence with n data.

Therein, with the ith path data D_i-1Corresponding logic gate circuit group for access gating with priority higher than and equal to D_i-1And outputs an enable signal for controlling D_i-1Control signal SEL [ i-1 ] of the gating state]，i＝[1，n]I is an integer;

the n control signals SEL [ n-1:0] output by the n logic gate circuit groups at least comprise n-1 control signals for controlling a certain path of data to be in a non-gating state, and 1 path of data is selected from the n paths of data to be used as the output of the multiplexer.

In this embodiment, how the control signal controls the gating of the corresponding path number data is not limited, and those skilled in the art may generate the control signal SEL [ n-1:0] corresponding to the selection unit in a one-to-one manner according to the m enable signals EN [ m-1:0] in any appropriate manner, for example, the control signal may directly control the switch gate circuit, so as to control the gating state of the corresponding path number data.

In this embodiment, when the multiplexer is configured, a truth table of the multiplexer is generally determined, and the truth table is a table for representing all possible states between the input and the output of the multiplexer. In this embodiment, the logic gate circuits included in each logic gate circuit group, the connection modes of the logic gate circuits, and the enable signals accessed by the logic gate circuit groups may be determined directly according to the truth table.

The logic gate circuit groups in the controller correspond to the n paths of data one to one, the enable signal input to each logic gate circuit group can be directly determined according to a truth table of the multi-path selector, and the control signal for indicating gating can be output when the enable signal meets the output condition of the logic gate circuit groups. Whole output control signal's process need not to carry out the logic and judges, and then the chaotic condition of logic has been avoided appearing, and, logic gate circuit group in the controller need simple logic gate circuit can output with the control signal of multichannel data one-to-one, when concrete use, can realize the multiplexer through a switch of every control signal control, compare with the multiplexer that present cooperation realization such as through look-up table LUT and D flip-flop, the structure of the multiplexer that the controller that adopts the embodiment of this application provided realized is simpler, and the volume is more small and exquisite.

In this embodiment, the enable signal corresponding to any path of data refers to an enable signal used for indicating a gating state of the path of data among the m enable signals.

In this embodiment, the numerical relationship between m and n is not limited, as long as the gating state of n-way data can be indicated by m enable signals, and any one-way data D in the n-way data is targeted_i-1In this application, according to the gating priority being higher than and equal to D_i-1Is generated for controlling D_i-1Control signal SEL [ i-1 ] of the gating state]Therefore, no logical confusion occurs. In addition, the gating state of one path of data may be indicated by one enable signal, or may be indicated by a plurality of enable signals, which is not limited in this embodiment.

Optionally, in this embodiment of the application, when i is greater than 1 and smaller than n, the ith channel of data D is accessed_i-1The corresponding logic gate circuit group comprises: inverter, and logic gate circuit.

And ith data D_i-1A corresponding logic gate circuit group, which accesses data D with higher priority than the ith path through the phase inverter_i-1The data of (2) corresponds to an enable signal; and, passing the ith data D through an AND logic gate circuit_i-1The corresponding enable signal and the output of the inverter are subjected to AND logic calculation, and the output is used for controlling the ith data D_i-1Control signal SEL [ i-1 ] of the gating state]. Thus, the priority can be higher than the ith data D_i-1Of whichThe enable signal corresponding to other data generates and outputs the I-th data D for controlling_i-1Control signal SEL [ i-1 ] of the gating state]. Thus, only if the priority is higher than D_i-1When none of the partial data is selected, D_i-1Will be the output of the multiplexer.

Optionally, in this embodiment of the application, the number of the enable signals is less than 1, that is, m is equal to n-1, than the number of lanes of the data, so as to pass m enable signals EN [ m-1:0 [ ]]And respectively indicating the gating state of the n-1 paths of data, and defaulting that the priority of one path of data except the n-1 paths of data is the lowest. Thus, gating priority higher than and equal to D can be directly set_j-1Access to the enabling signal of data one-to-one correspondence D_j-1Corresponding logic gate circuit group to generate D through the logic gate circuit group_j-1Corresponding control signal SEL [ j-1 ]]The structure of the circuit is simpler.

As shown in FIG. 2, the nth data D_n-1When the gating priority of (2) is lowest, and D_n-1The corresponding logic gate circuit group comprises: an inverter and an AND logic gate circuit; and D_n-1A corresponding logic gate circuit group with access priority higher than D through the phase inverter_n-1Other way data (D)₀-D_n-2) A corresponding enable signal; and performing AND logic calculation on the output of the inverter through an AND logic gate circuit, wherein the output is used for controlling D_n-1Control signal SEL [ n-1 ] of the gating state]。

In another embodiment of the present application, a 7-to-1 multiplexer is taken as an example, and a specific implementation of the multiplexer in the foregoing embodiment is exemplarily described.

For example, see table 1 below, which is a truth table of a 7-to-1 multiplexer, and see fig. 3 below, which is a schematic diagram of a circuit structure of a multiplexer corresponding to table 1.

In this embodiment, the input data of the multiplexer has 7 paths, which are respectively D₀-D₆，D₀-D₆Has a priority order of D₀>D₁>D₂>D₃>D₄>D₅>D₆。

Enable signal EN [ m-1:0]Is a total of 6 (EN [5:0]]) Respectively for indicating D₀-D₅When it is determined that the enable signal does not indicate D₀-D₅When any one path is conducted, the 7 th path gating signal D is determined₆On, Q ═ D₆. An "X" in the table indicates that the enable signal may be any value (1 or 0).

TABLE 1

Optionally, in this embodiment of the present application, i is 1, and the 1 st path of data D₀When the gating priority is highest, and D₀The corresponding logic gate circuit group comprises: buffer for accessing D₀Corresponding enable signal EN [ 0]]And output for controlling D₀Control signal SEL [ 0] of the gated state of]。

Optionally, in this embodiment of the present application, when i is 3, see fig. 3, the 3 rd path data D₂Gating priority of less than D₀And D₁。

In the controller with D₂The corresponding set of logic gates may comprise inverters and logic gates. Wherein, the phase inverter can include two, respectively connected to the enable signal EN [ 0]](priority higher than D)₂D of (A)₀Corresponding enable signal), EN [1 ]](priority higher than D)₂D of (A)₁Corresponding enable signal) and then EN 2 may be applied through an and logic gate]And EN [ 0] output of inverter]B、EN[1]B performs AND logic calculation to obtain control D₂Control signal SEL [ 2] of the gated state of]I.e. SEL [ 2]]＝EN[0]B&EN[1]B&EN[2]。

For example, when the enable signal EN [5:0]When xxxx 111, D is gated preferentially₀Instead of D₂I.e. the output Q ═ D of the multiplexer₀. When the enable signal EN [5:0]When xxx100, EN 0]B、 EN[1]B、EN[2]Are all equal to 1, SEL ₂1, the output Q of the multiplexer D₂。

When i is 1, 2, 4, and 5, the structure of the logic circuit group is similar to that of the logic circuit group when i is 3, and details thereof are not repeated.

Alternatively, in the embodiment of the present application, when i is 7, still referring to table 1 above, data D in the 7 th channel₆Of lowest priority, D₀-D₅Are all higher than D₆Then and D₆The corresponding logic gate circuit group comprises inverters and AND logic gate circuits, the number of the inverters can be 6, and the inverters are respectively connected with enable signals EN [5:0]Then, the outputs of the 6 inverters can be subjected to AND logic calculation through an AND logic gate circuit, and the outputs are used for controlling 7 th data D₆Control signal SEL [6 ] of the gated state of]。

In other implementations of the present application, with D₆The corresponding set of logic gates may include NOR gates, with enable signals EN [5:0]]Can be directly input into a NOR gate, and enable signals EN [5:0] are input through the NOR gate]Performing NOR logic calculation, outputting data D for controlling 7 th path₆Control signal SEL [6 ] of the gated state of]。

By way of example, and still referring to Table 1 above, one may pass through others (i.e., EN [5:0]]000000), represents D₆Strobing, i.e. defaulting to other way data (D)₀-D₅) When not gating, gating D₆。

Of course, the above description is merely illustrative and not restrictive of the present application. The scheme provided by the application can also be applied to other multiplexers.

For example, the scheme provided by this embodiment may also be applied to a 1-out-of-16 multiplexer.

The input data of the 16-to-1 multiplexer can comprise 16 paths, and then 4 paths of data can be divided into a small group to obtain 4 small groups; each two subgroups were divided into one large group, resulting in 2 large groups.

The enable signal of the 16-to-1 multiplexer may include 6, respectively EN [5:0], where EN [3:0] is used to indicate the gating state of the 4-way data in each subgroup, where the gating priority of the 4-way data in each subgroup is gradually decreased, EN [4] is used to indicate the gating state of the 2 subgroups in the major group, and EN [5] is used to indicate the gating state of the 2 major groups.

Therefore, the truth table corresponding to the 16-to-1 multiplexer can be determined, and the logic gate circuit group corresponding to each path of data one by one can be directly determined according to the truth table. The truth table can be determined by referring to the related art, and details thereof are not repeated herein.

For example, for the 2 nd data D in 16 ways₁It belongs to the first big group-first small group-2 data, and its priority is lower than the first big group-first small group-1 data. The enable signals may be EN [5:0] when the 2 nd way data is strobed]＝[0001XX]Wherein, EN [5]]0, indicating the first large group strobe; EN 4]0, indicating the first subgroup strobe in each large group; EN 3]0 indicates that way 1 in each subgroup is not gated; EN 2]1 indicates the 2 nd way strobe in each subgroup, and X indicates that the enable signal may be any value (0 or 1).

Then for way 2 data D₁The corresponding set of logic gates may include: three inverters and an and logic gate circuit.

Wherein, three phase inverters in the logic gate circuit group are respectively connected with enable signals EN [5:3 ]]Then AND logic gate circuit will EN [ 2]]And EN [3 ] of the inverter output]B、EN[4]B、EN[5]B performs AND logic calculation, obtains and outputs for controlling D₁Control signal SEL [1 ] of the gated state of]I.e. SEL [1 ]]＝EN[5]B&EN[4]B&EN[3]B&EN[2]。

The selection means in the multiplexer will be explained in detail below.

Referring to fig. 4, a selection device in a multiplexer provided in an embodiment of the present application is shown.

The selection device comprises n selection units corresponding to the n paths of data one by one, wherein the input end of the jth selection unit is connected with the jth data D_j-1The control end of the jth selection unit is used for accessing a control signal SEL [ j-1 ]]The control signal is used for controlling the selection unit to be in a gating state, wherein j is [1, n ]]And j is an integer, control signal SEL [ j-1 ]]According to the gating priority higher than and equal to the jth data D_j-1Enable signal generation corresponding to the data ofAnd the output ends of the n selection units are connected with the output stage of the selection device.

In this embodiment, how to generate the control signal is not limited, and those skilled in the art may generate the control signal SEL [ n-1: 0].

The selection device provided in this embodiment is higher than and equal to the jth data D according to the gating priority_j-1Is generated according to the enable signal of the data generating control signal SEL [ j-1 ]]The control signals SEL [ n-1:0]And then the output is controlled by n control signals SEL [ n-1:0]Control and n-way data D₀-D_n-1Whether n corresponding selection units are in a gating state or not, wherein the output ends of the n selection units are connected with the output stage of the selection device, and after a certain selection unit is in the gating state, the input of the selection unit can be transmitted to the output stage of the selection device, so that the selection unit corresponding to n paths of data one by one is adopted, and one path of data can be directly selected from the n paths of data for output. The volume is more compact.

In the present embodiment, as shown in fig. 4, a:0 in the middle brackets indicates that each path of data may include a +1 bit (bit) data. In addition, when a certain path of data (e.g. D shown in the figure)_cAnd c is 0, …, n-1), the structure of the selection unit can be as shown in fig. 5. The selection unit may comprise a plurality of sub-selection units, each sub-selection unit corresponding to a bit numberAccordingly.

Optionally, in this embodiment of the application, the n selection units at least include n-1 selection units in a non-gating state, so that the selection unit directly selects 1 channel of data from the n channels of data as an output of the multiplexer.

Optionally, in this embodiment, the output ends of the n selection units are connected in parallel to implement a line and logic, and the output ends of the n parallel selection units are connected to the output stage of the selection device, so as to use the line and result as the output of the multiplexer.

Wired-and, i.e., the function of an and logic computation is implemented by direct interconnection between two or more outputs. In hardware, open collector gates (OC gates) or tri-state gates (TS gates) are typically used to implement wired-and logic.

In this embodiment, the number of devices in the selection device can be reduced by combining the output lines of the plurality of selection units, thereby further reducing the volume of the selection device. In addition, when the wired-and is used, the selection unit may be any gate-on/off device supporting the wired-and, which is not limited in this embodiment.

Optionally, in this embodiment, the selection unit may include a tri-state gate or a transmission gate. Compared with other switching gates, the tri-state gate/transmission gate realizes better performance under the condition of smaller occupied area.

When the selection unit comprises a tri-state gate, the control signal is used for controlling the tri-state gate to be in a high impedance state so as to enable the selection unit to be in a non-gating state, or the control signal is used for controlling the tri-state gate to be in a non-high impedance state so as to enable the selection unit to be in a gating state.

Referring to fig. 6, a schematic diagram of a selection device using tri-state gates is shown.

The tri-state gate includes four MOS, PMOS1, PMOS2, NMOS3, and NMOS 4.

Wherein the S-pole (source) of PMOS1 is connected to the driving power supply, and the G-pole (gate) is connected to the data to be gated, such as D₁D pole (drain) is connected with S pole of PMOS2, G pole of PMOS2 is connected with reverse SELB, P of control signalThe D electrode of MOS2 is connected to the S electrode of NMOS3, the G electrode of NMOS3 is connected to control signal SEL, the D electrode of NMOS3 is connected to the S electrode of NMOS4, and the G electrode of NMOS4 is connected to gated data, such as D₁And the D pole of the NMOS4 is grounded.

Of course, the above description is only exemplary of the structure of the tri-state gate, and in other implementations, other tri-state gates may be adopted, which is also within the scope of the present application. For example, P1, P2, N1 and N2 of the tri-state gates shown in fig. 6 may be exchanged, and the exchanged tri-state gates are also within the scope of the present application.

For the selection unit corresponding to any path of data, when the selection unit is a three-state gate, if SEL_i-1If it is 0, the tri-state gate is in high impedance state, which is equivalent to open circuit, and the corresponding ith data D_i-1In an ungated state; if SEL is available_i-1If 1, the output and input of the tri-state gate are the same, and the corresponding ith data D_i-1Is in a gated state.

When the tri-state gate lines are AND, one of the tri-state gates is in a non-high impedance state (corresponding to the output of the selection device), and the rest are in a high impedance state.

In addition, when the tri-state gate shown in fig. 6 is used, the output stage of the selection device is a CMOS inverter in order to ensure that the output of the selection device coincides with the input.

Of course, fig. 6 is a schematic diagram illustrating the structure of a tri-state gate, and is not intended to limit the present application.

Optionally, in another implementation manner of the present application, when the selection unit includes a transmission gate, the control signal is used to control the transmission gate to be turned off so that the selection unit is in a non-gated state, or the control signal is used to control the transmission gate to be turned on so that the selection unit is in a gated state.

Referring to fig. 7, a schematic diagram of a selection device using transmission gates is shown.

As shown in fig. 7, each path of data may be accessed to the input end of the transmission gate through the CMOS inverter, and the control signal SEL and the inverse SELB of the control signal may be accessed to two control ends of the transmission gate, so as to control the on/off of the transmission gate through the control signal.

In addition, since each path of data is connected to the transmission gate through the CMOS inverter, in order to make the input and output consistent, the output stage of the selection device may be a CMOS inverter.

Because the plurality of selection units are directly connected with each other, when the selection units are tri-state gates or transmission gates, the driving capability of the selection units is weak, therefore, in this embodiment, the CMOS inverter is used as an output stage of the selection device, and besides ensuring that input and output are not inverted, external driving energy can be ensured through the CMOS inverter, and the CMOS inverter can shield interference of external signals to the selection device, especially interference to lines and nodes, and ensure the safety of signals inside the selection device.

It should be noted that the output stage of the selection device may not include a CMOS inverter, but may directly use QN as an output, which is also within the protection scope of the present application.

Referring to fig. 8, another multiplexer provided in the embodiments of the present application is shown.

In this embodiment, each of the n paths of data is divided into at least two paths of sub-data to obtain at least two sub-data sets; the number of the selected devices is at least two, each group of the sub data sets is input into one of the selected devices, and at least two of the selected devices share one group of the control signals.

Illustratively, as shown in FIG. 8, D₀-D₆And the data can be 64 bits, each path of data can be divided into two paths of sub data. For example, D₁Is divided into D₁[63：32]And D₁[31：0](i.e., a-63, b-32); or D₁Is divided into D₁[63：16]And D₁[15：0]. The present embodiment does not limit the specific dividing manner.

For example, as shown in fig. 8, when the multi-path data is divided into 2 sub-data, two sub-data groups may be obtained. The two sub-data sets are respectively the sub-data set corresponding to [63:32] and the sub-data set corresponding to [31:0 ]. The number of the selection devices is also two, and two sub data sets are input respectively. The two selection means share a set of said control signals output by a controller.

When the bit number (bit) of the multi-path data is higher, the scheme provided by the embodiment can output different bit numbers of one path of data through at least two selection devices respectively, so that the output of the path of data is completed.

Referring to fig. 9, an embodiment of the present application provides a processor.

As shown in fig. 9, the processor may include a multiplexer and a control module, and the control module is configured to generate m enable signals EN [ m-1:0] and input the m enable signals EN [ m-1:0] to the multiplexer.

In this embodiment, the processor may be any processor having a requirement for processing multiple paths of data, such as a central processing unit CPU, a graphics processing unit GPU, and the like, which is not limited in this embodiment.

In this embodiment, the n paths of data input to the multiplexer may be audio and video data streams or other data, which is not limited in this embodiment.

In this embodiment, the control module in the processor may generate an enable signal for controlling the gating state of the multi-channel data according to its own control logic.

Another embodiment of the present application provides an on-chip network system, which includes the above multiplexer.

Another embodiment of the present application provides a parallel computing system, which includes the multiplexer described above.

In this embodiment, if the parallel computing system generally includes a plurality of computing cores, and the plurality of computing cores perform parallel operations, the multiplexer may transmit the data with computation to the corresponding plurality of computing cores according to the priority order, and the plurality of computing cores perform parallel computations.

Similarly, the outputs of the plurality of computation cores may be used as multiple input data of a multiplexer, and the computation results of the parallel computation by the plurality of computation cores may be sequentially output by the multiplexer according to the priority order for subsequent use.

In the embodiments provided in the present application, it should be understood that the disclosed system and apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be separately processed, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. Selection device applied to multiplexer, characterized in that the multiplexer is used for accessing m enable signals EN [ m-1:0]]And n-way data D₀-D_n-1M enable signals are used for indicating the gating state of n paths of data, and m and n are positive integers larger than 1;

the selection device comprises n selection units corresponding to the n paths of data one by one, wherein the input end of the jth selection unit is connected with the jth data D_j-1The control end of the jth selection unit is used for accessing a control signal SEL [ j-1 ]]The control signal is used for controlling the selection unit to be in a gating state, wherein j is [1, n ]]And j is an integer, control signal SEL [ j-1 ]]According to gating priority higher than and equal to D_j-1Generating an enable signal corresponding to the data of (1);

the output ends of the n selection units are connected with the output stage of the selection device.

2. The selection device of claim 1, wherein the outputs of n of the selection units are connected in parallel to implement a wired-and logic, and the outputs of n of the parallel selection units are connected to the output stage of the selection device to take the wired-and result as the output of the multiplexer.

3. Selection device according to claim 1, characterized in that the selection unit comprises: and the control signal is used for controlling the tri-state gate to be in a high-impedance state so as to enable the selection unit to be in a non-gating state, or the control signal is used for controlling the tri-state gate to be in a non-high-impedance state so as to enable the selection unit to be in a gating state.

4. Selection device according to claim 1, characterized in that the selection unit comprises: and the control signal is used for controlling the transmission gate to be disconnected so as to enable the selection unit to be in a non-gating state, or the control signal is used for controlling the transmission gate to be connected so as to enable the selection unit to be in a gating state.

5. The selection device of claim 1, wherein the output stage of the selection device is a CMOS inverter.

6. A multiplexer, characterized in that it comprises a selection device according to any one of claims 1-5.

7. The multiplexer of claim 6, wherein each of the n data paths is divided into at least two sub-data paths to obtain at least two sub-data groups; the number of the selected devices is at least two, each group of the sub data sets is input into one of the selected devices, and at least two of the selected devices share one group of the control signals.

8. A processor comprising a multiplexer according to any one of claims 6 to 7 and a control module for generating an enable signal for input to the multiplexer.

9. A network-on-chip system comprising a multiplexer according to any one of claims 6-7.

10. A parallel computing system comprising a multiplexer according to any one of claims 6 to 7.