CN214154487U

CN214154487U - Analog-to-digital converter digital calibration circuit based on dynamic unit matching

Info

Publication number: CN214154487U
Application number: CN202022516086.7U
Authority: CN
Inventors: 马元君; 黄晶
Original assignee: Nanjing Derui Zhixin Electronic Technology Co ltd
Current assignee: Nanjing Derui Zhixin Electronic Technology Co ltd
Priority date: 2020-11-03
Filing date: 2020-11-03
Publication date: 2021-09-07
Anticipated expiration: 2030-11-03

Abstract

The invention relates to an analog-to-digital converter digital calibration circuit based on dynamic unit matching, which is mainly applied to a high-speed high-precision pipeline structure ADC. The circuit comprises a pseudo-random sequence generator, a DEM decoder, an LMS algorithm convergence module, a Booth multiplier and a DEM analog DAC circuit. The design of the patent relates to the technical field of integrated circuit design, in particular to an analog-to-digital converter with a pipeline structure, which is used for calibrating feedback errors caused by interstage gain errors and parasitic capacitance due to dynamic change of a working environment. The circuit algorithm utilizes some properties of signal non-correlation, signals are introduced into the analog domain circuit through the digital domain circuit, then the output signals of the analog domain are converged and extracted with error factors in the digital domain circuit, and finally corresponding compensation is carried out on the output signals by using a digital calculation method. The method aims to solve the problem of signal quantization errors caused by limited gain errors of parasitic capacitance feedback and interstage operational amplification of an ADC chip.

Description

Analog-to-digital converter digital calibration circuit based on dynamic unit matching

Technical Field

The invention relates to a calibration circuit, in particular to an analog-to-digital converter digital calibration circuit based on dynamic unit matching, and belongs to the technical field of integrated circuit design.

Background

An analog-to-Digital converter (ADC) is an analog-to-Digital converter (ADC) chip with a Digital circuit and an analog circuit inside, and is often designed due to the superiority of Pipeline ADC structure, but each stage in the Pipeline structure has a high requirement for operational amplifier, and under the severe working environment, the operational amplifier will have a large influence on the quantization of the next stage of the ADC if it is in a low-difference working state, and this phenomenon largely determines the performance of the chip. At present, high-speed ADC chips are widely used in electronic systems such as high-speed communication, radars and automation equipment, and the relative deviation of a certain degree exists between sampling capacitors due to the fact that the sampling capacitors work at high frequency, the process deviation and the environment temperature change. These non-ideal factors exist in each stage of pipeline module, especially the first stage module has the largest influence on the performance of the whole analog-to-digital converter, so that it is necessary to perform real-time calibration compensation on the output signal, so as to effectively improve the output performance of the signal. The method comprises the steps that a digital domain judges an operational point of an analog domain, a digital domain circuit generates a known signal, the known signal is converted into an analog signal through a related circuit, the analog signal is added into a quantization production line of the analog domain for quantization, a signal of an output structure caused by non-ideal operational amplification and feedback is sent into a rear stage for quantization to generate a corresponding error signal, the error signal is judged, and the analog domain is compensated in the digital domain to reduce errors caused by the conditions. Therefore, a new solution to solve the above technical problems is urgently needed.

Disclosure of Invention

The invention provides a digital calibration circuit of an analog-to-digital converter based on dynamic unit matching aiming at the problems in the prior art, and the technical scheme provides a method for solving quantization errors caused by parasitic capacitance feedback and interstage operational amplifier limited gain errors of an ADC chip, particularly when the chip works at a higher frequency. By using some properties of signal non-correlation, the performance and linearity of a digital output signal can be obviously improved by converging an error factor in a digital domain circuit and then correspondingly compensating a current signal in the digital circuit by a digital compensation method, and compared with a non-calibration circuit, the anti-interference performance and accuracy of a system can be improved.

In order to achieve the above object, according to the technical scheme of the present invention, the digital calibration circuit of the analog-to-digital converter based on dynamic unit matching comprises a pseudo-random sequence generator, a DEM decoder, an LMS algorithm convergence module, a Booth multiplier, and a DEM analog DAC circuit, wherein the digital domain circuit comprises a pseudo-random sequence generator, a DEM decoder, an LMS algorithm convergence module, and a Booth multiplier, the pseudo-random sequence circuit provides input for the DEM decoder, the LMS algorithm convergence module calls the Booth multiplier, and improves algorithm performance and speed, the analog domain circuit comprises a DEM analog DAC circuit, and the output of the DEM decoder is used as the input of the DEM decoder, and the output of the DEM decoder is used as the input of the LMS algorithm convergence module.

As an improvement of the invention, the pseudo-random series generator adopts a parallel linear feedback shift register structure and consists of twenty-three registers, and the initial state is circularly changed by adopting parallel linear feedback, so that the pseudo-random and the non-correlation of each bit data are improved.

As an improvement of the invention, the DEM decoder adopts an adder, an M sequence generator and an 1/2 circuit, four-bit binary data is decoded into random eight-bit thermometer codes, a 1/2 circuit is utilized to divide the four-bit binary data into two three-bit random numbers by taking a pseudo-random sequence as a switch, the three-bit binary data is divided into two-bit random numbers again, the two-bit binary data is divided into two one-bit random numbers again, and the two-bit random numbers are connected in a tree structure.

As an improvement of the invention, the LMS algorithm convergence module adopts a seven-stage pipeline structureThe method comprises two multipliers, two adders and a step length selection unit, wherein input ends of the two multipliers are input signals containing DEM quantized signals and digital DEM signals, the input ends of the two adders and the step length selection unit are respectively provided with a minimum mean square algorithm convergence circuit realized by the adders and the multipliers through non-correlation signal characteristics, and the convergence formula is omega_i+1＝ω_i–u*d(k)(ω_id (k) -y (k), converging the error factor to obtain a convergence value, wherein d (k) is a convergence expected value, y (k) is an actual training value, u is a convergence step length, and ω is_iFor error factors needing convergence, the convergence characteristic of the LMS algorithm is utilized, and meanwhile, the convergence step length can be adjusted to respond to the change precision, for example, a long step length can be selected when the chip is ideally adjusted during working, the convergence time is prolonged, and the real-time compensation is improved; otherwise, selecting short step length and improving the precision value.

As an improvement of the invention, the DEM analog DAC circuit is added with eight quantization capacitors with the same weight, the capacitor switch is controlled by the DEM signal output of the digital circuit, the digital DEM signal is converted into the analog DEM signal, the analog DEM signal is mixed into the first-stage output of the ADC pipeline, the non-ideality of a device is uniformly balanced, the noise caused by the non-ideality is reduced, the input of an LMS algorithm is optimized, the speed of convergence caused by larger errors is prevented, and meanwhile, the uniform noise input has the function of directly balancing the convergence, and the problem of non-convergence is reduced.

As an improvement of the invention, the LMS algorithm structure is based on specific precision requirement and convergence time, in the implementation of the LMS algorithm, a step value controllable circuit is added, the convergence speed can be modified by writing in corresponding registers through a chip communication module, the convergence speed range is 0-16 times, and the convergence precision and speed can be selected in a compromise mode according to specific chip working environment.

As an improvement of the invention, the circuit calibration circuit flow starts a digital domain calibration module through a control bit, a digital domain DEM signal is output to an analog domain, the DEM digital signal is converted into a DEM analog signal and added into an input signal of the analog domain, finally the analog signal with the DEM is quantized, the quantized digital signal is input to the digital domain again, the step length and the related setting are selected, a convergence circuit is started to converge the error factor, and the digital compensation is carried out on the input signal through a compensation circuit.

As an improvement of the invention, the pseudo-random sequence is generated in a digital domain circuit, then passes through an analog domain, acts on the analog domain, and finally is sent back to the digital domain circuit, and meanwhile, the jitter signal is eliminated in the digital domain.

Compared with the prior art, the digital calibration circuit has the advantages that the digital calibration circuit is ingenious in overall structural design, error factors caused by an operational amplifier, parasitic capacitance and the like due to external environment changes can be monitored in real time by calibrating the analog circuit through the digital circuit, corresponding digital compensation is completed on quantized analog signals according to actual error factor coefficients, on the basis of the original diter function, the characteristic of data non-correlation is ingeniously adopted, the mode of summing and averaging is carried out, the convergence of an LMS algorithm is utilized, and small hardware overhead is adopted to complete real-time digital calibration. Simultaneously, DEM structure corresponding structures are added in a digital domain and an analog domain, so that the possibility of convergence errors caused by larger noise due to accidental factors in convergence is further optimized. In the design, a parallel LFSR structure is adopted to generate random numbers, the randomness of output signals is improved, and the utilization rate of hardware resources is increased by simultaneously multiplexing the results in a DEM structure. In addition, the LMS algorithm adopts an adjustable step length, and can better complete real-time digital compensation on an output signal.

Drawings

FIG. 1 is a diagram of a digital circuit in relation to an analog circuit;

FIG. 2 is a circuit configuration for generating an error in an analog circuit;

FIG. 3 is an analog circuit DEM structure;

FIG. 4 is a digital DEM structure;

FIG. 5 is the generation of a pn sequence;

FIG. 6 is a structure of the LMS algorithm;

figure 7 is a LMS algorithm pipeline structure.

The specific implementation mode is as follows:

for the purpose of enhancing an understanding of the present invention, the present embodiment will be described in detail below with reference to the accompanying drawings.

Example 1: referring to fig. 1, a digital calibration circuit of an analog-to-digital converter based on dynamic cell matching, the technical scheme is that a ten-bit Dither Dither signal is injected through a digital module, an analog domain is mixed with a white noise signal, the design can effectively improve quantization noise of the signal and differential nonlinearity of a transfer function, the Dither Dither signal is converted through a sub-DAC and added into a first-stage residual signal, the residual signal containing the Dither signal is subjected to operational amplification of various stages with the residual signal of an original signal, sampling, comparator quantization, a subsequent Pipeline structure and the like are carried out, and finally a quantized signal result is output to the digital circuit. The difference is that the processed analog circuit output signal contains the known diter signal, the change value Delta of the jitter signal is tracked through convergence operation to obtain the corresponding error factor, the compensation value of the original signal is calculated through the error factor, and real-time error compensation is carried out in a digital domain.

The method is characterized in that algorithm calibration is added into a digital domain circuit, the error factor is solved, an LMS algorithm (least mean square algorithm) is adopted in design and is an improved algorithm of a steepest descent algorithm, further optimization extension of the steepest descent method is applied, the structure is simple, the realization is easy, only input vectors are needed to be used in each iteration and expectation is needed to correspond, although the LMS convergence speed is slow, because the structure is simple, the arithmetic logic units are relatively few, a large amount of hardware resources can be saved in the design, and the LMS algorithm is adopted in the design to converge the error factor.

The common Dither jitter injection circuit is an exponential multiplication addition for the weight of each bit, and if the lowest bit represents 8 LSBs and the next lowest bit is 16 LSBs, the weights are sequentially increased in multiples. The modified DEM structure is a circuit which changes the jittering low 4-bit equal-ratio weight into 8-bit equal-weight, and is made into a mixed weight circuit structure with the same low DEM weight and different high-order weights, so that the capacitance error can be averaged more effectively, and the 4-bit capacitance error is averaged on an 8-bit capacitor.

The design of the pseudo-random sequence in the digital circuit adopts a cyclic seed pseudo-random sequence, and each bit of the pseudo-random sequence is guaranteed to be irrelevant, which is also the basis for the digital circuit to calibrate the analog circuit. By utilizing the uncorrelated characteristic of noise and input signals, the energy tends to zero after the operation steps of correlation, accumulation and averaging. By using the autocorrelation of the random sequence, the energy tends to the average value of the self energy after the autocorrelation, accumulation and averaging steps are carried out on the random sequence. By using this principle, the error factor can be extracted. The output signal of the analog domain quantization is compensated by an error factor, the error is mainly concentrated in the residual output of the first stage of the PipelineADC, and the compensation of the whole analog quantization error is realized by compensating the quantity by a digital domain circuit.

The period of the pseudo-random sequence in the design of the pseudo-random sequence is 2^23-1, the design of a circularly changed transfer matrix is adopted, the complexity and the higher randomness of the pseudo-random sequence can be improved, the design has the advantages that each bit is irrelevant, meanwhile, the design can be matched with an LMS algorithm to carry out more effective convergence operation, in addition, the last 4 bits of the pseudo-random number are subjected to DEM design, the periodicity is further improved, the randomness of the pseudo-random sequence is further enhanced, and the noise problem caused by low bits can be better averaged.

The pseudo-random sequence is generated in a digital domain circuit, then acts on an analog domain through the analog domain, and finally is sent back to the digital domain circuit, meanwhile, a dither signal is eliminated in the digital domain, the structure can indirectly calibrate the capacitance of the analog domain, track the digital coding change, correspondingly compensate the digital coding change, compensate the quantization error of the analog domain caused by the error of the device, and the quantization error of the analog domain caused by the mismatch of the device can be greatly reduced through the structure that the digital circuit and the analog circuit are mutually interwoven, and in addition, the dither signal balances the action of the mismatch error of the device.

The specific embodiment is as follows: a digital calibration circuit of an analog-to-digital converter based on dynamic unit matching is disclosed, as shown in figure 1, the digital calibration circuit is a mutual relation between a digital domain circuit and an analog domain circuit of an ADC chip, the analog domain circuit provides input for the digital domain circuit through quantization of each stage, the digital domain circuit provides an environment for the analog domain to work at an optimal working point, and a dithering signal with a DEM structure is input, so that the analog domain circuit can average self noise on one hand, on the other hand, an error factor coefficient of the analog circuit is converged through an LMS algorithm of the digital domain circuit, and the obtained error factor coefficient is further used for compensating the caused error in real time.

Referring to fig. 2, in a first stage of the analog circuit, after the input signal passes through the sampling capacitor, quantizing in Sub-ADC, converting the quantized signal into analog DEM signal via Sub-DAC, removing the quantized signal from the original signal, converting into the residual signal, adding specific Dither digital input signal with DEM structure, mixing the Dither signal into the residual signal, the node signal passes through an operational amplifier after the follow-up, then the amplified signal is sent to a post-stage ADC pipeline, the Dither signal and the residual signal of the structure are transmitted through a consistent data path, and finally the quantized result is transmitted into a digital domain circuit, the first-stage operational amplifier of the structure is changed due to the external environment in the actual work, may operate in an undesired operating state, and therefore has a problem due to a limited open loop gain, etc. The same error also exists in the digitally generated Dither signal due to the same path, and the fact that the Dither signal is used for calibrating the error is the central idea of the design. The design mixes the known Dither signal with DEM signal before the signal enters the operational amplifier, the actual DEM signal also belongs to a part of the Dither signal, the signal is a pseudo-random sequence generated by a digital domain circuit, each bit of data has non-correlation mutually, and the basis of solving the factor of gain error is also provided.

As shown in fig. 3, the analog circuit DEM structure is an analog circuit DEM structure, which actually reduces the influence of noise on the analog circuit, and converts the low 4-bit signals with weights of 4:2:1:1 of the diter signal into random signals with weights of all 1, so that the average error values of mismatched components are approximately equal due to the connection relationship of the components, thereby reducing the influence of the mismatch of the components on the system performance. The technology is often used for reducing the influence of unit element mismatch on the performance of the Sub _ DAC and reducing the noise influence caused by noise and components. DTH [7:0] is an equally weighted pseudorandom signal, and DTH [14:8] is an equally weighted pseudorandom signal. And the analog quantity is converted into an analog quantity by controlling a capacitor switch of the comparator and is injected into a residual signal of a first stage of Pipeline.

As shown in fig. 4, a DEM signal framework diagram is shown for generating equal weights in the digital domain circuitry. The design of a 4-bit binary DEM decoder is completed by adopting a completely random DEM structure, a symmetrical five-level pipeline framework is adopted in the structure, and the decoder comprises three basic modules: the adder, the M sequence generator and the 1/2 circuit have simple structure, small occupied resource and easy realization, and the M sequence generator generates a pseudo-random sequence to play a random control bit of the whole mechanism.

As shown in FIG. 5, it is a block diagram of an M sequence generator, which employs a circuit structure of a twenty-three bit Linear Feedback Shift Register (LFSR) with a period of 2²³-1, in addition to improving the random nature of the pseudo random number, a parallel LFSR structure is used, the latest sequence being obtained by constantly changing the state of the initial state, which structure makes each bit non-coherent and each bit has a period of 2²³-1. And resource multiplexing for producing DEM output in fig. 4.

As shown in fig. 6, the LMS algorithm is a structural block diagram of the LMS algorithm, the LMS algorithm is a core module of a calibration method, when infinite iteration is performed, a filter weight vector reaches an optimal value or is in a small near field, an error factor coefficient is used as an optimal value required by the algorithm by using the characteristic of convergence of an algorithm coefficient, a digital signal of the DEM and a signal after quantization sent into an analog field are input into the algorithm, accumulation is performed according to the non-correlation between an analog input quantity and the DEM signal, and an optimal solution of the error factor coefficient is obtained by using the LMS algorithm.

As shown in fig. 7, a pipeline structure block diagram is established for the LMS algorithm structure, the implementation of the algorithm adopts a pipeline structure design, a 3-order Booth multiplier is adopted as a multiplier involved in the algorithm, signed bit operation can be completed at high speed and low power consumption, and the 3-order Booth multiplier is a multiplier with a pipeline structure, so that the implementation is facilitated in the design, and the operation rate is increased.

It should be noted that the above-mentioned embodiments are not intended to limit the scope of the present invention, and all equivalent modifications and substitutions based on the above-mentioned technical solutions are within the scope of the present invention as defined in the claims.

Claims

1. A digital calibration circuit of an analog-to-digital converter based on dynamic unit matching is characterized in that the calibration circuit comprises a pseudo-random sequence generator, a DEM decoder, an LMS algorithm convergence module, a Booth multiplier and a DEM analog DAC circuit, a digital domain circuit comprises the pseudo-random sequence generator, the DEM decoder, the LMS algorithm convergence module and the Booth multiplier, the pseudo-random sequence circuit provides input for the DEM decoder, the LMS algorithm convergence module calls the Booth multiplier to improve algorithm performance and speed, the analog domain circuit comprises the DEM analog DAC circuit, the output of the DEM decoder serves as the input of the DEM decoder, and the output of the DEM decoder serves as the input of the LMS algorithm convergence module.

2. The digital calibration circuit of analog-to-digital converter based on dynamic cell matching as claimed in claim 1, wherein the pseudo-random series generator adopts a parallel linear feedback shift register structure, which is composed of twenty-three registers, and the initial state is cyclically changed by adopting parallel linear feedback.

3. The dynamic cell matching based digital calibration circuit for analog-to-digital converters of claim 2, wherein said DEM decoder employs an adder, an M-sequencer and an 1/2 circuit to decode four-bit binary data into random eight-bit thermometer codes, a 1/2 circuit is used to divide the four-bit binary data into two three-bit random numbers, divide the three-bit binary data into two-bit random numbers again, and divide the two-bit binary data into two one-bit random numbers again, connected in a tree structure, by using a pseudo-random sequence as a switch.

4. The digital calibration circuit of the analog-to-digital converter based on the dynamic unit matching as claimed in claim 3, wherein the LMS algorithm convergence module is implemented by adopting a seven-stage pipeline structure, and comprises two multipliers, two adders and a step length selection unit, and the input ends are an input signal containing a DEM quantization signal and a digital DEM signal.

5. The analog-to-digital converter digital calibration circuit based on dynamic unit matching as claimed in claim 3 or 4, characterized in that the DEM analog DAC circuit is added with eight quantization capacitors with the same weight, the capacitance switch is controlled by the digital circuit DEM signal output, the digital DEM signal is converted into an analog DEM signal, and the analog DEM signal is mixed into the first stage output of the ADC pipeline.