CN214151689U - AXI bus structure and chip system - Google Patents
AXI bus structure and chip system Download PDFInfo
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- CN214151689U CN214151689U CN202022984797.7U CN202022984797U CN214151689U CN 214151689 U CN214151689 U CN 214151689U CN 202022984797 U CN202022984797 U CN 202022984797U CN 214151689 U CN214151689 U CN 214151689U
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Abstract
The utility model provides an AXI bus structure and chip system. The AXI bus structure includes: at least two main functional unit groups, each main functional unit group comprising at least two main functional units; at least two first routing units, at least two main function unit groups correspond to the at least two first routing units one by one, and each first routing unit is connected with each main function unit corresponding to the main function unit group through an AXI bus; at least two second routing units, each second routing unit and each first routing unit being connected via an AXI bus, respectively; each slave function unit group comprises at least two second slave function units, the at least two slave function unit groups correspond to at least two second routing units one by one, and each second routing unit is connected with each slave function unit corresponding to the slave function unit group through an AXI bus respectively.
Description
Technical Field
The application relates to the technical field of chips, in particular to an AXI bus structure and a chip system.
Background
The On-Chip interconnection bus (Network On Chip) refers to the connection relationship between systems or modules in a Chip, and is mainly used for realizing data exchange between subsystems or functional modules in the Chip. In AI processing chips, the enormous data throughput requirements present many challenges to on-chip interconnect bus design. For example, in a multi-core NPU (Neural network Processing Unit), bandwidth requirements for data interaction between multiple cores and data interaction with an OCM (On chip memory) are huge. In order to support high bandwidth, the clock frequency is high, and the bus bit width is large, which becomes the basic characteristics of the interconnection bus on the AI processor chip. Meanwhile, the number of lines of the interconnection bus starts to become huge due to the multi-core, and a serious congestion problem is brought to the realization of the back end of the chip.
SUMMERY OF THE UTILITY MODEL
An object of the embodiments of the present application is to provide an AXI bus structure and a chip system, which can reduce the number of interconnected AXI buses and eliminate congestion problem realized at the back end of a chip.
An embodiment of the present application provides an AXI bus structure, including:
at least two main functional unit groups, each main functional unit group comprising at least two main functional units;
at least two first routing units, wherein the at least two master function unit groups correspond to the at least two first routing units one by one, and each first routing unit is connected with each master function unit corresponding to the master function unit group through an AXI bus;
at least two second routing units, each of the second routing units being connected to each of the first routing units via an AXI bus, respectively;
each slave function unit group comprises at least two second slave function units, the at least two slave function unit groups correspond to the at least two second routing units one by one, and each second routing unit is connected with each slave function unit corresponding to the slave function unit group through an AXI bus respectively.
Optionally, in the AXI bus structure described in this embodiment of the application, each first routing unit includes at least two first routing nodes sequentially connected through an AXI bus, and each second routing unit includes at least two second routing nodes sequentially connected through an AXI bus;
at least two second routing nodes of each second routing unit are in one-to-one correspondence with the at least two first routing units, and each second routing node is connected with one first routing node corresponding to the first routing unit through an AXI bus.
Optionally, in the AXI bus structure according to this embodiment of the present application, each of the first routing nodes is connected to at least one of the second routing nodes.
Optionally, in the AXI bus structure according to this embodiment of the application, the number of first routing nodes of the first routing unit is different from the number of second routing nodes in each of the second routing units.
Optionally, in the AXI bus structure described in this embodiment of the present application, the AXI bus includes a write address/data channel, a read address channel, a read data channel, and a write acknowledge channel;
each of the first routing nodes includes: the first downlink sub-node is positioned on a write address/data channel, the second downlink sub-node is positioned on a read address channel, the first uplink sub-node is positioned on a read data channel, and the second uplink sub-node is positioned on a write response channel;
in the same first routing unit, first downlink sub-nodes of the at least two first routing nodes are connected in sequence, second downlink sub-nodes of the at least two first routing nodes are connected in sequence, first uplink sub-nodes of the at least two first routing nodes are connected in sequence, and second uplink sub-nodes of the at least two first routing nodes are connected in sequence;
and one end of each of the first downlink sub-node, the second downlink sub-node, the first uplink sub-node and the second uplink sub-node is connected with the corresponding main function unit, and the other end of each of the first downlink sub-node, the second downlink sub-node, the first uplink sub-node and the second uplink sub-node is connected with the corresponding second routing node.
Optionally, in the AXI bus structure according to this embodiment of the present application, each of the second routing nodes includes: the third downlink sub-node is positioned on the write address/data channel, the fourth downlink sub-node is positioned on the read address channel, the third uplink sub-node is positioned on the read data channel, and the fourth uplink sub-node is positioned on the write response channel;
in the same second routing unit, the third downlink sub-nodes of the at least two second routing nodes are sequentially connected, the fourth downlink sub-nodes of the at least two second routing nodes are sequentially connected, the third uplink sub-nodes of the at least two second routing nodes are sequentially connected, and the third downlink sub-nodes of the at least two second routing nodes are sequentially connected;
the input end of the third downlink sub-node is connected with the output end of the first downlink sub-node, the input end of the fourth downlink sub-node is connected with the output end of the second downlink sub-node, one end of the third uplink sub-node is connected with the first uplink sub-node, and the other end of the fourth uplink sub-node is connected with the second uplink sub-node; and the other ends of the third downlink sub-node, the fourth downlink sub-node, the third uplink sub-node and the fourth uplink sub-node are respectively connected with the corresponding slave functional units.
Optionally, in the AXI bus structure according to this embodiment of the present application, the first preset child node includes a master demultiplexer and a master arbiter;
the main multi-way distributor is used for accessing information sent by other nodes connected with the main multi-way distributor and sending the information to the main arbiter or another other node connected with the main arbiter;
the master arbiter is used for receiving the information sent by the demultiplexer or the information sent by other first preset child nodes and outputting the information to other nodes connected with the master arbiter;
the node type of the first preset child node is as follows: the node comprises a first uplink sub-node, a first downlink sub-node, a second uplink sub-node, a second downlink sub-node, a third uplink sub-node, a third downlink sub-node, a fourth uplink sub-node or a fourth downlink sub-node, and the number of the same type of first preset sub-nodes connected with the first preset sub-node is one.
Optionally, in the AXI bus structure according to this embodiment of the present application, the second preset child node includes a master demultiplexer, a master arbiter, a bypass demultiplexer, and a bypass arbiter;
the main demultiplexer is used for accessing information sent by other nodes connected with the main demultiplexer and sending the information to the main arbiter, the bypass arbiter and/or another other node connected with the main arbiter;
the master arbiter is used for receiving the information sent by the demultiplexer, the information sent by the bypass demultiplexer and/or other child nodes, and outputting the information to the nodes connected with the master arbiter;
the bypass multi-way distributor is used for accessing information sent by other nodes connected with the bypass multi-way distributor and sending the information to the main arbiter or the bypass arbiter;
the bypass arbiter is used for accessing the information sent by the main demultiplexer and the bypass demultiplexer and sending the information to other nodes connected with the bypass arbiter;
the node type of the second preset child node is as follows: the node comprises a first uplink sub-node, a first downlink sub-node, a second uplink sub-node, a second downlink sub-node, a third uplink sub-node, a third downlink sub-node, a fourth uplink sub-node or a fourth downlink sub-node, and the number of the same type of second preset sub-nodes connected with the second preset sub-node is at least two.
Optionally, in the AXI bus structure according to this embodiment of the present application, the main functional unit is a processor, an accelerator, a coprocessor, or a DMA controller.
Optionally, in the AXI bus structure according to this embodiment of the application, the slave function unit group is a memory, and the slave function unit is one storage unit of the memory.
Optionally, in the AXI bus structure according to this embodiment of the application, different first routing nodes are configured with different numbers of FIFO, and the depths of the FIFO on the different first routing nodes are different.
Optionally, in the AXI bus structure according to the embodiment of the present application, different second routing nodes are configured with different numbers of first-in first-out queues FIFO, and depths of the first-in first-out queues FIFO on the different second routing nodes are different.
In a second aspect, an embodiment of the present application further provides a chip system, including any one of the AXI bus structures described above.
As can be seen from the above, in the AXI bus structure provided in this embodiment of the application, the multiple master function units are divided into one group, the multiple slave function units are divided into one group, and the multiple master function units in the group share one routing network formed by the multiple first routing units to interact with the routing network formed by the multiple second routing units, so as to access each slave function unit, reduce the number of interconnected AXI buses, and eliminate the congestion problem realized at the back end of the chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic diagram of an AXI bus structure in some embodiments of the present application.
Fig. 2 is a schematic diagram of a first predetermined child node of an AXI bus structure in some embodiments of the present application.
Fig. 3 is a schematic diagram of a first connection structure of a first predetermined child node of an AXI bus structure in some embodiments of the present application.
Fig. 4 is a schematic diagram of a first connection structure of a first predetermined child node and a second predetermined child node of an AXI bus structure in some embodiments of the present application.
Fig. 5 is a schematic diagram of a second connection structure of a first predetermined child node and a second predetermined child node of an AXI bus structure in some embodiments of the present application.
Fig. 6 is a diagram of a sub-node connection structure for one channel of an AXI bus structure in some embodiments of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In the description of the present application, it should be noted that the terms "inside", "outside", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, and are only used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements that are referred to must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
It should also be noted that, unless expressly stated or limited otherwise, the terms "disposed" and "connected" are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an AXI bus structure in some embodiments of the present application.
Wherein the AXI bus structure includes: at least two master functional unit groups 10, at least two first routing units 20, at least two second routing units 30, and at least two slave functional unit groups 40.
Wherein each main functional unit group 10 includes at least two main functional units 11. The at least two master function unit groups 10 correspond to the at least two first routing units 20 one to one, and each first routing unit 20 is connected to each master function unit 11 of the corresponding master function unit group 10 through an AXI bus 100. Each second routing unit 30 is connected to each first routing unit 20 via an AXI bus 100; each slave function unit group 40 includes at least two second slave function units 41, the at least two slave function unit groups 40 are in one-to-one correspondence with the at least two second routing units 30, and each second routing unit 30 is connected to each slave function unit 41 of the corresponding slave function unit group 40 through an AXI bus 100, respectively.
In some embodiments, the main functional units 11 of each main functional unit group 10 may be different functional units, or may be the same functional unit. For example, the main functional unit 11 may be a processor, a dma (direct Memory access) controller, a Network Processor (NPU), or the like, but is not limited thereto. The number of the main functional units 11 in each main functional unit group 10 may be 3, 4, or other numbers. The number of the main functional unit groups 10 is 2 in this embodiment, but may be other numbers. In the present embodiment, there are a total of two main functional unit groups 10, one main functional unit group 10 including 3 main functional units 11, and the other main functional unit group 10 including 4 main functional units 11.
In some embodiments, the first routing unit 20 comprises at least two first routing nodes 21, which may be, for example, 2, 3, or more than 3. Wherein the at least two first routing nodes 21 are connected in sequence. Of course, in some embodiments, the at least two first routing nodes 21 may also adopt other connection modes, such as a star connection and the like.
Wherein, the at least two first routing nodes 21 may be connected with the at least two main functional units 11 of the corresponding main functional unit group 10 in a one-to-one correspondence; of course, there may not be a one-to-one correspondence, for example, the number of first routing nodes 21 may be greater than the number of main functional units 11 of the corresponding main functional unit group 10. Or the number of first routing nodes 21 may be larger than the number of main functional units 11 of the corresponding main functional unit group 10, in which case some first routing nodes 21 are to connect two or more main functional units 11.
The second routing unit 30 includes at least two second routing nodes 31, for example, 2, 3, or more than 3. The at least two second routing nodes 31 are connected in sequence. Of course, in some embodiments, the at least two second routing nodes 31 may also adopt other connection modes, for example, a star connection, and the like.
The at least two second routing nodes 31 of the second routing unit 30 and the at least two slave functional units 11 may be connected in a one-to-one correspondence, that is, the number of the second routing nodes 31 of the second routing unit 30 is equal to the number of the slave functional units 11 of the corresponding slave functional unit group 10. Of course, the at least two second routing nodes 31 of the second routing unit 30 may or may not correspond to the at least two slave functional units 11 one by one, for example, the number of the second routing nodes 31 may be greater than the number of the slave functional units 41 corresponding to the slave functional unit group 40.
At least two second routing nodes 31 of each second routing unit 30 correspond to the at least two first routing units 20 one by one, and each second routing node 31 is connected to one first routing node 21 of the corresponding first routing unit 20. As shown in fig. 1, the number of the second routing nodes 31 of each second routing unit 30 is two, and correspondingly, the number of the first routing units 20 is two; of course, it is not limited thereto.
In some embodiments, the slave functional unit group 40 includes at least two slave functional units 41, and at least two slave functional units 41 of each slave functional unit group 40 are connected to at least two second routing nodes 31 of the corresponding second routing unit 30 in a one-to-one correspondence manner, that is, the number of slave functional units 41 of each slave functional unit group 40 is equal to the number of second routing nodes 31 of the corresponding second routing unit 30. Of course, the number of slave functional units 41 of different slave functional unit groups 40 may be equal or may not be equal.
The at least two slave functional unit groups 40 may be subordinate to the same memory or a plurality of memories, and each slave functional unit 41 is a storage unit of the memory.
In some embodiments, the AXI bus 100 includes a write address/data channel, a read address channel, a read data channel, and a write acknowledge channel.
Each of the first routing nodes 21 and each of the second routing nodes 31 include four sub-nodes, and the four sub-nodes respectively correspond to a write address/data channel, a read address channel, a read data channel, and a write response channel one to one.
Specifically, the first routing node 21 includes: the first downlink sub-node is positioned on a write address/data channel, the second downlink sub-node is positioned on a read address channel, the first uplink sub-node is positioned on a read data channel, and the second uplink sub-node is positioned on a write response channel; in the same first routing unit, first downlink sub-nodes of the at least two first routing nodes are connected in sequence, second downlink sub-nodes of the at least two first routing nodes are connected in sequence, first uplink sub-nodes of the at least two first routing nodes are connected in sequence, and second uplink sub-nodes of the at least two first routing nodes are connected in sequence; in the same first routing unit, the first downlink sub-nodes of the at least two first routing nodes may be sequentially cascaded, or may also be interconnected in pairs, or may adopt other star-shaped connection manners, and of course, the sequential cascading is optimal. Of course, the second downlink sub-nodes in the same first routing unit may be sequentially cascaded, or may also be interconnected two by two, or may adopt other star connection manners, and of course, the sequential cascading is the best. The second uplink sub-nodes in the same first routing unit may be sequentially cascaded, or may also be interconnected in pairs, or may adopt other star-type connection manners, and of course, the sequential cascading is optimal. The second downlink sub-nodes in the same first routing unit may be cascaded in sequence, or may also be interconnected in pairs, or may adopt other star-type connection manners, and certainly, the cascade connection is optimal.
One end of each of the first downlink sub-node, the second downlink sub-node, the first uplink sub-node, and the second uplink sub-node is connected to the corresponding main function unit 11, and the other end of each of the first downlink sub-node, the second downlink sub-node, the first uplink sub-node, and the second uplink sub-node is connected to the corresponding second routing node 31. Specifically, the input ends of the first downlink sub-node and the second downlink sub-node are connected to the main function unit, and the inputs of the first downlink sub-node and the second downlink sub-node are connected to the corresponding second routing node. The input ends of the first uplink sub-node and the second uplink sub-node are connected with the second routing node, and the output ends of the first uplink sub-node and the second uplink sub-node are connected with the main function unit.
Specifically, each second routing node 31 includes: the third downlink sub-node is positioned on the write address/data channel, the fourth downlink sub-node is positioned on the read address channel, the third uplink sub-node is positioned on the read data channel, and the fourth uplink sub-node is positioned on the write response channel; in the same second routing unit, the third downlink sub-nodes of the at least two second routing nodes are sequentially connected, the fourth downlink sub-nodes of the at least two second routing nodes are sequentially connected, the third uplink sub-nodes of the at least two second routing nodes are sequentially connected, and the third downlink sub-nodes of the at least two second routing nodes are sequentially connected. In the same second routing unit, the third downlink sub-nodes of the at least two second routing nodes may be sequentially cascaded, or may also be interconnected two by two, or may adopt other star-shaped connection manners, and of course, the sequential cascading is optimal. Of course, the third uplink sub-nodes in the same second routing unit may be sequentially cascaded, or may also be interconnected two by two, or may adopt other star connection manners, and of course, the sequential cascading is optimal. The fourth uplink sub-nodes in the same second routing unit may be sequentially cascaded, or may also be interconnected two by two, or may adopt other star connection modes, and of course, the sequential cascading is optimal. The fourth downlink sub-nodes in the same second routing unit may be cascaded in sequence, or may also be interconnected two by two, or may adopt other star-type connection manners, and certainly, the fourth downlink sub-nodes are cascaded in sequence as the best.
One end of the third downlink sub-node is connected with the output end of the first downlink sub-node, one end of the fourth downlink sub-node is connected with the output end of the second downlink sub-node, one end of the third uplink sub-node is connected with the input ends of the first uplink sub-node and the second uplink sub-node, and one end of the fourth uplink sub-node is connected with the input end of the second uplink sub-node; the other ends of the third downlink sub-node, the fourth downlink sub-node, the third uplink sub-node and the fourth uplink sub-node are respectively connected with the corresponding slave functional unit 41. Specifically, the output end of the third downlink sub-node and the output end of the fourth downlink sub-node are respectively connected to the corresponding slave functional units 41. The input terminal of the third uplink sub-node and the input terminal of the fourth uplink sub-node are connected to the corresponding slave functional unit 41, respectively.
In the present application, the lower row refers to a direction in which the direction of data flow is directed from the master functional unit to the slave functional unit, and the upper row refers to a direction in which the direction of data amount is directed from the slave functional unit to the master functional unit.
As shown in fig. 2, the first predetermined child node a1 includes a master demultiplexer a11 and at least one master arbiter a 12. The master demultiplexer a11 is used to access information sent by other nodes connected to the master demultiplexer a12 and send the information to the master arbiter a12 or another other node connected to the master demultiplexer. The master arbiter a12 is used to receive the information sent by the master demultiplexer a11 or the information sent by other nodes, and output the information to other nodes connected to the master arbiter a 11. For example, only one master arbiter a12 is included in fig. 2. The rightmost first preset child node in fig. 4 includes two master arbiters a 12.
The node type of the first predetermined child node a1 may be: the node comprises a first uplink sub-node, a first downlink sub-node, a second uplink sub-node, a second downlink sub-node, a third uplink sub-node, a third downlink sub-node, a fourth uplink sub-node or a fourth downlink sub-node, wherein the number of the first preset sub-nodes of the same type connected with the first preset sub-nodes is one. For example, for the first upstream sub-node being the first preset sub-node a1, the number of the connected first upstream sub-nodes is one. In fig. 2, 3 and 4, the child nodes at both ends are all connected to only one child node of the same type, and therefore, all are the first predetermined child nodes.
Of course, it will be understood that for some first predetermined child nodes a1, where two main demultiplexers a11 are provided, a bypass demultiplexer a13 is required to be provided to receive information sent from other nodes. This information is then sent to the master arbiter, causing the master arbiter to issue the received individual information in sequence.
As shown in fig. 3, is a node network formed by two first preset sub-nodes a1 of the same type. For example, the fig. 3 may correspond to the connection relationship of the same type of child nodes of two second routing nodes in the second routing unit in fig. 1.
Wherein, as shown in fig. 4, the second preset child node a2 includes a master demultiplexer a11, at least one master arbiter a12, at least one bypass demultiplexer a13, and at least one bypass arbiter a 14. The master demultiplexer a11 is used to access information sent by other nodes connected to the master demultiplexer a11 and send the information to the corresponding master arbiter a12, the bypass arbiter a14 and/or other child nodes; for example, in FIG. 4, the left second child node is the second predetermined child node a2 whose coordinates have been assigned to the bypass demultiplexer a13 selectively assigns the information it accepts from the first predetermined child node a1 to the master arbiter a12 or the right bypass arbiter a 14.
The master arbiter a12 is configured to receive the information sent by the master demultiplexer and the bypass demultiplexer a13, and output the information to another node connected to the second predetermined child node.
The bypass demultiplexer a14 is used for accessing information sent by other child nodes and sending the information to the main arbiter a12 or the bypass arbiter a 13;
the bypass arbiter a13 is used to access the information sent by the main demultiplexer a11 and the bypass demultiplexer a14, and send the information to other nodes connected to the information.
The node type of the second preset child node is as follows: the node comprises a first uplink sub-node, a first downlink sub-node, a second uplink sub-node, a second downlink sub-node, a third uplink sub-node, a third downlink sub-node, a fourth uplink sub-node or a fourth downlink sub-node, and the number of the same type of first preset sub-nodes connected with the first preset sub-node is at least two. For example, the middle child node in fig. 3 is connected to the two child nodes beside the middle child node, and is the second preset child node. The middle two child nodes in fig. 4 are respectively connected to the two child nodes, so that the middle two child nodes in fig. 4 are the second preset child nodes.
In the present application, the arbiter is configured to sequentially send the received at least two paths of information to a next node. The demultiplexer is used for distributing the received information to at least one node connected with the demultiplexer.
As shown in fig. 6, in the present application, a connection relationship diagram of a seed node of a second routing unit and a first routing unit on a downlink channel only needs to be adaptively adjusted.
Different first routing nodes 21 and second routing nodes 31 are configured with different numbers of first-in first-out queues FIFO, and the depths of the first-in first-out queues FIFO on different first routing nodes 21 are different. And the depth of the FIFO's on the different second routing nodes 31 is different.
Each child node of the first routing node 21 has a function of splitting the burst length of the AXI bus into multiple segments, so that the burst length can be reduced.
It is understood that the AXI bus 100 includes a write address channel, a write data channel, a read address channel, a read data channel, and a write acknowledge channel. Namely, the write address/data channel is divided into two channels, namely a write address channel and a write data channel.
In some embodiments, the signal transmission directions of the write address/data channel and the read address channel are consistent, and the depths of the FIFO configurations of the same first routing node on different channels are consistent. Therefore, the child nodes of the same first routing node or second routing node on the write address/data channel and the read address channel may adopt the same structure.
As can be seen from the above, in the AXI bus structure provided in this embodiment of the application, the multiple master function units are divided into one group, the multiple slave function units are divided into one group, and the multiple master function units in the group share one routing network formed by the multiple first routing units to interact with the routing network formed by the multiple second routing units, so as to access each slave function unit, reduce the number of interconnected AXI buses, and eliminate the congestion problem realized at the back end of the chip.
An embodiment of the present application further provides a chip system, where the chip system includes an AXI bus structure in any of the above embodiments.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (12)
1. An AXI bus structure, comprising:
at least two main functional unit groups, each main functional unit group comprising at least two main functional units;
at least two first routing units, wherein the at least two master function unit groups correspond to the at least two first routing units one by one, and each first routing unit is connected with each master function unit corresponding to the master function unit group through an AXI bus;
at least two second routing units, each of the second routing units being connected to each of the first routing units via an AXI bus, respectively;
each slave function unit group comprises at least two second slave function units, the at least two slave function unit groups correspond to the at least two second routing units one by one, and each second routing unit is connected with each slave function unit corresponding to the slave function unit group through an AXI bus respectively.
2. The AXI bus structure as recited in claim 1, wherein each of the first routing units comprises at least two first routing nodes connected in sequence by an AXI bus, each of the second routing units comprises at least two second routing nodes connected in sequence by an AXI bus;
at least two second routing nodes of each second routing unit respectively correspond to the at least two first routing units one by one, and each second routing node is connected with one first routing node corresponding to the first routing unit through an AXI bus.
3. The AXI bus structure as recited in claim 2, wherein each of the first routing nodes is connected with at least one of the second routing nodes.
4. The AXI bus structure as recited in claim 2, wherein the AXI bus comprises a write address/data channel, a read address channel, a read data channel, and a write acknowledge channel;
each of the first routing nodes includes: the first downlink sub-node is positioned on a write address/data channel, the second downlink sub-node is positioned on a read address channel, the first uplink sub-node is positioned on a read data channel, and the second uplink sub-node is positioned on a write response channel;
in the same first routing unit, first downlink sub-nodes of the at least two first routing nodes are connected in sequence, second downlink sub-nodes of the at least two first routing nodes are connected in sequence, first uplink sub-nodes of the at least two first routing nodes are connected in sequence, and second uplink sub-nodes of the at least two first routing nodes are connected in sequence;
and one end of each of the first downlink sub-node, the second downlink sub-node, the first uplink sub-node and the second uplink sub-node is connected with the corresponding main function unit, and the other end of each of the first downlink sub-node, the second downlink sub-node, the first uplink sub-node and the second uplink sub-node is connected with the corresponding second routing node.
5. The AXI bus structure of claim 4, wherein each of the second routing nodes comprises: the third downlink sub-node is positioned on the write address/data channel, the fourth downlink sub-node is positioned on the read address channel, the third uplink sub-node is positioned on the read data channel, and the fourth uplink sub-node is positioned on the write response channel;
in the same second routing unit, the third downlink sub-nodes of the at least two second routing nodes are connected in sequence, the fourth downlink sub-nodes of the at least two second routing nodes are connected in sequence, the third uplink sub-nodes of the at least two second routing nodes are connected in sequence, and the fourth uplink sub-nodes of the at least two second routing nodes are connected in sequence;
the input end of the third downlink sub-node is connected with the output end of the first downlink sub-node, the input end of the fourth downlink sub-node is connected with the output end of the second downlink sub-node, one end of the third uplink sub-node is connected with the first uplink sub-node, and the other end of the fourth uplink sub-node is connected with the second uplink sub-node; and the other ends of the third downlink sub-node, the fourth downlink sub-node, the third uplink sub-node and the fourth uplink sub-node are respectively connected with the corresponding slave functional units.
6. The AXI bus structure as recited in claim 5, wherein the first predetermined child node comprises a master demultiplexer and a master arbiter;
the main multi-way distributor is used for accessing information sent by other nodes connected with the main multi-way distributor and sending the information to the main arbiter or another other node connected with the main arbiter;
the master arbiter is used for receiving the information sent by the demultiplexer or the information sent by other first preset child nodes and outputting the information to other nodes connected with the master arbiter;
the node type of the first preset child node is as follows: the node comprises a first uplink sub-node, a first downlink sub-node, a second uplink sub-node, a second downlink sub-node, a third uplink sub-node, a third downlink sub-node, a fourth uplink sub-node or a fourth downlink sub-node, and the number of the same type of first preset sub-nodes connected with the first preset sub-node is one.
7. The AXI bus structure of claim 5, wherein the second predetermined child node comprises a master demultiplexer, a master arbiter, a bypass demultiplexer, and a bypass arbiter;
the main demultiplexer is used for accessing information sent by other nodes connected with the main demultiplexer and sending the information to the main arbiter, the bypass arbiter and/or another other node connected with the main arbiter;
the main arbitrator is used for receiving the information sent by the demultiplexer, the information sent by the bypass demultiplexer and/or other child nodes and outputting the information to the nodes connected with the main arbitrator;
the bypass multi-way distributor is used for accessing information sent by other nodes connected with the bypass multi-way distributor and sending the information to the main arbiter or the bypass arbiter;
the bypass arbiter is used for accessing the information sent by the main demultiplexer and the bypass demultiplexer and sending the information to other nodes connected with the bypass arbiter;
the node type of the second preset child node is as follows: the node comprises a first uplink sub-node, a first downlink sub-node, a second uplink sub-node, a second downlink sub-node, a third uplink sub-node, a third downlink sub-node, a fourth uplink sub-node or a fourth downlink sub-node, and the number of the same type of second preset sub-nodes connected with the second preset sub-node is at least two.
8. The AXI bus structure of claim 1, wherein the master functional unit is comprised of a processor, an accelerator, a coprocessor, or a DMA controller.
9. The AXI bus structure as recited in claim 1, wherein the set of slave functional units is a memory, the slave functional unit being one memory unit of the memory.
10. The AXI bus structure of claim 4, wherein different first routing nodes are configured with different numbers of first-in-first-out queue FIFOs, and the depths of the first-in-first-out queue FIFOs on different first routing nodes are different.
11. The AXI bus structure of claim 4, wherein different second routing nodes are configured with different numbers of first-in-first-out queue FIFOs, and wherein the depths of the first-in-first-out queue FIFOs on different second routing nodes are different.
12. A chip system comprising the AXI bus structure of any of claims 1-11.
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