CN214122744U - Novel low-voltage frequency domain synthesis type ultrasonic microscope circuit - Google Patents
Novel low-voltage frequency domain synthesis type ultrasonic microscope circuit Download PDFInfo
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- CN214122744U CN214122744U CN202120024218.6U CN202120024218U CN214122744U CN 214122744 U CN214122744 U CN 214122744U CN 202120024218 U CN202120024218 U CN 202120024218U CN 214122744 U CN214122744 U CN 214122744U
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Abstract
The utility model discloses a novel low-voltage frequency domain synthesis type ultrasonic microscope circuit, which comprises a double-channel floating point multi-core signal processor, an FPGA, a DAC, an IQ modulator, a radio frequency amplifier and a transmitting sensor; the system comprises a receiving sensor, a radio frequency front-end circuit, an IQ demodulator, an ACD and a frequency synthesizer; the two-channel floating-point multi-core signal processor transmits signals to the DAC through the FPGA, and the DAC transmits the signals to the transmitting sensor through the IQ modulator and the radio frequency amplifier; the receiving sensor transmits signals to an IQ demodulator through a radio frequency receiving circuit, and the IQ demodulator transmits the signals to a two-channel floating point multi-core signal processor through an ADC; the frequency synthesizer provides local oscillation signals for the IQ modulator and the IQ demodulator. The utility model provides a novel low-voltage frequency domain synthesis type ultrasonic microscope circuit with better detection precision, low loss, strong safety, high reliability and various functions.
Description
Technical Field
The utility model relates to an ultrasonic testing technical field especially relates to a novel low-voltage frequency domain synthesis formula ultrasonic microscope circuit.
Background
Scanning ultrasonic microscopy is a high-resolution ultrasonic nondestructive testing instrument, and the resolution of the scanning ultrasonic microscope is close to nanosecond in time. To meet this requirement, conventional ultrasonic instrument designs require the generation of nanosecond-level high-voltage pulse signals at the transmitter side and high sampling frequencies in the GHz level at the receiver side. This design not only has a low signal-to-noise ratio, but the chips used are either very expensive or disable devices.
Ultrasound detection is based on the propagation and reflection of elastic waves. Propagation and reflection of elastic waves have the desired properties we expect only in a limited linear range. The high voltage pulse excitation has actually pushed the entire system under test (including the sensor) into the non-linear range. The test result after the nonlinear distortion has low signal-to-noise ratio and poor repeatability, and is not suitable for high-precision detection application.
The exact center frequency of the resulting signal after pulse excitation of the sensor is unknown to the receiving party. In radar terminology, this is a non-coherent detection method with low signal-to-noise ratio. The receiving side cannot remove the carrier wave and cannot perform correlation processing. The carrier cannot be removed, resulting in a reflection point showing up as a set of signal peaks. The inability to perform correlation processing results in the inability of the receiver to employ advanced digital signal processing methods to improve signal-to-noise ratio and sensitivity.
The pulse excitation method cannot develop a more precise frequency domain and phase domain detection method.
The utility model provides a new design circuit, this circuit is the result of low-voltage pulse compression method plus frequency domain synthesis method. The circuit design only needs common wireless communication devices and is matched with advanced signal processing, and the signal-to-noise ratio, the sensitivity and the like of the method are far higher than those of the existing time domain high voltage pulse method.
Chinese patent application No. 201811036560.7, application date: 09 month 05 in 2018, published day: 22.02/2019, with patent names: the invention discloses an ultrasonic microscope and a method based on an annular array, and discloses an ultrasonic microscope based on an annular array, which comprises an annular array transducer, an acoustic beam generator, a signal processing device, a control device, a driving device and an ultrasonic image display device, wherein the annular array transducer is connected with the acoustic beam generator; the acoustic beam generator is respectively electrically connected with the annular array surface transducer and the signal processing device, and the signal processing device is electrically connected with the ultrasonic image display device; the control device is electrically connected with the annular array surface transducer, the signal processing device and the driving device respectively; the annular array transducer is annular array, and the acoustic lens material of annular array transducer is quartz glass material, just the acoustic lens of annular array transducer locates on the drive arrangement, along with drive arrangement removes and accomplishes the scanning point by point with changing the focus. The ultrasonic microscope provided by the embodiment of the invention can reduce the cost of the acoustic lens material and ensure the performance of the ultrasonic microscope.
Although the above patent document discloses an ultrasonic microscope based on a circular array, the ultrasonic microscope has insufficient detection accuracy and poor reliability, and cannot develop a more precise frequency domain and phase domain detection method.
SUMMERY OF THE UTILITY MODEL
In view of this, the present invention provides a novel low-voltage frequency domain synthesis type ultrasonic microscope circuit with better detection precision, low loss, high safety, high reliability and various functions.
In order to realize the utility model discloses the purpose can take following technical scheme:
a novel low-voltage frequency domain synthesis type ultrasonic microscope circuit comprises a two-channel parallel interface floating point multi-core signal processor, a field programmable gate array unit, a two-channel digital-to-analog converter, an IQ modulator, a radio frequency amplifier and an emission sensor; the system comprises a receiving sensor, a radio frequency front-end circuit, an IQ demodulator, a two-channel analog-to-digital converter and a frequency synthesizer;
the two-channel parallel interface floating point multi-core signal processor is used for digital signal processing; the field programmable gate array unit is used for storing and processing digital signals; the two-channel digital-to-analog converter is used for converting a digital signal into an analog signal; the IQ modulator is used for modulating the center frequency of the fundamental frequency signal to high frequency; the radio frequency amplifier is used for amplifying a high-frequency signal; the transmitting sensor is used for converting an electric signal into an ultrasonic vibration signal;
the receiving sensor is used for converting the ultrasonic vibration signal into an electric signal; the radio frequency front-end circuit is used for amplifying or attenuating or protecting a radio frequency signal; the IQ demodulator is used for demodulating the high-frequency radio-frequency signal into a pair of IQ base-frequency signals; the two-channel analog-to-digital converter is used for converting an analog signal into a digital signal; the frequency synthesizer is used for providing local oscillation signals;
the dual-channel parallel interface floating-point multi-core signal processor transmits a digital signal to a dual-channel digital-to-analog converter through a field programmable gate array unit, and the dual-channel digital-to-analog converter converts the digital signal into a pair of analog base frequency signals and transmits the analog base frequency signals to the IQ modulator; the IQ modulator transmits a base frequency signal to the transmitting sensor through a radio frequency amplifier;
the receiving sensor transmits signals to an IQ demodulator through a radio frequency front-end circuit, the IQ demodulator demodulates high-frequency radio frequency signals into a pair of IQ base frequency signals and transmits the IQ base frequency signals to the two-channel analog-to-digital converter, and the two-channel analog-to-digital converter converts analog signals into digital signals and transmits the digital signals to the two-channel parallel interface floating point multi-core signal processor; the frequency synthesizer provides local oscillation signals for the IQ modulator and the IQ demodulator.
The two-channel parallel interface floating point multi-core signal processor is a chip with the model number of TMS320C 6657.
And the two-channel parallel interface floating point multi-core signal processor transmits signals to the field programmable gate array unit through a serial interface.
The radio frequency front-end circuit comprises a front-end protection circuit, a pre-amplification circuit and a filter, wherein the receiving sensor transmits signals to the pre-amplification circuit through the front-end protection circuit, and the pre-amplification circuit amplifies the signals and then transmits the signals to the radio frequency front-end circuit through the filter.
The frequency synthesizer includes a reference clock source that provides a clock source for the frequency synthesizer.
The dual-channel analog-to-digital converter comprises a parallel interface, and transmits signals to the dual-channel parallel interface floating point multi-core signal processor through the parallel interface.
The utility model has the advantages that: 1) the utility model does not contain any high voltage pulse generating device and any transmitting and receiving transfer switch device, and has low loss and high safety; 2) the utility model has the advantages of best signal-to-noise ratio, strong sensitivity, good repeatability and high detection precision, and is suitable for high-precision detection requirements; 3) the utility model adds the result of the frequency domain synthesis method through the low voltage pulse compression method to achieve the best signal-to-noise ratio and sensitivity; the utility model discloses use extensively, be fit for generally promoting.
Drawings
Fig. 1 is a circuit block diagram of a novel low-voltage frequency domain synthesis type ultrasonic microscope according to an embodiment of the present invention;
fig. 2 is a circuit block diagram of a novel low-voltage frequency domain synthesis type ultrasonic microscope according to another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and embodiments of the present invention.
Example 1
Referring to fig. 1, the novel low-voltage frequency domain synthesis type ultrasonic microscope circuit comprises a two-channel parallel interface floating point multi-core signal processor 1, a Field Programmable Gate Array (FPGA) unit 2, a two-channel digital-to-analog converter (DAC)3, an IQ modulator 4, a radio frequency amplifier 5 and a transmitting sensor 6; a receiving sensor 10, a radio frequency front end circuit 9, an IQ demodulator 8, a dual-channel analog-to-digital converter 7(ADC), a frequency synthesizer 11;
the two-channel parallel interface floating point multi-core signal processor 1 is used for digital signal processing; the field programmable gate array unit 2 is used for storing and processing digital signals; the dual-channel digital-to-analog converter 3 is used for converting a digital signal into an analog signal; the IQ modulator 4 is configured to modulate a center frequency of the fundamental frequency signal to a high frequency; the radio frequency amplifier 5 is used for amplifying a high-frequency signal; the transmitting sensor 6 is used for converting an electric signal into an ultrasonic vibration signal;
the receiving sensor 10 is used for converting the ultrasonic vibration signal into an electric signal; the radio frequency front-end circuit 9 is configured to amplify or attenuate a radio frequency signal or protect a load; the IQ demodulator 8 is configured to demodulate the high-frequency radio frequency signal into a pair of IQ baseband signals; the two-channel analog-to-digital converter 7 is used for converting an analog signal into a digital signal; the frequency synthesizer 11 is configured to provide a local oscillator signal;
the double-channel parallel interface floating-point multi-core signal processor 1 transmits a digital signal to a double-channel digital-to-analog converter (DAC)3 through a Field Programmable Gate Array (FPGA)2, and the double-channel DAC 3 converts the digital signal into a pair of analog base frequency signals and transmits the analog base frequency signals to the IQ modulator 4; the IQ modulator 4 transmits the base frequency signal to the transmitting sensor 6 through the radio frequency amplifier 5; the transmitting transducer 6 converts the electrical signal into an ultrasonic vibration signal; thus, a complete transmitting circuit is formed, and the transmitting sensor 6 transmits signals to a required detection device to carry out ultrasonic detection on the device;
the receiving sensor 10 converts the reflected ultrasonic vibration signal into an electric signal; the receiving sensor 10 transmits the signals to an IQ demodulator 10 through a radio frequency front end circuit 9, the IQ demodulator 10 demodulates the high-frequency radio frequency signals into a pair of IQ fundamental frequency signals and transmits the IQ fundamental frequency signals to the two-channel analog-to-digital converter 7, and the two-channel analog-to-digital converter 7 converts the analog signals into digital signals and transmits the digital signals to the two-channel parallel interface floating point multi-core signal processor 1; the frequency synthesizer 11 provides local oscillation signals for the IQ modulator 4 and the IQ demodulator 8; thus, a completed receiving circuit is constructed.
Referring to fig. 1 and 2, in the embodiment, preferably, the dual-channel parallel interface floating point multi-core signal processor 1 is a chip with a model number of TMS320C 6657.
The two-channel parallel interface floating point multi-core signal processor 1 is connected with a field programmable gate array unit (FPGA)2 through a serial interface (SPI). In the receiving circuit, the two-channel analog-to-digital converter 7 transmits signals to the two-channel parallel interface floating point multi-core signal processor 1 through the parallel interface.
The field programmable gate array unit (FPGA)2 receives a transmission baseband signal generated by a Digital Signal Processor (DSP), and then continuously and repeatedly transmits the transmission baseband signal to a dual-channel digital-to-analog converter (DAC) 3.
The two-channel dac 3 converts the digital IQ signals into a pair of analog baseband signals, which are transmitted to the IQ modulator 4. The IQ modulator 4 modulates the transmitted IQ baseband signal to a high frequency, the center frequency of which is determined by the output of the frequency synthesizer 11; the radio frequency amplifier 5 sends a high frequency signal to the transmitting transducer 6.
In this embodiment, the rf front-end circuit 9 preferably includes a front-end protection circuit 91, a pre-amplification circuit 92, and a filter 93, the receiving sensor 10 transmits the signal to the pre-amplification circuit 92 through the front-end protection circuit 91, and the pre-amplification circuit 92 amplifies the signal and transmits the signal to the rf front-end circuit 9 through the filter 93.
In this embodiment, the IQ demodulator 8 reduces the high-frequency rf signal into a pair of IQ baseband signals; the two-channel analog-to-digital converter 7 is used for sampling and digitizing the pair of fundamental frequency signals and outputting the signals through a parallel port, and the two-channel parallel interface floating point multi-core signal processor 1 is used for processing the signals.
In this embodiment, the frequency synthesizer 11 includes a reference clock source 12, and the reference clock source 12 provides a clock source for the frequency synthesizer 11.
The reference clock source 12 provides a reference clock for the frequency synthesizer 11, and also provides a synchronous sampling clock for the dual-channel digital-to-analog converter 3(DAC) and the dual-channel analog-to-digital converter 7 (ADC). The frequency synthesizer 11 provides local oscillation signals for the IQ modulator 4 and the IQ demodulator 8 under the control of the two-channel parallel interface floating point multi-core signal processor 1.
The whole detection system (from the circuit to the ultrasonic sensor to the ultrasonic transmission and reflection) is a linear system which needs to be characterized. The purpose of the probe is to find the impulse response of the system.
The conventional design approach is to directly excite the system with a pulse signal and then digitize the impulse response signal with very high frequency samples. The disadvantage of this method is not repeated here.
The principle of the present invention is to first seek the steady state frequency domain response (amplitude and phase) of this system, and then transform the frequency domain response into a time domain impulse response by inverse Fourier transform.
When seeking frequency domain response, the utility model discloses a method that each breaks, the segmentation is synthetic. If it is desired to acquire a frequency response in the frequency range of 50MHz to 1000MHz, and assume that our baseband signal processing bandwidth is 50 MHz.
First, a 50MHz bandwidth baseband signal is generated using the DSP. The fundamental frequency signal is composed of multiple frequencies, while the total amplitude of the signal still maintains a minimum peak ratio. The period of this signal (or the separation of the constituent frequencies) is determined by factors such as the maximum measured distance and multi-echo control. The digital baseband signal is sent to the FPGA. After receiving all the IQ base frequency signals, the FPGA starts to repeatedly send the IQ digital base frequency signals to the two-channel DAC according to the command of the DSP. The DAC converts the signals into analog signals, and the analog signals are sent to an IQ modulator after low-pass filtering. The IQ modulator modulates the signal to a bandpass signal whose center frequency is determined by the output of the frequency synthesizer.
On the receiving side, the IQ demodulator reduces the band pass signal to a fundamental IQ signal, which is then sent to a two-channel ADC. The dual-channel ADC sends the digital signal to the DSP through the parallel port.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (6)
1. A novel low-voltage frequency domain synthesis type ultrasonic microscope circuit is characterized in that: the system comprises a two-channel parallel interface floating point multi-core signal processor, a field programmable gate array unit, a two-channel digital-to-analog converter, an IQ modulator, a radio frequency amplifier and a transmitting sensor; the system comprises a receiving sensor, a radio frequency front-end circuit, an IQ demodulator, a two-channel analog-to-digital converter and a frequency synthesizer;
the two-channel parallel interface floating point multi-core signal processor is used for digital signal processing; the field programmable gate array unit is used for storing and processing digital signals; the two-channel digital-to-analog converter is used for converting a digital signal into an analog signal; the IQ modulator is used for modulating the center frequency of the fundamental frequency signal to high frequency; the radio frequency amplifier is used for amplifying a high-frequency signal; the transmitting sensor is used for converting an electric signal into an ultrasonic vibration signal;
the receiving sensor is used for converting the ultrasonic vibration signal into an electric signal; the radio frequency front-end circuit is used for amplifying or attenuating or protecting a radio frequency signal; the IQ demodulator is used for demodulating the high-frequency radio-frequency signal into a pair of IQ base-frequency signals; the two-channel analog-to-digital converter is used for converting an analog signal into a digital signal; the frequency synthesizer is used for providing local oscillation signals;
the dual-channel parallel interface floating-point multi-core signal processor transmits a digital signal to a dual-channel digital-to-analog converter through a field programmable gate array unit, and the dual-channel digital-to-analog converter converts the digital signal into a pair of analog base frequency signals and transmits the analog base frequency signals to the IQ modulator; the IQ modulator transmits a base frequency signal to the transmitting sensor through a radio frequency amplifier;
the receiving sensor transmits signals to an IQ demodulator through a radio frequency front-end circuit, the IQ demodulator demodulates high-frequency radio frequency signals into a pair of IQ base frequency signals and transmits the IQ base frequency signals to the two-channel analog-to-digital converter, and the two-channel analog-to-digital converter converts analog signals into digital signals and transmits the digital signals to the two-channel parallel interface floating point multi-core signal processor; the frequency synthesizer provides local oscillation signals for the IQ modulator and the IQ demodulator.
2. The novel low-voltage frequency-domain synthesized ultrasonic microscope circuit of claim 1, wherein: the two-channel parallel interface floating point multi-core signal processor is a chip with the model number of TMS320C 6657.
3. The novel low voltage frequency domain synthetic ultrasound microscope circuit of claim 1 or 2, wherein: and the two-channel parallel interface floating point multi-core signal processor transmits signals to the field programmable gate array unit through a serial interface.
4. The novel low voltage frequency domain synthetic ultrasound microscope circuit of claim 3, wherein: the radio frequency front-end circuit comprises a front-end protection circuit, a pre-amplification circuit and a filter, wherein the receiving sensor transmits signals to the pre-amplification circuit through the front-end protection circuit, and the pre-amplification circuit amplifies the signals and then transmits the signals to the radio frequency front-end circuit through the filter.
5. The novel low-voltage frequency-domain synthesized ultrasonic microscope circuit of claim 4, wherein: the frequency synthesizer includes a reference clock source that provides a clock source for the frequency synthesizer.
6. The novel low voltage frequency domain synthetic ultrasound microscope circuit of claim 5, wherein: the dual-channel analog-to-digital converter comprises a parallel interface, and transmits signals to the dual-channel parallel interface floating point multi-core signal processor through the parallel interface.
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