CN214043677U - Power semiconductor device - Google Patents

Abstract

The utility model relates to the technical field of semiconductors, concretely relates to power semiconductor device, power semiconductor device includes N base member and middle P + layer, the top both ends of N base member all are equipped with active area N + layer and parcel the P district on active area N + layer, the P district includes channel P-layer, channel P-layer is disposed the inboard on active area N + layer, gate oxide is disposed the surface middle part of N base member, and cover active area N + layer, middle P + layer is disposed two between the P district, and with two the P district links to each other. The utility model provides a pair of power semiconductor device can reduce the electric field strength that gate oxide bore when the drain electrode is exerted pressure, reduces the probability that gate oxide was punctured, improves the reliability of device, can guarantee the channel density of device simultaneously.

Description

Power semiconductor device

Technical Field

The utility model relates to the field of semiconductor technology, concretely relates to power semiconductor device.

Background

Compared with Si materials, the SiC materials have 10 times of critical breakdown electric fields, so that when MOSFET devices with the same voltage class are designed, the thickness of a drift region of the devices can be greatly reduced, the doping concentration can also be improved, and the resistance of the drift region of the devices can be reduced by 1000 times, so that SiC becomes an attractive semiconductor material for developing high-voltage power MOSFET devices.

However, in a MOSFET device using SiC as a semiconductor material, the maximum electric field withstanding capability of the gate oxide is low, and the MOSFET device is easily broken after a high reverse voltage is applied to the drain and source. Moreover, because the planar SiC power MOSFET device has JFET resistance, the width of the gate is generally designed to be large in the prior art, so that the middle portion of the gate is subjected to high electric field strength after the drain is reversely stressed, and the gate is easily damaged.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a solve among the prior art width of MOSFET device bars great, cause the technical problem that the grid oxygen damaged easily after the drain electrode is exerted pressure in reverse, provided a power semiconductor device, can reduce the electric field strength that the grid oxygen bore when the drain electrode is exerted pressure, reduced the probability that the grid oxygen was punctured, improved the reliability of device.

The technical scheme of the utility model:

a power semiconductor device comprising:

the device comprises an N substrate, wherein an active region N + layer and a P region wrapping the active region N + layer are arranged at two ends of the top of the N substrate;

a P region including a channel P-layer configured inside the active region N + layer;

the gate oxide layer is arranged in the middle of the surface of the N substrate and covers the active region N + layer;

an intermediate P + layer disposed between and connected to the two P regions.

Furthermore, the plurality of intermediate P + layers are arranged at intervals along a direction perpendicular to the cross section of the cellular structure of the power semiconductor device.

Optionally, the intermediate P + layers include a first intermediate P + layer disposed between the two channel P-layers and a second intermediate P + layer formed by the channel P-layers being highly doped.

Optionally, the P region further includes a P +1 layer disposed outside the active region N + layer and a P +2 layer disposed at the bottom of the active region N + layer, and the middle P + layer is disposed between the two P +2 layers and is connected to the two P +2 layers.

Preferably, the N base includes an N + substrate and an N-drift region epitaxially formed on the N + substrate, and a middle N + layer is further disposed at a middle position of a top of the N-drift region.

Preferably, the material of the N matrix is SiC.

After the technical scheme is adopted, compared with the prior art, the utility model, have following beneficial effect: the utility model discloses a power semiconductor device is provided with middle P + layer at the below interval of gate oxide, and this middle P + layer links to each other with the active area, after the reverse voltage that applys of leakage source, can reduce gate oxide's electric field strength, reduces the probability that gate oxide was punctured, improves the reliability of device, is particularly useful for adopting the power device of third generation semiconductor material preparation such as SiC. Meanwhile, the middle P + layer can be designed into a buried layer scheme, so that the electric field intensity of a gate oxide layer when the device applies voltage reversely is reduced, and the channel density of the device is not reduced.

Drawings

FIG. 1 is a schematic cross-sectional view of a planar MOSFET in the prior art;

fig. 2 is a top view of the planar MOSFET structure of fig. 1 (excluding the polysilicon gate and the dielectric layer);

FIG. 3 is a top view of a planar MOSFET structure (excluding the polysilicon gate and dielectric layer) in accordance with one embodiment;

FIG. 4a is a schematic cross-sectional view A1-A1' of FIG. 3;

FIG. 4b is a schematic cross-sectional view A2-A2' of FIG. 3;

FIG. 5a is a schematic cross-sectional view B1-B1' of FIG. 3;

FIG. 5B is a schematic cross-sectional view B2-B2' of FIG. 3;

FIG. 5c is a schematic cross-sectional view B3-B3' of FIG. 3;

FIG. 6 is a top view of a four-sided embodiment planar MOSFET structure (excluding polysilicon gates and dielectric layers);

FIG. 7a is a schematic cross-sectional view A1-A1' of FIG. 6;

FIG. 7b is a schematic cross-sectional view A2-A2' of FIG. 6;

FIG. 8a is a schematic cross-sectional view B1-B1' of FIG. 6;

FIG. 8B is a schematic cross-sectional view B2-B2' of FIG. 6;

FIG. 8c is a schematic cross-sectional view of B3-B3' of FIG. 6.

Wherein the content of the first and second substances,

the semiconductor device comprises an N matrix 1, an N + substrate 11, an N-drift region 12, an intermediate N + layer 13, an active region N + layer 2, a P region 3, a channel P-layer 31, a P +1 layer 32, a P +2 layer 33, an intermediate P + layer 4, a gate oxide layer 5, a polysilicon gate 6 and an insulating dielectric layer 7.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the orientation words such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" etc. are usually based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplification of description, and in the case of not making a contrary explanation, these orientation words do not indicate and imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore, should not be interpreted as limiting the scope of the present invention; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.

Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and if not stated otherwise, the terms have no special meaning, and therefore, the scope of the present invention should not be construed as being limited.

The utility model aims at providing a plane MOSFET device structure, P + layer in the middle of the below interval of grid oxygen sets up in the N base member, and middle P + interlamellar spacing can be adjusted according to the degree of protection grid oxygen, and this middle P + layer links to each other with the active area, after the reverse voltage that applys of leakage source, can reduce gate oxide electric field intensity, reduces the probability that grid oxygen was punctured, improves the reliability of device. The method is particularly suitable for power devices made of third-generation semiconductor materials such as SiC and the like. Meanwhile, the middle P + layer can be designed into a buried layer scheme, so that the electric field intensity of gate oxide is reduced when the reverse voltage is applied to the device, and the channel density of the device is not reduced. The power semiconductor device will be specifically described below with reference to specific examples.

The first embodiment is as follows:

as shown in fig. 1-2, a planar MOSFET structure in the prior art includes an N base body 1, an active region N + layer 2, a P region 3, and a gate oxide layer 5, where the active region N + layer 2 and the P region 3 wrapping the active region N + layer 2 are disposed at both ends of the top of the N base body 1, a gate oxide layer 5 is disposed in the middle of the surface of the N base body 1, the gate oxide layer 5 covers the active region N + layer 2, a polysilicon gate 6 and an insulating dielectric layer 7 are disposed above the gate oxide layer 5, the active region N + layer 2 is electrically connected to a source electrode, and the bottom of the N base body 1 is electrically connected to a drain electrode. Further, both P regions 3 include a channel P-layer 31, the channel P-layer 31 is disposed inside the active region N + layer 2, the channel P-layer 31 inverts to form a conductive channel when a gate-on voltage is applied, and an on-current flows in a vertical direction in the N matrix 1. Because JFET (junction field effect transistor) resistance exists in the MOSFET structure, the area below the gate oxide layer 5 is generally designed to be large, namely the space between the two channel P-layers 31 is large, so that when the device bears a high drain voltage, the electric field intensity below the gate oxide layer 5 is high, and the gate oxide layer 5 is easily broken down and damaged.

Further, as shown in fig. 1, the N base 1 further includes an N + substrate 11 and an N-drift region 12 epitaxially formed on the N + substrate 11, the N-drift region 12 is used to improve the withstand voltage capability, and a middle N + layer 13 is further disposed at a middle position of the top of the N-drift region 12, so that the conduction capability of the device can be increased. The dashed line in fig. 1 is the approximate intersection of the intermediate N + layer 13 and the N-drift layer 12.

The present embodiment improves the prior art, and as shown in fig. 3-5 c, the power semiconductor device of the present embodiment further includes an intermediate P + layer 4, and the intermediate P + layer 4 is disposed between the two P regions 3 and connected to the two P regions 3. Therefore, a PN junction is formed between the gate oxide layer 5 and the drain electrode, when the power semiconductor device is subjected to a higher drain voltage, namely, the PN junction is reversely applied with pressure, and with the increase of the voltage, the depletion layer of the PN junction is wider and wider, and finally the gate oxide layer 5 and the drain electrode are clamped off, so that the electric field intensity below the gate oxide layer 5 is greatly reduced, the probability that the gate oxide layer 5 is broken down is reduced, and the reliability of the device is improved.

Further, the number of the intermediate P + layers 4 in this embodiment is plural, and the intermediate P + layers are uniformly or non-uniformly arranged at intervals in a direction perpendicular to the cross section of the cell structure of the power semiconductor device. Specifically, the structures shown in fig. 4a and 4b are all cell structure cross sections of the power semiconductor device, and as shown in fig. 3, in this embodiment, a plurality of intermediate P + layers 4 are uniformly arranged at intervals in a direction perpendicular to the cell cross sections, and an intermediate N + layer 13 is still arranged between every two intermediate P + layers 4, so that after a gate is applied with a turn-on voltage, the intermediate N + layers 13 between the P + layers can still form a wider current path, and thus, the conduction capability required by the device can be maintained. The number and the interval of the middle P + layers 4 can be adjusted according to the reverse voltage and the degree of the protective gate oxide, so that the reverse withstand voltage capability of the device can be met, and the conduction capability of the device can be improved as much as possible.

Further, the P region 3 of the present embodiment further includes a P +1 layer 32 disposed outside the active region N + layer 2 and a P +2 layer 33 disposed at the bottom of the active region N + layer 2.

Further, as shown in fig. 4b, the intermediate P + layer 4 of the present embodiment includes a first intermediate P + layer disposed between the two original channel P-layers 31 and a second intermediate P + layer formed by the channel P-layers 31 through high doping, so that the intermediate P + layer 4 is located between the two active region N + layers 2 and connected to the two P regions 3 in the cross-sectional structure of a2-a 2' of fig. 3.

Preferably, the material of the N matrix 1 of this embodiment is SiC, because the critical breakdown electric field of SiC is much higher than that of a common Si material, when SiC is used as the matrix material, the thickness of the device drift region can be greatly reduced, but the thickness of the device drift region is reduced, so that the gate oxide layer 5 is more easily broken down, and the device of the SiC material is generally used in a high voltage situation, so the risk of breaking down the gate oxide layer 5 is higher.

As can be seen from the above, the power semiconductor device provided in this embodiment can reduce the electric field strength borne by the gate oxide layer 5 when applying a reverse voltage, reduce the probability of breakdown of the gate oxide layer 5, improve the reliability of the device, and ensure a certain current conducting capability.

Example two:

the embodiment provides a manufacturing process flow of a power semiconductor device of the first embodiment, which includes the following steps:

s1, extending a layer of N-epitaxial layer 12 and a layer of P-epitaxial layer with required thickness on the surface of the N + substrate 11 by adopting an epitaxial process to form an N matrix 1;

s2, defining the middle N + layer 13 area by photoetching by adopting photoetching and ion implantation processes, and compensating the area corresponding to the middle N + layer 13 in the corresponding P-epitaxial layer into N type doping by implanting nitrogen ions or phosphorus ions with different energies to form the middle N + layer 13; thus, a P-epitaxial layer is firstly formed through epitaxy process, then corresponding N-type semiconductor impurities are injected on the P-epitaxial layer to form a middle N + layer 13, and a part of the P-epitaxial layer is reserved as a channel P-layer 31;

s3, defining the P +1 layer 32 to be implanted by photoetching by adopting photoetching and ion implantation processes, and forming the P +1 layer 32 by implanting aluminum ions with different energies into corresponding areas with different depths of the active layer;

s4, defining a P +2 layer 33 to be implanted by photoetching by adopting photoetching and ion implantation processes, forming the P +2 layer 33 by implanting aluminum ions with different energies into corresponding regions with different depths of the active layer, and forming a P region 3 in the first embodiment by the P +1 layer 32, the P +2 layer 33 and the P-layer;

s5, defining the middle P + layer 4 area by photoetching and ion implantation, and implanting aluminum ions to form the middle P + layer 4; thus, the middle P + layer 4 of the utility model is located in the upper region of the device, so that the injection process of the middle P + layer 4 is simple and easy to realize, especially in the device made of SiC material, the deeper the depth is, the more difficult the ion injection is, and the structure of the utility model can well avoid the problem;

s6, defining the region to be implanted by photoetching by adopting photoetching and ion implantation processes, and forming an active region N + layer 2 by implanting the corresponding regions of nitrogen ions or phosphorus ions with different energies;

s7, growing an oxide layer on the surface of the N substrate 1 by thermal oxidation to form a gate oxide layer 5 by a thermal oxidation process;

s8, depositing a layer of polysilicon on the gate oxide layer 5 by adopting a deposition process to form a polysilicon gate 6;

s9, defining different polysilicon gate 6 areas by photoetching and etching processes, and etching off unnecessary polysilicon;

s10, depositing an insulating dielectric layer 7 on the surface of the polysilicon gate 6 by adopting a deposition process to electrically isolate the polysilicon gate 6 from metal;

s11, defining the active layer orifice layer and the orifice layer on different polysilicon gates 6 by photoetching and etching process, and etching the unnecessary insulating dielectric layer 7;

s12, depositing a layer of metal on the insulating medium layer 7 by adopting a deposition process;

and S13, defining the active layer metal area and the grid metal area by photoetching and etching processes, and etching to form the active area electrode and the grid electrode of the device.

Further, the sequence of steps S2-S6 may be re-adjusted as required, that is, the formation sequence of the P region 3, the active region N + layer 2, the intermediate N + layer 13, and the intermediate P + layer 4 may be adjusted as required.

Example three:

the manufacturing process of the power semiconductor device of this embodiment is different from that of the second embodiment in that steps S1-S2 in the second embodiment can be replaced by the following steps:

an N-epitaxial layer 12 with the required thickness is epitaxially formed on the surface of an N + substrate 11 by adopting an epitaxial process to form an N matrix 1;

photoetching and ion implantation processes are adopted, a channel P-layer 31 area is defined through photoetching, and aluminum ions are implanted to form a channel P-layer 31;

photoetching and ion implantation processes are adopted, the middle N + layer 13 area is defined by photoetching, and nitrogen ions or phosphorus ions with different energies are implanted to form a middle N + layer 13; thus, a channel P-layer 31 and an intermediate N + layer 13 are formed by implanting different ions on the N-epitaxial layer 12, respectively.

Example four:

as shown in fig. 6 to 8c, the power semiconductor device of the present embodiment is different from the first embodiment in that the intermediate P + layer 4 of the present embodiment is disposed between the two P +2 layers 33 and connected to the two P +2 layers 33, and the intermediate P + layer 4 is a buried layer structure, and the intermediate N + layer 13 still remains above the intermediate P + layer 4, so that after the gate is applied with the turn-on voltage, the channel P-layer 31 still inverts to form a conduction loop without reducing the channel density of the device.

The power semiconductor device of this embodiment may also adopt the manufacturing processes of the second embodiment and the third embodiment, the difference is the implantation depth of the intermediate P + layer 4, and other specific embodiments may refer to the second embodiment and the third embodiment.

As can be seen from the above, the power semiconductor device of the present embodiment can reduce the electric field intensity of the gate oxide layer when a high voltage is applied in the reverse direction of the device, thereby protecting the gate oxide layer, and does not reduce the channel density of the device.

The above, only be the concrete implementation of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the utility model, the concept of which is equivalent to replace or change, should be covered within the protection scope of the present invention.

Claims (6)

1. A power semiconductor device, comprising:

the device comprises an N substrate (1), wherein both ends of the top of the N substrate (1) are provided with an active area N + layer (2) and a P area (3) wrapping the active area N + layer (2);

a P region (3), the P region (3) comprising a channel P-layer (31), the channel P-layer (31) being arranged inside the active area N + layer (2);

a gate oxide layer (5), wherein the gate oxide layer (5) is configured in the middle of the surface of the N substrate (1) and covers the active region N + layer (2);

an intermediate P + layer (4), the intermediate P + layer (4) being arranged between the two P regions (3) and being connected to the two P regions (3).

2. The power semiconductor device according to claim 1, wherein the intermediate P + layers (4) are plural and arranged at intervals in a direction perpendicular to a cross section of the cell structure of the power semiconductor device.

3. Power semiconductor device according to claim 1 or 2, characterized in that the intermediate P + layer (4) comprises a first intermediate P + layer arranged between two of the channel P-layers (31) and a second intermediate P + layer formed by the channel P-layers (31) being highly doped.

4. Power semiconductor device according to claim 1 or 2, characterized in that the P-region (3) further comprises a P +1 layer (32) arranged outside the active region N + layer (2) and a P +2 layer (33) arranged at the bottom of the active region N + layer (2), the intermediate P + layer (4) being arranged between the two P +2 layers (33) and being connected to the two P +2 layers (33).

5. The power semiconductor device according to claim 1, characterized in that the N-body (1) comprises an N + substrate (11) and an N-drift region (12) epitaxially formed on the N + substrate (11), the N-drift region (12) being further provided with an intermediate N + layer (13) in a position intermediate on top of the N-drift region.

6. Power semiconductor device according to claim 1, characterized in that the material of the N-body (1) is SiC.

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