CN214043658U - Packaging structure - Google Patents

Packaging structure Download PDF

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Publication number
CN214043658U
CN214043658U CN202022376318.3U CN202022376318U CN214043658U CN 214043658 U CN214043658 U CN 214043658U CN 202022376318 U CN202022376318 U CN 202022376318U CN 214043658 U CN214043658 U CN 214043658U
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Prior art keywords
carrier
flow
carrier plate
electronic component
package
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CN202022376318.3U
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Chinese (zh)
Inventor
张伟杰
张强波
宋关强
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Sky Chip Interconnection Technology Co Ltd
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Sky Chip Interconnection Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The application provides a packaging structure, which comprises a first carrier plate, a first electronic component, a second carrier plate and a first through flow column; the first carrier plate is provided with a first surface and a second surface opposite to the first surface; a first electronic component is attached to the first surface of the first carrier plate; the second electronic component is attached to the second surface of the first carrier plate; the second carrier plate is arranged opposite to the second surface of the first carrier plate, and a communicating piece is arranged on the surface of the second carrier plate facing the first carrier plate; one end of the first through flow column is connected with the second surface of the first carrier plate, and the other end of the first through flow column is connected with the communicating piece on the second carrier plate; and the transverse dimension of the first through-flow column is smaller than that of the communicating piece. Therefore, the volume of the product can be reduced, and the heat dissipation and the through-flow capacity of the product can be effectively improved.

Description

Packaging structure
Technical Field
The utility model relates to a semiconductor package technical field especially relates to an encapsulation structure.
Background
In the information society of today, the dependence of human beings on electronic products is increasing day by day, and the electronic products are developing vigorously in the direction of high integration, miniaturization and miniaturization.
Currently, in order to achieve high integration, miniaturization and miniaturization of products, a Package In Package (PiP), a Package on Package (PoP) or a System In Package (SiP) is generally adopted to Package each component; however, the prior art package structure type has weak heat dissipation and current capacity.
SUMMERY OF THE UTILITY MODEL
The application provides a packaging structure, has not only reduced the product volume, and has effectively improved the heat dissipation and the current capacity of product.
In order to solve the technical problem, the application adopts a technical scheme that: providing a packaging structure, wherein the packaging structure comprises a first carrier plate, a first electronic component, a second carrier plate and a first through flow column; the first carrier plate is provided with a first surface and a second surface opposite to the first surface; a first electronic component is attached to the first surface of the first carrier plate; the second electronic component is attached to the second surface of the first carrier plate; the second carrier plate is arranged opposite to the second surface of the first carrier plate, and a communicating piece is arranged on the surface of the second carrier plate facing the first carrier plate; one end of the first through flow column is connected with the second surface of the first carrier plate, and the other end of the first through flow column is connected with the communicating piece on the second carrier plate; and the transverse dimension of the first through-flow column is smaller than that of the communicating piece.
According to the packaging structure provided by the application, the first electronic component and the second electronic component are respectively attached to the first surface and the second surface of the first carrier plate, so that the size of a product is greatly reduced; meanwhile, the communicating piece is arranged on the second carrier plate, and the transverse size of the communicating piece is larger than that of the first through flow column, so that the first through flow column and the communicating piece are well aligned in the mounting process, and the through flow capacity of a product is effectively improved.
Drawings
Fig. 1 is a schematic structural diagram of a package structure according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a first package according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a second carrier according to an embodiment of the present application;
fig. 4 is a schematic structural diagram illustrating a power bare chip mounted on a first carrier according to a first embodiment of the present application;
fig. 5 is a schematic structural diagram illustrating a power bare chip mounted on a first carrier according to a second embodiment of the present application;
fig. 6 is a schematic structural diagram illustrating a power bare chip mounted on a first carrier according to a third embodiment of the present application;
fig. 7 is a schematic flowchart illustrating a method for manufacturing a package structure according to an embodiment of the present application;
FIG. 8 is a flowchart illustrating the step S13 in FIG. 7;
fig. 9a is a schematic view of a product structure corresponding to step S130 in fig. 8;
fig. 9b is a schematic view of a product structure corresponding to step S131 in fig. 8.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second" and "third" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. All directional indications (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are only used to explain the relative positional relationship between the components, the movement, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indication is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The present application will be described in detail with reference to the accompanying drawings and examples.
Referring to fig. 1 to fig. 3, fig. 1 is a schematic structural diagram of a package structure according to an embodiment of the present application; fig. 2 is a schematic structural diagram of a first package according to an embodiment of the present disclosure; fig. 3 is a schematic structural diagram of a second carrier according to an embodiment of the present application.
In the present embodiment, a package structure 1 is provided, which includes a first package body 10, a second carrier 11 and a second package layer 12.
The first package 10 includes a first carrier 100, an electronic component 101, and a first package layer 102. The electronic component 101 is attached to at least one surface of the first carrier 100. Specifically, the first encapsulation layer 102 covers a side surface of the electronic component 101 away from the first carrier 100, and cooperates with the first carrier 100 to encapsulate the electronic component 101, so as to protect the electronic component 101.
Specifically, a signal line electrically connected to a pin of the electronic component 101 is disposed on the first carrier 100, a pad is disposed on the first carrier 100, the pad is communicated with the signal line, and the pin of the electronic component 101 can be printed by connecting solder paste to the pad.
Specifically, the electronic component 101 includes one or any combination of a resistor, an inductor, a capacitor, a chip, and a power bare chip 1010. Of course, in other embodiments, the electronic component 101 may further include a diode and a transistor, which is not limited in this embodiment.
In a specific implementation process, electronic components 101 are mounted on both the upper surface and the lower surface (i.e., a first surface and a second surface opposite to the first surface) of the first carrier 100, so as to reduce a floor area and a product volume; specifically, a first electronic component is attached to a side surface, i.e., a first surface, of the first carrier 100 away from the second carrier 11, where the first electronic component may specifically include one or more of a resistor, a capacitor, a chip, a power bare chip 1010, and a partial inductor, and a second electronic component is attached to a side surface, i.e., a second surface, of the first carrier 100 close to the second carrier 11, where the second electronic component may specifically include an inductor.
Referring to fig. 4 to 6, fig. 4 is a schematic structural view illustrating a power bare chip mounted on a first carrier according to a first embodiment of the present disclosure; fig. 5 is a schematic structural diagram illustrating a power bare chip mounted on a first carrier according to a second embodiment of the present application; fig. 6 is a schematic structural diagram illustrating a power bare chip mounted on a first carrier according to a third embodiment of the present application.
In one embodiment, the power bare chip 1010 may be attached to the first carrier 100 by an adhesive, which is taken as an example in the following embodiments.
Specifically, the adhesive may be glue.
In a specific implementation process, a bonding wire is disposed on the power bare chip 1010, and the bonding wire is connected to a bonding pad on the first carrier 100 to electrically connect the power bare chip 1010 and a signal line on the first carrier 100.
Of course, in other embodiments, the power bare chip 1010 may also be mounted on the first carrier 100 by solder balls or copper pillars, which can be seen in the prior art that the power bare chip is mounted on the first carrier 100 by solder balls or copper pillars, and can achieve the same or similar technical effects, and the description of the embodiment is omitted here.
It can be understood that, when the power bare chip 1010 is mounted on the first carrier 100 through a solder ball or a copper pillar, the power bare chip 1010 is electrically connected to the signal line on the first carrier 100 through the solder ball or the copper pillar.
Specifically, the first carrier 100 may be a Printed Circuit Board (PCB), a package substrate or a Quad Flat No-lead package (QFN) frame.
The second carrier 11 is disposed opposite to the second surface of the first carrier 100, and is used for mounting the first package 10, so that the first package 10 is communicated with an external device through the second carrier 11. Specifically, the first carrier 100 is close to a side surface of the second carrier 11, that is, the second surface is further provided with a first flow post 103a, and the second carrier 11 is provided with a communicating member 110 at a position opposite to the first flow post 103a, in a specific implementation process, one end of the first flow post 103a is connected to the first carrier 100, and the other end is attached to the communicating member 110 on the first carrier 100, so as to attach the first package 10 to the second carrier 11, and enable the electronic component 101 on the first package 10 to communicate with an external device through the first flow post 103a and the communicating member 110 on the second carrier 11.
Specifically, the first flow post 103a is in communication with a signal line on the first carrier board 100, and the electronic component 101 is in communication with an external device through the first carrier board 100 and the first flow post 103 a.
It is understood that the electronic component 101 on the first package 10 is communicated with the communication part 110 on the second carrier 11 through the first flow post 103a, and the external device is also communicated with the communication part 110 on the second carrier 11, so that the electronic component 101 on the first package 10 is communicated with the external device through the first flow post 103a and the communication part 110 on the second carrier 11.
Specifically, the second carrier 11 may be a metal plate; specifically, the second carrier 11 may be a copper plate.
Compared with the transverse size of the communication piece in the prior art, the transverse size of the communication piece 110 is larger, and the heat dissipation efficiency is effectively improved; and the transverse dimension of the communicating piece 110 in the application is larger than that of the first through-flow column 103a, so that the alignment precision between the two can be effectively improved in the specific mounting process, and the through-flow capacity is further improved.
The second package layer 12 covers a side surface of the first package 10 away from the second carrier 11, and cooperates with the second carrier 11 to package the first package 10, so as to protect the first package 10.
Specifically, the material of the first encapsulation layer 102 and the second encapsulation layer 12 may be a mixture of epoxy resin and silicon dioxide.
In the package structure 1 provided by this embodiment, by providing the first package body 10, the first package body 10 is configured to include the first carrier 100, the electronic component 101 attached to two surfaces of the first carrier 100, and the first package layer 102, wherein the first package layer 102 covers a side surface of the electronic component 101 away from the first carrier 100 and is matched with the first carrier 100 to package the electronic component 101, so that the electronic component 101 can be effectively prevented from directly contacting the atmosphere, and the electronic component 101 can be protected; meanwhile, by arranging the second carrier 11, arranging the first flow post 103a on the surface of the first carrier 100 close to one side of the second carrier 11, and arranging the communicating member 110 at a position of the second carrier 11 opposite to the first flow post 103a, so as to attach the first package 10 to the communicating member 110 through the first flow post 103a, the electronic component 101 on the first package 10 is communicated with an external device through the communicating member 110 on the second carrier 11; in addition, the transverse size of the communication piece 110 in the application is larger than that of the communication piece in the prior art, so that the heat dissipation capacity is effectively improved; the transverse dimension of the communicating piece 110 is larger than that of the first through flow column 103a, so that the first through flow column 103a and the communicating piece 110 can be well aligned in the mounting process, and the through flow capacity of a product can be effectively improved; in addition, the second package layer 12 is disposed on a side surface of the first package 10 away from the second carrier 11, and the second package layer 12 cooperates with the second carrier 11 to package the first package 10, so as to protect the first package 10.
In this embodiment, the via 110 may be specifically a pad, and the pad includes a first pad 1100 and a second pad 1101.
The first pad 1100 is used for mounting the first through-flow column 103a, so as to mount the first package 10 on the second carrier 11. Specifically, the lateral dimension of the first pad 1100 is greater than the lateral dimension of the first flow post 103a, so as to improve the alignment accuracy of the first flow post 103a and the first pad 1100 in the mounting process, and further improve the flow capacity.
Specifically, the number of the first flow columns 103a is at least two, and the number of the first flow columns 103a is the same as the number of the first pads 1100.
Wherein the second pads 1101 are used for mounting the electronic components 101 disposed on a surface of the first carrier 100 on a side close to the second carrier 11, i.e., for mounting the second electronic components. Specifically, referring to fig. 1, in one embodiment, the second pads 1101 are used for mounting an inductor disposed on a surface of the first carrier board 100 near one side of the second carrier board 11.
In a specific embodiment, the thickness of the second electronic component is the same as that of the first flow post 103a, and a surface of the second electronic component, which is away from the first carrier 100, exposes the second encapsulation layer 12 to be connected to the second carrier 11; it is understood that, in this embodiment, the electronic component 101 mounted on the surface of the first carrier 100 near the side of the second carrier 11 is directly mounted on the second pad 1101 to perform a certain current flowing function, so as to conduct the electronic component 101 with external equipment, thereby further improving the current flowing capability.
In another embodiment, referring to fig. 1, the thickness of the second electronic component is less than the length of the first flow post 103 a; the package structure 1 further includes a second flow post 103 b; one end of the second flow through post 103b is connected to a side surface of the second electronic component away from the first carrier board 100, and the other end is connected to the connecting member 110 on the second carrier board 11, that is, connected to the second pad 1101 on the second carrier board 11, so as to directly connect the second electronic component with the second carrier board 11 through the second flow through post 103b, thereby improving the flow guiding capability; the transverse dimension of the second through-flow column 103b is smaller than that of the communicating piece 10, so that the alignment precision and the through-flow capacity of the two are improved.
In the implementation, the current capacity is further improved by mounting a part of the inductor on the surface of the first carrier 100 close to the second carrier 11 and by mounting a part of the inductor on the second pad 1101.
Specifically, the lateral dimension of the second pad 1101 is greater than the lateral dimension of the electronic component 101 attached to the surface of the first carrier 100 near the second carrier 11, and specifically, the lateral dimension of the second pad 1101 is greater than the lateral dimension of a part of the inductor attached to the surface of the first carrier 100 near the second carrier 11, so that not only the heat dissipation capability can be improved, but also better alignment between the electronic component 101 and the second pad 1101 can be realized, and further the current capacity can be further improved.
Specifically, there are at least two first flow-through posts 103a, and at least two first flow-through posts 103a are disposed along the edge of the first carrier plate 100; and in one embodiment, referring to fig. 3, at least two first pass columns 103a are distributed on opposite sides of a second pass column 103 b.
Specifically, the communication members 110 are formed by a PCB etching process, and the number and the positions of the communication members 110 correspond to the number and the positions of the first flow columns 103a and the second flow columns 103 b; in an embodiment, there are at least two first pads 1100, and the at least two first pads 1100 are uniformly distributed on both sides of the second pad 1101.
Referring to fig. 3, in an embodiment, eight first pads 1100 are provided, and the eight first pads 1100 are uniformly distributed on two sides of the second pad 1101 in two rows. It is understood that, in the present embodiment, eight first flow pillars 103a are also provided, and the number and positions of the eight first flow pillars 103a correspond to those of the first pads 1100 one by one.
Referring to fig. 1 to 7, fig. 7 is a schematic flow chart illustrating a manufacturing method of a package structure according to an embodiment of the present application; in the present embodiment, a method for manufacturing a package structure is provided, and the package structure 1 according to the above embodiment is specifically manufactured by the following method for manufacturing a package structure.
Specifically, the manufacturing method comprises the following steps:
step S11: and providing a first carrier plate and a second carrier plate, wherein the second carrier plate is provided with a communicating piece.
The first carrier 100 may be a printed circuit board, the second carrier 11 may be a metal plate, such as a copper plate, and the structure of the second carrier 11 can be specifically shown in fig. 3; in the specific implementation process, providing a metal copper plate, and then etching the second carrier plate 11 by adopting a PCB etching process according to a preset pattern to obtain a metal copper frame with a communicating piece 110; by adopting the method to manufacture the metal copper frame, the size of the communicating piece 110 is easy to realize, the processing cost is low, and the reliability of the plastic packaged finished product is high.
Specifically, the via 110 is a pad including a first pad 1100 and a second pad 1101. In a specific implementation process, the number of the first pads 1100 is at least two, and the at least two first pads 1100 are uniformly distributed on two sides of the second pad 1101.
Specifically, the first carrier 100 is provided with signal lines and pads electrically connected to pins of the electronic component 101.
In a specific implementation, the first carrier 100 and the second carrier 11 are stacked.
Step S12: a first electronic component is pasted on the first surface of the first carrier plate, and a second electronic component and a first through flow column are pasted on the second surface of the first carrier plate to form a first packaging body.
Specifically, the schematic structural diagram of the product obtained through step S12 can be seen in fig. 2.
Specifically, after a first electronic component is mounted on a first surface of the first carrier 100, the first electronic component is subjected to primary plastic package to form a first package layer 102; then, a second electronic component and a first through-flow column 103a are attached to a second surface of the first carrier 100, and then the first package layer 102 and the first carrier 100 are cut to form a plurality of first packages 10; the first electronic component comprises one or any combination of a resistor, an inductor, a capacitor, a chip and a power bare chip; the second electronic component may comprise an inductor.
In an embodiment, the thickness of the second electronic component is the same as the length of the first flow post 103a, and an end of the second electronic component away from the first carrier 100 is exposed out of the second package layer 12 to be connected to the second carrier 11.
In another embodiment, the thickness of the second electronic component is less than the length of the first flow column 103 a; after the step of mounting the second electronic component and the first flow post 103a on the second surface of the first carrier 100, the method further comprises: a second flow through post 103b is attached to the surface of the second electronic component far from the first carrier 100 to form a first package 10; wherein the transverse dimension of the second flow post 103b is smaller than the transverse dimension of the communicating member 110.
Step S13: attaching the first packaging body to the second carrier plate, and connecting the first through-flow column with the communicating piece; wherein the transverse dimension of the first through-flow column is smaller than that of the communicating piece.
Specifically, the schematic structural diagram of the product obtained through step S13 can be seen in fig. 1.
Specifically, a plurality of first package bodies 10 are attached to a second carrier 11, and a second plastic package is performed on the plurality of first package bodies 10 to form a second package layer 12, and then the second package layer 12 and the second carrier 11 are cut to form a plurality of package structures 1; wherein, a first through-flow column 103a and/or a second through-flow column 103b is disposed on a side surface of the first carrier 100 close to the second carrier 11, a communication member 110 is disposed at a position of the second carrier 11 opposite to the first through-flow column 103a and/or the second through-flow column 103b, a transverse dimension of the first through-flow column 103a and/or the second through-flow column 103b is smaller than a transverse dimension of the communication member 110, and the first through-flow column 103a and/or the second through-flow column 103b are attached to the communication member 110, so as to attach the first package 10 to the second carrier 11.
Specifically, a plurality of first packages 10 may be mounted on the second carrier 11 by soldering.
Specifically, the injection molding equipment can be used for carrying out secondary plastic package on the first package body 10; and the first plastic package and the second plastic package can be both plastic packaged by adopting a mixture of epoxy resin and silicon dioxide.
In an embodiment, the electronic component 101 may be connected to a pad on the first carrier 100 through solder paste, so as to attach the electronic component 101 to the first carrier 100. And the electronic component 101 can be subjected to primary plastic package by adopting injection molding equipment.
Specifically, the number and the position of the first through-flow pillars 103a and/or the second through-flow pillars 103b correspond to the number and the position of the first pads 1100.
It is understood that, multiple sets of electronic components 101 may be attached to the first carrier 100, and in a specific implementation process, a position where each set of electronic components 101 is located needs to be cut to form multiple first packages 10.
Referring to fig. 8, fig. 9a and fig. 9b, wherein fig. 8 is a schematic diagram of a detailed flow of step S13 in fig. 7, and fig. 9a is a schematic diagram of a product structure corresponding to step S130 in fig. 8; FIG. 9b is a schematic diagram of a product structure corresponding to step S131 in FIG. 8; step S13 specifically includes:
step S130: and attaching the first packaging body to a second carrier plate through the first through-flow column and carrying out secondary plastic packaging to form a second packaging layer.
Specifically, the structure of the product obtained through step S130 can be specifically seen in fig. 9 a.
Specifically, the first through-flow column 103a of the first package 10 is attached to the first pad 1100, and the electronic component 101 on the surface of the first carrier 100 close to one side of the second carrier 11, that is, the second electronic component is attached to the second pad 1101, so as to attach the first package 10 to the second carrier 11; of course, when the thickness of the second electronic component is smaller than the length of the first flow column 103a, the second electronic component is mounted on the second pad 1101 by the second flow column 103 b.
Specifically, the lateral dimension of the first flow post 103a is smaller than that of the first pad 1100, and the lateral dimension of the second flow post 103b is smaller than that of the second pad 1101, so that the alignment accuracy between the first flow post and the second flow post is improved in a specific mounting process, and the flow capacity is improved.
Specifically, a surface of the second carrier 11 away from the first carrier 100 is metallurgically treated to prevent the second carrier 11 from being oxidized when exposed to the atmosphere.
Step 131: and cutting the second packaging layer and the second carrier plate to form a plurality of packaging structures.
Specifically, the structure of the product manufactured in step S131 can be specifically seen in fig. 9 b.
It can be understood that a plurality of groups of pads are disposed on the second carrier 11, each first package 10 corresponds to one group of pads, in a specific manufacturing process, the plurality of first packages 10 are mounted on the second carrier 11, then the plurality of first packages 10 are subjected to a second plastic package to form a second package, and finally the second package is cut at a position corresponding to each group of pads to form the plurality of package structures 1.
In the manufacturing method of the package structure provided by this embodiment, the first carrier 100 and the second carrier 11 are provided, the electronic component 101 is mounted on the first carrier 100 and is subjected to plastic package to form the first package 10, so that the electronic component 101 can be effectively prevented from contacting the atmosphere, and the electronic component 101 is protected; meanwhile, the first package 10 is packaged on the second carrier 11, so that the first package 10 can be effectively prevented from contacting the atmosphere, and the second package can be protected; in addition, since the first flow post 103a is disposed on a side surface of the first carrier 100 close to the second carrier 11, the connecting member 110 is disposed at a position of the second carrier 11 opposite to the first flow post 103a, and the first flow post 103a is attached to the connecting member 110, so as to attach the first package 10 to the second carrier 11, and enable the electronic component 101 on the first package 10 to communicate with an external device through the connecting member 110 on the second carrier 11; in addition, the transverse size of the communication piece 110 in the application is larger than that of the communication piece in the prior art, so that the heat dissipation capacity is effectively improved; and because the transverse dimension of the communicating piece 110 is larger than that of the first through-flow column 103a, the first through-flow column 103a and the communicating piece 110 can realize better alignment in the mounting process, and the through-flow capacity is further effectively improved.
The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.

Claims (9)

1. A package structure, comprising:
the first carrier plate is provided with a first surface and a second surface opposite to the first surface;
the first electronic component is attached to the first surface of the first carrier plate;
the second electronic component is attached to the second surface of the first carrier plate;
the second carrier plate is arranged opposite to the second surface of the first carrier plate, and a communicating piece is arranged on the surface of the second carrier plate facing the first carrier plate;
one end of the first through flow column is connected with the second surface of the first carrier plate, and the other end of the first through flow column is connected with the communicating piece on the second carrier plate; and the transverse dimension of the first through-flow column is smaller than that of the communicating piece.
2. The package structure of claim 1, further comprising:
the first packaging layer is arranged on the first surface of the first carrier plate and is matched with the first carrier plate to package the first electronic component;
and the second packaging layer is arranged on the surface of one side, facing the first carrier plate, of the second carrier plate and is matched with the second carrier plate to package the second electronic component, the first through flow column and the first packaging layer.
3. The package structure according to claim 2, wherein a thickness of the second electronic component is the same as a length of the first flow post, and a surface of the second electronic component facing away from the first carrier board exposes the second encapsulation layer to be connected to the second carrier board.
4. The package structure according to claim 2, wherein a thickness of the second electronic component is smaller than a length of the first flow column;
the packaging structure further comprises a second through-flow column; one end of the second flow through column is connected with the surface of one side, away from the first carrier plate, of the second electronic component, and the other end of the second flow through column is connected with a communicating piece on the second carrier plate; and the transverse dimension of the second flow through column is smaller than that of the communicating piece.
5. The package structure of claim 4, wherein the number of the first through-flow posts is at least two, and at least two of the first through-flow posts are disposed along an edge of the first carrier.
6. The package structure of claim 5, wherein at least two of the first flow posts are distributed on opposite sides of the second flow post.
7. The package structure according to claim 6, wherein the communication members are formed by an etching process, and the number and the positions of the communication members correspond to those of the first flow post and the second flow post.
8. The package structure of claim 1, wherein the first electronic component comprises one or more of a resistor, a capacitor, a chip, a power bare chip, and an inductor; the second electronic component includes an inductor.
9. The package structure of claim 1, wherein the first carrier is a printed circuit board and the second carrier is a metal plate.
CN202022376318.3U 2019-10-28 2020-10-22 Packaging structure Active CN214043658U (en)

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US9111896B2 (en) * 2012-08-24 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package semiconductor device
US8872326B2 (en) * 2012-08-29 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional (3D) fan-out packaging mechanisms
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US9799590B2 (en) * 2013-03-13 2017-10-24 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in package
US20170213801A1 (en) * 2016-01-22 2017-07-27 Micron Technology, Inc. Method for manufacturing a package-on-package assembly
US10325828B2 (en) * 2016-03-30 2019-06-18 Qorvo Us, Inc. Electronics package with improved thermal performance

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