CN214043650U - Package body - Google Patents

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Publication number
CN214043650U
CN214043650U CN202023045333.6U CN202023045333U CN214043650U CN 214043650 U CN214043650 U CN 214043650U CN 202023045333 U CN202023045333 U CN 202023045333U CN 214043650 U CN214043650 U CN 214043650U
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China
Prior art keywords
package
chip
insulating layer
layer
packaging
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Application number
CN202023045333.6U
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Chinese (zh)
Inventor
吴畏
阳小芮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Kaihong Electronic Co Ltd
Diodes Shanghai Co Ltd
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Diodes Shanghai Co Ltd
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Priority to CN202023045333.6U priority Critical patent/CN214043650U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A packaging body comprises a chip and a plurality of pins, wherein the chip and each pin are encapsulated in a plastic packaging layer and are electrically connected through a bonding wire, an insulating layer is arranged on one surface of the chip, and one surface of the insulating layer and one surface of each pin are exposed by the plastic packaging layer; and the material of the insulating layer is thermosetting resin.

Description

Package body
Technical Field
The present disclosure relates to semiconductor packages, and particularly to a package and a method for manufacturing the package.
Background
QFN packages are commonly used package structures. Fig. 1 shows a conventional QFN package structure. As shown in fig. 1. The conventional QFN package 1 includes: the die 4 is attached to a support pad (base island) 3 by an adhesive 2. The chip 4 is in turn supported on the support pad 3 for fixation during packaging, to facilitate the process of forming the bonding wires 5. Finally, the package body is obtained after the package body is packaged by the plastic package layer 6.
At present, aiming at the requirements of light weight, thinness, small size and the like of electronic products, further requirements are put forward on the size of a packaging body, and particularly, thinner requirements are put forward on the thickness aspect of the packaging body.
However, in the package 1 shown in fig. 1, due to the existence of the supporting pad 3, the thickness of the supporting pad itself increases the overall thickness of the package 1, and also raises the wire loop of the bonding wire 5, so that the thickness of the package 1 cannot be further reduced.
In addition, since the supporting pad 3 is used to support and fix the chip 4 during the packaging process of the package, the thickness of the package 1 shown in fig. 1 cannot be further reduced by the conventional package structure and packaging method.
Therefore, there is a need to provide a new package to overcome the above-mentioned drawbacks.
SUMMERY OF THE UTILITY MODEL
The present application provides a package and a method for manufacturing the package, in which a metal core pad (or called a "base island") of a chip in the package is removed to obtain an ultra-thin package.
In order to achieve the above object, according to an aspect of the present application, a package is provided, which includes a chip encapsulated in a molding layer and a plurality of leads, wherein the chip is electrically connected to each of the leads through a bonding wire; an insulating layer is arranged on one surface of the chip, and the plastic packaging layer exposes one surface of the insulating layer and one surface of each pin; wherein the insulating layer is made of thermosetting resin.
In some embodiments, the thermosetting resin is one or more of epoxy resin, unsaturated polyester resin, phenolic resin, melamine formaldehyde resin or furan resin.
In some embodiments, the insulating layer has a thickness of 15 μm to 50 μm.
In some embodiments, the plurality of pins are disposed around the chip, and at least one pin extends toward the chip toward an end of the chip to form a terminal; the terminals are encapsulated in the plastic package layer.
According to another aspect of the present application, there is also provided a manufacturing method of a package, the manufacturing method including:
providing a bearing substrate;
forming a patterned metal layer on the bearing substrate to form a plurality of pins;
providing a wafer with a functional surface and a back surface opposite to the functional surface, forming an insulating layer on the back surface of the wafer, and cutting to form a plurality of chips provided with the insulating layers;
attaching the chip provided with the insulating layer to the bearing substrate;
forming a plurality of bonding wires so that the chip is electrically connected with each pin through one bonding wire; and the number of the first and second groups,
and forming a plastic packaging layer to encapsulate the chip, the bonding wires and the pins, and removing the bearing substrate to expose a surface of the insulating layer and a surface of each pin.
In some embodiments, after the step of removing the carrier substrate, the manufacturing method further comprises: and cutting to form a single packaging body.
In some embodiments, in the step of forming a patterned metal layer on the carrier substrate, the patterned metal layer is formed by electroplating.
In some embodiments, in the step of forming the patterned metal layer on the carrier substrate, the patterned metal layer is formed by two-step electroplating to form a plurality of pins, so that a projected area of a surface of at least one pin away from the carrier substrate on the carrier substrate is larger than a projected area of a surface of the pin contacting the carrier substrate on the carrier substrate.
In some embodiments, in the step of forming an insulating layer on the back surface of the wafer, the insulating layer is formed by coating a thermosetting resin on the back surface of the wafer and thermally curing; the thickness of the insulating layer is 15-50 μm.
In some embodiments, the thermosetting resin is one or more of epoxy resin, unsaturated polyester resin, phenolic resin, melamine formaldehyde resin or furan resin.
In the application, through setting the insulating layer and the thermosetting characteristic thereof, the chip is supported by the base island of the lead frame in the packaging process of the packaging body without the packaging step like a conventional packaging body, so that the base island in the finally obtained packaging body structure is eliminated, the thickness of the packaging body is greatly reduced, the radian of a bonding wire is reduced, and the ultrathin packaging body can be obtained. In addition, in the preparation method of the package body, the plurality of pins are formed in an electroplating mode, the thickness of the formed pins can be accurately controlled according to requirements, and the forming of the ultrathin package body is facilitated.
Drawings
In order to more clearly illustrate the features of particular embodiments of the present invention, reference will now be made briefly to the accompanying drawings of embodiments. It is obvious that the drawings described below are only some embodiments of the invention, and that other similar pictures can be obtained from these drawings without inventive effort for a person of ordinary skill or practice in the art.
FIG. 1 is a schematic diagram of a conventional package product;
fig. 2 is a schematic structural diagram of a package according to an embodiment of the present application;
fig. 3 is a flow chart of a method of fabricating a package according to an embodiment of the present application;
fig. 4A to 4E are schematic structural diagrams corresponding to fig. 3.
Detailed Description
The present invention will be further described with reference to the following specific examples. It is obvious that the described embodiments are only a part of the application of the invention, and not all. It is to be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of the present invention.
As shown in fig. 2, in the present embodiment, a package 100 is provided, which includes: the chip package comprises a chip 110, a plurality of pins 120, and a molding compound layer 130 encapsulating the chip 110 and the plurality of pins 120.
Specifically, as shown in fig. 2, in the package 100, the plurality of leads 120 are disposed around the chip 110, and each of the leads 120 is electrically connected to the chip 110 through a bonding wire 140. As shown in fig. 2, in order to achieve the mode-locking effect, each pin 120 extends toward the chip 110 toward one end of the chip 110 to form a terminal 121, and the terminal 121 is also encapsulated in the molding layer 130.
In this embodiment, the package 100 may be a QFN package. In order to obtain an ultra-thin package, as shown in fig. 1 and 2, the package body 100 of the present application eliminates a substrate for mounting the chip 110, and an insulating layer 150 is disposed on one surface 110a of the chip 110. The insulating layer 150 is arranged to satisfy: the molding compound layer 130 exposes a surface 150a of the insulating layer 150 and a surface 120a of each lead 120. That is, a surface 100a of the package body 100 exposes the surface 150a of the insulating layer 150 and the surface 120a of each lead 120. As shown in fig. 2, the lower surface of the package 100 (i.e., the mounting surface of the package) exposes the surface 150a of the insulating layer 150 and the surface 120a of each lead 120.
In consideration of the thickness of the package 100, the thickness of the insulating layer 150 is 15 μm to 50 μm.
The insulating layer is made of thermosetting resin, and can be one or a mixture of epoxy resin, unsaturated polyester resin, phenolic resin, melamine formaldehyde resin or furan resin. It will be appreciated by those skilled in the art that in the present application, the material of the insulating layer may be a material known in the art that is heat curable, particularly a double sided adhesive material that is heat curable, such as, but not limited to, LOCTITE ablestak 8006NS epoxy. When selecting the material of the insulating layer, the cured insulating layer may have characteristics similar to those of a conventional ABF carrier (Ajinomot Build-up Film).
Therefore, in the package 100 of the present application, by providing the insulating layer and the thermal curing property thereof, it is not required to support the chip 120 by using the base island of the lead frame in the packaging process of the package 100 like in the packaging step of the conventional package, so that the base island in the finally obtained package 100 structure is eliminated, the thickness of the package is greatly reduced, and the ultra-thin package is obtained.
Hereinafter, the method for manufacturing the package 100 will be described in detail with reference to fig. 3 and 4A to 4E.
As shown in fig. 3 and 4A, the method for manufacturing the package 100 includes step S1: a carrier substrate SP is provided, and a patterned metal layer M is formed on the carrier substrate SP to form a plurality of leads 120. It will be appreciated by a person skilled in the art that in this step the metal layer M may be patterned on the carrier plate SP by methods known in the art, such as electroplating, deposition, etc. The carrier substrate SP may be a conventional carrier substrate used in the art for package packaging. As an exemplary example and not limiting the application, in this step, a carbon steel plate is used as the carrier substrate SP. Meanwhile, considering that the metal frame (lead frame) of the ultra-thin QFN product is rather thin, it is difficult to make the molding by the conventional direct copper plate etching, and therefore, in this step, the patterned metal layer M is formed by copper plating on the carbon steel plate as the carrier substrate SP. In this step, the thickness of the copper plating is approximately < ═ 0.1 mm.
Further, in this step, in order to realize the formation of a terminal 121 at one end of each lead 120 as shown in fig. 1, the terminal 121 is formed by two-step copper plating in this step.
As shown in fig. 3 and 4B, the method for manufacturing the package 100 includes step S2: a chip 110 with an insulating layer 150 attached thereto is provided. It will be appreciated by those skilled in the art that the chip 110 enriched with the insulating layer 150 can be obtained by any method known in the art. As an exemplary example and not limiting to the present application, in the present step, a wafer W having a functional surface S and a back surface opposite to the functional surface S is first provided, an insulating layer 150 is formed on the back surface of the wafer W, and a plurality of chips 110 provided with the insulating layer 150 are formed after dicing.
As shown in fig. 3 and 4C, the method for manufacturing the package 100 includes step S3: the chip 110 provided with the insulating layer 150 is attached to the carrier substrate SP. It will be understood by those skilled in the art that the chip 110 provided with the insulating layer 150 may be attached to the carrier substrate SP by any method known in the art. For example, in this step, the chip 110 is attached to the carrier substrate SP by using a conventional die bonder.
As shown in fig. 3 and 4D, the method for manufacturing the package 100 includes step S4: a plurality of bonding wires 140 are formed such that the chip 110 and each of the leads 120 are electrically connected by a bonding wire 140. It will be appreciated by those skilled in the art that the plurality of bond wires 140 can be formed by any method known in the art.
As shown in fig. 3 and 4E, the method for manufacturing the package 100 includes step S4: a molding compound layer 130 is formed to encapsulate the chip 110, the bonding wires 140 and the leads 120, and the carrier substrate SP is removed, so that the molding compound layer 130 exposes a surface 150a of the insulating layer 150 and a surface 120a of each lead 120. After dicing in a conventional dicing step, a single package 100 as shown in fig. 2 can be obtained.
The present application has been described in relation to the above embodiments, which are only examples for implementing the present application. It must be noted that the disclosed embodiments do not limit the scope of the application. Rather, modifications and equivalent arrangements included within the spirit and scope of the claims are included within the scope of the present application.

Claims (3)

1. A packaging body comprises a chip and a plurality of pins, wherein the chip and each pin are encapsulated in a plastic packaging layer and are electrically connected through a bonding wire; wherein the insulating layer is made of thermosetting resin.
2. The package of claim 1, wherein the insulating layer has a thickness of 15 μ ι η to 50 μ ι η.
3. The package of claim 1, wherein the plurality of leads are disposed around the chip, and wherein at least one lead extends toward the chip toward an end of the chip to form a terminal; the terminals are encapsulated in the plastic package layer.
CN202023045333.6U 2020-12-16 2020-12-16 Package body Active CN214043650U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202023045333.6U CN214043650U (en) 2020-12-16 2020-12-16 Package body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202023045333.6U CN214043650U (en) 2020-12-16 2020-12-16 Package body

Publications (1)

Publication Number Publication Date
CN214043650U true CN214043650U (en) 2021-08-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
CN (1) CN214043650U (en)

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