CN214011778U - Pulse signal acquisition system based on FPGA - Google Patents

Abstract

A pulse signal acquisition system based on an FPGA (field programmable gate array) comprises a high-speed ADC (analog to digital converter), an FPGA board card and a PC (personal computer) terminal, wherein the FPGA board card comprises an FPGA, a DDR3, an SD (secure digital) card, a USB (universal serial bus) channel and a gigabit Ethernet channel, the high-speed ADC is connected with the FPGA, the FPGA is respectively connected with the DDR3 and the SD card, the FPGA is respectively connected with the PC terminal through the USB channel and the gigabit Ethernet channel, and the gigabit Ethernet can be selectively used by the FPGA for real-time data transmission; or the data storage is realized by using the SD card, and the data transmission is realized by reading the data of the SD card by a computer, so that the flexibility is stronger.

Description

Pulse signal acquisition system based on FPGA

Technical Field

The utility model relates to a pulse signal gathers the field, in particular to pulse signal collection system based on FPGA.

Background

The pulse signal is a discrete signal, and the pulse signal is represented on a plane coordinate, namely, a curve with countless break points, that is, the limit of some points in the periodicity does not exist, such as a sawtooth wave, and signals 0 and 1 of a digital circuit used in a computer. Pulse signals, namely pulse beating signals, are intermittent signals relative to direct current, and if the signals are water flow shapes, the direct current enables the faucet to be always opened for water flowing, and the pulse is the water pulse formed by continuously opening and closing the faucet. The pulse signal has various shapes, and compared with common analog signals (such as sine waves), the pulse signal has the characteristics that the waveforms are discontinuous on the Y axis (obvious intervals exist between the waveforms) and have certain periodicity. The most common pulse wave is a rectangular wave (i.e., a square wave). The pulse signal can be used to represent information, can also be used as a carrier wave, such as Pulse Code Modulation (PCM) in pulse modulation, Pulse Width Modulation (PWM), and the like, and can also be used as a clock signal for various digital circuits and high-performance chips.

The existing pulse signal acquisition scheme, as the patent publication number is CN106019350A, is a nuclear pulse signal acquisition device and system, and comprises an FPGA processing module and at least one signal acquisition circuit; the signal acquisition circuit comprises a following amplifying circuit and an ADC (analog to digital converter) sampling circuit which are sequentially connected; the following amplifying circuit is connected with the radiation detection device and used for receiving the nuclear pulse signals acquired by the radiation detection device, and inputting the input signals into the ADC sampling circuit after impedance matching and amplitude adjustment are carried out on the input signals; the ADC sampling circuit converts the nuclear pulse analog signal into a nuclear pulse digital signal according to a preset sampling frequency in a pipeline sampling mode; the FPGA processing module is used for enabling and controlling each signal acquisition circuit and providing sampling frequency for an ADC sampling circuit in each signal acquisition circuit; the FPGA processing module is also used for receiving the nuclear pulse digital signals output by the ADC sampling circuit, and the nuclear pulse digital signals are firstly stored in the FIFO module and then output to the upper computer by the FIFO module. This prior art employs a single data transmission scheme. In practical situations, due to environmental conditions, some need to be transmitted in real time, and some need to be stored before transmission. Therefore, there is a need for a pulse signal acquisition system with more flexibility that can select real-time transmission or storage-before-transmission.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a: the FPGA-based pulse signal acquisition system comprises a high-speed ADC, an FPGA board card and a PC (personal computer) terminal, and can selectively use a gigabit Ethernet for real-time data transmission through the FPGA; or the data storage is realized by using the SD card, and the data transmission is realized by reading the data of the SD card by a computer, thereby solving the problems.

The utility model adopts the technical scheme as follows:

the utility model provides a pulse signal acquisition system based on FPGA, includes high-speed ADC, FPGA integrated circuit board and PC end, the FPGA integrated circuit board includes FPGA, DDR3, SD card, USB passageway and gigabit Ethernet passageway, high-speed ADC and FPGA are connected, FPGA is connected with DDR3, SD card respectively, FPGA is connected with the PC end through USB passageway and gigabit Ethernet passageway respectively.

In order to better implement the scheme, the FPGA further includes a FIFO1 and a FIFO2, the FIFO1 and the FIFO2 are respectively connected to the DDR3, and digital data transmitted from the high-speed ADC to the FPGA is preprocessed by the FPGA and then stored in the FIFO1 for buffering.

In order to better implement the scheme, the FIFO2 is connected with the SD card, and the data temporarily stored in the DDR3 is stored in the SD card or the PC according to actual requirements.

In order to better implement the present solution, the FIFO2 is further connected to the PC terminal through a USB channel and a gigabit ethernet channel, respectively.

According to the scheme, the high-speed ADC converts pulse analog quantity into digital quantity and transmits the digital quantity to the FPGA, the FPGA preprocesses data and stores the data into the FIFO1 for caching, then reads data in the FIFO1 and writes the data into the external memory DDR3 for storage, after collection and storage are finished, reads data in the DDR3 and writes the data into the FIFO2 for caching, then reads data in the FIFO2, according to different requirements, the data can be selectively written into an SD card for storage or directly transmitted to a PC end through a gigabit Ethernet channel for storage, and further according to different requirements, the communication between the USB channel or the gigabit Ethernet and the PC end is selected.

To sum up, owing to adopted above-mentioned technical scheme, the beneficial effects of the utility model are that:

1. the utility model discloses a pulse signal acquisition system based on FPGA, including high-speed ADC, FPGA integrated circuit board and PC end, can select to use gigabit Ethernet to carry out data real-time transmission through FPGA; or the data storage is realized by using the SD card, and the data transmission is realized by reading the data of the SD card by a computer, so that the flexibility is stronger;

2. the utility model discloses a pulse signal acquisition system based on FPGA, including high-speed ADC, FPGA integrated circuit board and PC end, can select to use gigabit Ethernet to carry out data real-time transmission through FPGA; or the data storage is realized by using the SD card, the data transmission is realized by reading the data of the SD card through a computer, the system frame is simple, various specific circuits can be used, and the practicability is high.

Drawings

In order to more clearly illustrate the technical solution, the drawings needed to be used in the embodiments are briefly described below, and it should be understood that, for those skilled in the art, other related drawings can be obtained according to the drawings without creative efforts, wherein:

fig. 1 is a block diagram of the present invention.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only some embodiments of the present invention, but not all embodiments, and therefore should not be considered as limitations to the scope of protection. Based on the embodiments in the present invention, all other embodiments obtained by the staff of ordinary skill in the art without creative work belong to the protection scope of the present invention.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The present invention will be described in detail with reference to fig. 1.

Example 1

The utility model provides a pulse signal acquisition system based on FPGA, includes high-speed ADC, FPGA integrated circuit board and PC end, the FPGA integrated circuit board includes FPGA, DDR3, SD card, USB passageway and gigabit Ethernet passageway, high-speed ADC and FPGA are connected, FPGA is connected with DDR3, SD card respectively, FPGA is connected with the PC end through USB passageway and gigabit Ethernet passageway respectively.

The working principle is as follows: in this embodiment, the high-speed ADC converts the pulse analog quantity into a digital quantity and transmits the digital quantity to the FPGA, the FPGA preprocesses the data and stores the data in the FIFO1 for buffering, then reads the data in the FIFO1 and writes the data in the external memory DDR3 for storage, after the acquisition and storage are completed, reads the data in the DDR3 and writes the data in the FIFO2 for buffering, then reads the data in the FIFO2, according to different requirements, the data can be written in the SD card for storage or directly transmitted to the PC end for storage through the gigabit ethernet channel, and further according to different requirements, the communication between the PC end and the USB channel or the gigabit ethernet channel is selected.

Example 2

In this embodiment, on the basis of embodiment 1, the FPGA includes a FIFO1 and a FIFO2, the FIFO1 and the FIFO2 are respectively connected to the DDR3, and digital data transmitted from the high-speed ADC to the FPGA is preprocessed by the FPGA and stored in the FIFO1 for buffering.

Furthermore, the FIFO2 is connected with the SD card, and the data temporarily stored in the DDR3 is stored into the SD card or the PC terminal according to actual requirements.

Further, the FIFO2 is connected to the PC terminal through a USB channel and a gigabit ethernet channel, respectively.

The working principle is as follows: in this embodiment, the high-speed ADC converts the pulse analog quantity into a digital quantity and transmits the digital quantity to the FPGA, the FPGA preprocesses the data and stores the data in the FIFO1 for buffering, then reads the data in the FIFO1 and writes the data in the external memory DDR3 for storage, after the acquisition and storage are completed, reads the data in the DDR3 and writes the data in the FIFO2 for buffering, then reads the data in the FIFO2, according to different requirements, the data can be written in the SD card for storage or directly transmitted to the PC end for storage through the gigabit ethernet channel, and further according to different requirements, the communication between the PC end and the USB channel or the gigabit ethernet channel is selected.

Other parts of this embodiment are the same as those of embodiment 1, and thus are not described again.

The above is only the preferred embodiment of the present invention, not to the limitation of the present invention in any form, all the technical matters of the present invention all fall into the protection scope of the present invention to any simple modification and equivalent change of the above embodiments.

Claims (4)

1. The utility model provides a pulse signal acquisition system based on FPGA, includes high-speed ADC, FPGA integrated circuit board and PC end, its characterized in that: the FPGA board card comprises an FPGA, a DDR3, an SD card, a USB channel and a gigabit Ethernet channel, the high-speed ADC is connected with the FPGA, the FPGA is respectively connected with the DDR3 and the SD card, and the FPGA is respectively connected with a PC end through the USB channel and the gigabit Ethernet channel.

2. The FPGA-based pulse signal acquisition system of claim 1, wherein: the FPGA comprises a FIFO1 and a FIFO2, the FIFO1 and the FIFO2 are respectively connected with a DDR3, and digital quantity data transmitted to the FPGA by the high-speed ADC is stored in the FIFO1 for buffering after being preprocessed by the FPGA.

3. The FPGA-based pulse signal acquisition system of claim 2, wherein: the FIFO2 is connected with the SD card, and the data temporarily stored in the DDR3 is stored in the SD card or the PC end according to actual requirements.

4. An FPGA-based pulse signal acquisition system according to claim 2 or 3, characterized in that: the FIFO2 is connected with the PC end through a USB channel and a gigabit Ethernet channel respectively.

Images