CN213903717U - Power chip fault representation structure - Google Patents
Power chip fault representation structure Download PDFInfo
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- CN213903717U CN213903717U CN202022438322.8U CN202022438322U CN213903717U CN 213903717 U CN213903717 U CN 213903717U CN 202022438322 U CN202022438322 U CN 202022438322U CN 213903717 U CN213903717 U CN 213903717U
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Abstract
The utility model discloses a power chip trouble shows structure is applied to the power chip including voltage conversion module, voltage conversion module's power input end and power output end, including operating voltage DC, operating voltage DC organizes ground connection through divider resistance R16 and divider resistance, wherein, divider resistance group includes a plurality of different identification resistance of resistance by the parallelly connected of field effect transistor control, the field effect transistor switches on by the control of fault detection unit, detects divider resistance R16 with voltage between the divider resistance group is in order to acquire the fault type. According to the invention, different identification resistors in the voltage dividing resistor group are connected through conduction of different field effect transistors during different faults, so that the voltage dividing values of the positions between the voltage dividing resistor R16 and the voltage dividing resistor group are different, and the fault occurrence reason can be determined according to the voltage dividing amount. The maintenance personnel can conveniently maintain the power supply chip according to the specific failure occurrence reason.
Description
Technical Field
The utility model relates to a power chip fault detection field especially relates to a power chip trouble shows structure.
Background
A power supply chip is a chip that plays roles in conversion, distribution, detection, and other power management of power in an electronic equipment system. The CPU power supply amplitude is mainly identified, corresponding short moment waves are generated, and a post-stage circuit is pushed to output power.
Many power chips all have a protection function, and when a fault occurs, the power chip has a special pin to do a pull-down or pull-up action, and the system judges whether the power chip works abnormally or not by acquiring a high level or low level signal of the corresponding pin. However, in this method, since the power chip abnormality is transmitted by a high-level or low-level signal, the cause of the abnormality cannot be accurately transmitted. However, in many cases, the specific reason of the power supply chip needs to be known in order to solve the problem of abnormal operation, and the current actions (sending high level or low level) of the chip after various faults occur are the same, so that the specific reason of the faults cannot be determined through the actions of the fault information transmission pins.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problems, the present invention provides a power chip failure indication structure, which is applied to a power chip comprising a voltage conversion module, wherein a power input end and a power output end of the voltage conversion module comprise a working voltage DC, the working voltage DC is grounded via a voltage dividing resistor R16 and a voltage dividing resistor set, wherein the voltage dividing resistor set comprises a plurality of identification resistors with different resistances controlled by field effect transistors in parallel connection,
the field effect transistor is controlled to be conducted by the fault detection unit,
and detecting the voltage between the voltage dividing resistor R16 and the voltage dividing resistor group to acquire the fault type.
Preferably, the fault detection unit includes an input current detection unit, an input voltage upper limit detection unit, an input voltage lower limit detection unit, and an output voltage detection unit.
Preferably, the input current detecting unit includes a detecting resistor R9, the detecting resistor R9 is connected in series between the power input terminal and the voltage converting module, and two ends of the detecting resistor R9 are electrically connected to two input terminals of a differential amplifier a 1; the reference voltage is grounded through a resistor R10 and a resistor R11, two input ends of a differential amplifier A2 are respectively connected with the output of the differential amplifier A1 and between the resistor R10 and the resistor R11, and the output end of the differential amplifier A2 is electrically connected with the grid of a field effect transistor Q1.
Preferably, the input voltage upper limit detection unit includes a differential amplifier A3, the power input terminal is grounded through a resistor R1 and a resistor R2, the reference voltage is grounded through a resistor R3 and a resistor R4, two input terminals of the differential amplifier A3 are respectively and electrically connected between the resistor R1 and the resistor R2, and between the resistor R3 and the resistor R4, and an output terminal of the differential amplifier A3 is electrically connected to a gate of the fet Q2.
Preferably, the input voltage lower limit detection unit includes a differential amplifier a4, the power input terminal is grounded through a resistor R5 and a resistor R6, the reference voltage is grounded through a resistor R7 and a resistor R8, two input terminals of the differential amplifier a4 are respectively and electrically connected between the resistor R5 and the resistor R6, and between the resistor R7 and the resistor R8, and an output terminal of the differential amplifier a4 is electrically connected to a gate of the fet Q3.
Preferably, the output voltage detection unit includes a differential amplifier a5, the power output terminal is grounded through a resistor R12 and a resistor R13, the reference voltage is grounded through a resistor R14 and a resistor R15, two input terminals of the differential amplifier a5 are respectively and electrically connected between the resistor R14 and the resistor R15, and between the resistors R12 and R13, and an output terminal of the differential amplifier a5 is electrically connected to a gate of the field effect transistor Q4.
Preferably, the voltage dividing resistor R16 and the voltage dividing resistor group are electrically connected to an analog-to-digital conversion device.
The power chip fault representation structure provided by the application has the following beneficial effects:
the utility model provides a power chip trouble shows structure passes through input current detecting element detects whether take place the trouble that input current overflows is judged with the partial pressure comparison of resistance R11 to the both ends voltage difference of detecting resistance R9, when the overcurrent fault of generating current, field effect transistor Q1 switches on and inserts identifying resistance R20, changes the voltage between divider resistance R16 and the divider resistance group. The input voltage upper limit detection unit compares the voltage difference between the resistor R2 and the resistor R4 to judge whether the input voltage overvoltage fault occurs, when the input overvoltage fault occurs, the field effect transistor Q2 is conducted to connect the identification resistor R19, and the voltage between the voltage dividing resistor R16 and the voltage dividing resistor group is changed. The input voltage lower limit detection unit compares the voltage difference between the resistor R6 and the resistor R8 to judge whether the input voltage undervoltage fault occurs, when the input undervoltage fault occurs, the field effect transistor Q3 is conducted to connect the identification resistor R18, and the voltage between the voltage dividing resistor R16 and the voltage dividing resistor group is changed. Whether the output voltage overvoltage fault occurs or not is judged by comparing the voltage division difference between the resistor R13 and the resistor R15 through the output voltage detection unit, and when the output overvoltage fault occurs, the field effect transistor Q4 is conducted to connect the identification resistor R17, so that the voltage between the voltage division resistor R16 and the voltage division resistor group is changed. Since the identification resistor R17, the identification resistor R18, the identification resistor R19, and the identification resistor R20 are different in resistance value, the divided voltage change amount is different so that the cause of the occurrence of the fault can be determined according to the divided voltage change amount. The maintenance personnel can conveniently maintain the power supply chip according to the specific failure occurrence reason.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic diagram of a power chip failure indication structure in an embodiment of the present invention.
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The present invention is described below with reference to the accompanying drawings, wherein fig. 1 is a schematic diagram of a power supply chip fault indication structure in an embodiment of the present invention.
The utility model provides a power chip trouble shows structure is applied to the power chip including voltage conversion module, voltage conversion module's power input end and power output end, including operating voltage DC, operating voltage DC is through divider resistance R16 and divider resistance group ground connection, wherein, the divider resistance group includes a plurality of parallelly connected different identification resistance of resistance by the field effect transistor control, the field effect transistor is switched on by the control of fault detection unit, specifically, as shown with reference to figure 1, the divider resistance group includes field effect transistor Q1, field effect transistor Q2, field effect transistor Q3 and field effect transistor Q4, field effect transistor Q1, field effect transistor Q2, field effect transistor Q3 and field effect transistor Q4's drain electrode electric connection the one end of divider resistance R16, field effect transistor Q1, field effect transistor Q2, field effect transistor Q3 and field effect transistor Q4's source ground connection, the gates of the field-effect transistor Q1, the field-effect transistor Q2, the field-effect transistor Q3 and the field-effect transistor Q4 are respectively and electrically connected with different fault detection units. The other end of the divider resistor R16 is electrically connected with a constant-voltage working voltage DC.
In a specific implementation process, the fault detection unit comprises an input current detection unit, an input voltage upper limit detection unit, an input voltage lower limit detection unit and an output voltage detection unit. As shown in fig. 1, the input current detecting unit includes a detecting resistor R9, the detecting resistor R9 is connected in series between the power input terminal and the voltage converting module, and two ends of the detecting resistor R9 are electrically connected to two input terminals of a differential amplifier a 1; the reference voltage is grounded through a resistor R10 and a resistor R11, two input ends of a differential amplifier A2 are respectively connected with the output of the differential amplifier A1 and between the resistor R10 and the resistor R11, and the output end of the differential amplifier A2 is electrically connected with the grid of a field effect transistor Q1. The resistance value of the detection resistor R9 is determined, the voltage difference between the two ends of the detection resistor R9 is used for representing the input current of the power input end to the voltage conversion module, and when the voltage difference between the two ends of the detection resistor R9 is determined
When the voltage is on, the field effect transistor Q1 is conducted. The input voltage upper limit detection unit comprises a differential amplifier A3, the power input end is grounded through a resistor R1 and a resistor R2, the reference voltage is grounded through a resistor R3 and a resistor R4, two input ends of the differential amplifier A3 are respectively and electrically connected between the resistor R1 and the resistor R2 and between the resistor R3 and the resistor R4, and the output end of the differential amplifier A3 is electrically connected with the grid of a field effect transistor Q2. When the voltage of the resistor R2 is divided
When the voltage is on, the field effect transistor Q2 is conducted. The input voltage lower limit detection unit comprises a differential amplifier A4, the power input end is grounded through a resistor R5 and a resistor R6, the reference voltage is grounded through a resistor R7 and a resistor R8, two input ends of the differential amplifier A4 are respectively and electrically connected between the resistor R5 and the resistor R6 and between the resistor R7 and the resistor R8, and the output end of the differential amplifier A4 is electrically connected with the grid of a field effect transistor Q3. When the resistor R6 divides voltage
When the voltage is on, the field effect transistor Q3 is conducted. The output voltage detection unit comprises a differential amplifier A5, the power output end is grounded through a resistor R12 and a resistor R13, the reference voltage is grounded through a resistor R14 and a resistor R15, two input ends of the differential amplifier A5 are respectively and electrically connected between the resistor R14 and the resistor R15 and between the resistor R12 and the resistor R13, and the output end of the differential amplifier A5 is electrically connected with the grid of a field effect transistor Q4. When the voltage of the resistor R2 is divided
When the voltage is on, the field effect transistor Q4 is conducted. Wherein KnDenotes the amplification factor, U, of the differential amplifier AnQnRepresents the on-voltage of the field effect transistor Qn, where n is 1, 2, 3, 4; u shapeRmThe voltage division of the resistance Rm is shown, and m is 2, 4, 6, 8, 13, 15.
And detecting the voltage between the voltage dividing resistor R16 and the voltage dividing resistor group to acquire the fault type. In a specific implementation process, an analog-to-digital conversion device is electrically connected between the voltage dividing resistor R16 and the voltage dividing resistor group, the voltage between the voltage dividing resistor R16 and the voltage dividing resistor group is output through a digital signal through the analog-to-digital conversion device, and a fault type is determined according to an output value of the digital signal.
The utility model provides a power chip trouble shows structure passes through input current detecting element detects whether take place the trouble that input current overflows is judged with the partial pressure comparison of resistance R11 to the both ends voltage difference of detecting resistance R9, when the overcurrent fault of generating current, field effect transistor Q1 switches on and inserts identifying resistance R20, changes the voltage between divider resistance R16 and the divider resistance group. The input voltage upper limit detection unit compares the voltage difference between the resistor R2 and the resistor R4 to judge whether the input voltage overvoltage fault occurs, when the input overvoltage fault occurs, the field effect transistor Q2 is conducted to connect the identification resistor R19, and the voltage between the voltage dividing resistor R16 and the voltage dividing resistor group is changed. The input voltage lower limit detection unit compares the voltage difference between the resistor R6 and the resistor R8 to judge whether the input voltage undervoltage fault occurs, when the input undervoltage fault occurs, the field effect transistor Q3 is conducted to connect the identification resistor R18, and the voltage between the voltage dividing resistor R16 and the voltage dividing resistor group is changed. Whether the output voltage overvoltage fault occurs or not is judged by comparing the voltage division difference between the resistor R13 and the resistor R15 through the output voltage detection unit, and when the output overvoltage fault occurs, the field effect transistor Q4 is conducted to connect the identification resistor R17, so that the voltage between the voltage division resistor R16 and the voltage division resistor group is changed. Since the identification resistor R17, the identification resistor R18, the identification resistor R19, and the identification resistor R20 are different in resistance value, the divided voltage change amount is different so that the cause of the occurrence of the fault can be determined according to the divided voltage change amount. The maintenance personnel can conveniently maintain the power supply chip according to the specific failure occurrence reason.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (7)
1. A power chip fault representation structure is applied to a power chip comprising a voltage conversion module, wherein a power input end and a power output end of the voltage conversion module are respectively connected with a working voltage DC, the working voltage DC is grounded through a divider resistor R16 and a divider resistor group, wherein the divider resistor group comprises a plurality of identification resistors which are controlled by field effect transistors and are connected in parallel and have different resistance values,
the field effect transistor is controlled to be conducted by the fault detection unit,
and detecting the voltage between the voltage dividing resistor R16 and the voltage dividing resistor group to acquire the fault type.
2. The power chip failure presentation structure of claim 1, wherein the failure detection unit comprises an input current detection unit, an input voltage upper limit detection unit, an input voltage lower limit detection unit, and an output voltage detection unit.
3. The power chip failure indication structure of claim 2, wherein the input current detection unit comprises a detection resistor R9, the detection resistor R9 is connected in series between the power input terminal and the voltage conversion module, and two ends of the detection resistor R9 are electrically connected to two input terminals of a differential amplifier a 1; the reference voltage is grounded through a resistor R10 and a resistor R11, two input ends of a differential amplifier A2 are respectively connected with the output of the differential amplifier A1 and between the resistor R10 and the resistor R11, and the output end of the differential amplifier A2 is electrically connected with the grid of a field effect transistor Q1.
4. The power chip failure indication structure of claim 2, wherein the input voltage upper limit detection unit comprises a differential amplifier A3, the power input terminal is grounded via a resistor R1 and a resistor R2, the reference voltage is grounded via a resistor R3 and a resistor R4, two input terminals of the differential amplifier A3 are respectively electrically connected between the resistor R1 and the resistor R2 and between the resistor R3 and the resistor R4, and an output terminal of the differential amplifier A3 is electrically connected to a gate of the fet Q2.
5. The power chip failure indication structure of claim 2, wherein the input voltage lower limit detection unit comprises a differential amplifier a4, the power input terminal is grounded via a resistor R5 and a resistor R6, the reference voltage is grounded via a resistor R7 and a resistor R8, two input terminals of the differential amplifier a4 are respectively electrically connected between the resistor R5 and the resistor R6 and between the resistor R7 and the resistor R8, and an output terminal of the differential amplifier a4 is electrically connected to a gate of the fet Q3.
6. The power chip failure indication structure of claim 2, wherein the output voltage detection unit comprises a differential amplifier a5, the power output terminal is grounded via a resistor R12 and a resistor R13, the reference voltage is grounded via a resistor R14 and a resistor R15, two input terminals of the differential amplifier a5 are electrically connected between the resistor R14 and the resistor R15 and between the resistor R12 and the resistor R13, respectively, and an output terminal of the differential amplifier a5 is electrically connected to a gate of the fet Q4.
7. The power chip failure indication structure of claim 1, wherein an analog-to-digital conversion device is electrically connected between the voltage dividing resistor R16 and the voltage dividing resistor set.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022438322.8U CN213903717U (en) | 2020-10-28 | 2020-10-28 | Power chip fault representation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022438322.8U CN213903717U (en) | 2020-10-28 | 2020-10-28 | Power chip fault representation structure |
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| Publication Number | Publication Date |
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| CN213903717U true CN213903717U (en) | 2021-08-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202022438322.8U Active CN213903717U (en) | 2020-10-28 | 2020-10-28 | Power chip fault representation structure |
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