CN213846626U - Wafer-level packaging structure of filter - Google Patents
Wafer-level packaging structure of filter Download PDFInfo
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- CN213846626U CN213846626U CN202023166844.3U CN202023166844U CN213846626U CN 213846626 U CN213846626 U CN 213846626U CN 202023166844 U CN202023166844 U CN 202023166844U CN 213846626 U CN213846626 U CN 213846626U
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Abstract
The utility model relates to a semiconductor package technical field discloses a wave filter wafer level packaging structure. The wafer-level packaging structure of the filter comprises a filter wafer, a cover wafer and a micro-convex welding spot, wherein the filter wafer comprises a substrate, a functional area and a plurality of welding pads are arranged on the upper surface of the substrate, the cover wafer is made of a silicon wafer and is adhered to the upper surface of the substrate through a glue layer, a groove is formed in one side, close to the substrate, of the cover wafer, the functional area is contained in the groove, the micro-convex welding spot is arranged on the cover wafer, and the micro-convex welding spot is electrically connected with the welding pads. The utility model discloses a wave filter wafer level packaging structure, packaging process is simple, the difficult contaminated function district of packaging process, and whole thickness structure is thinner.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially relates to a wave filter wafer level packaging structure.
Background
The filter is a frequency selection device, which can pass specific frequency components in the signal, and greatly attenuate other frequency components, so that the filter can be used for filtering interference noise. As shown in fig. 1, the wafer level 1 ' of the filter includes a substrate 11 ', a functional region 12 ' and a pad 13 ' are disposed on an upper surface of the substrate 11 ', and the functional region 12 ' is required to be located in a cavity when the wafer level 1 ' of the filter is packaged according to the performance and function requirements of the filter. As shown in fig. 1, in the prior art, the filter wafer level package structure includes a patterned support dam 2 ', the support dam 2 ' is disposed on a substrate 11 ', a protective layer 3 ' is disposed on the support dam 2 ', the substrate 11 ', the support dam 12 ' and the protective layer 3 ' together enclose a closed accommodating cavity 4 ', and a functional region 12 ' is located in the accommodating cavity 4 '. In the wafer-level packaging structure of the filter in the prior art, on one hand, the supporting cofferdam is usually formed on the substrate by adopting a dry film photoetching process, and the pollution of a functional area is easily caused in the processing process, so that the yield of the packaging structure is low; on the other hand, the supporting cofferdam and the protective layer are packaged together, the process is complex, the supporting cofferdam, the substrate and the protective layer are bonded by adhesives, and the finally obtained packaging structure is thick in whole thickness.
Therefore, a need exists for a wafer level package structure for a filter to solve the above problems.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a wave filter wafer level packaging structure, packaging process is simple, the difficult contaminated functional area of packaging process, and whole thickness structure is thinner.
To achieve the purpose, the utility model adopts the following technical proposal:
a filter wafer level package structure, comprising:
the filter wafer comprises a substrate, wherein a functional area and a plurality of welding pads are arranged on the upper surface of the substrate;
the cover wafer is made of a silicon wafer, the cover wafer is bonded on the upper surface of the substrate through a glue layer, a groove is formed in one side, close to the substrate, of the cover wafer, and the functional area is contained in the groove;
and the micro-bump welding points are arranged on the covering wafer and are electrically connected with the welding pads.
Optionally, a blind hole is formed in the filter wafer level package structure, the blind hole penetrates through the cover wafer, the glue layer and the pad in sequence from one side of the cover wafer, a Cu connector is arranged in the blind hole, and the Cu connector is electrically connected with the conductive layer of the pad and the micro-bump respectively.
Optionally, the blind hole is made by a laser drilling process.
Optionally, the Cu connector is formed in the blind hole by electroplating.
Optionally, an area on the upper side of the cover wafer, which is located within a preset size range of the blind hole, is a preset area, metal layers are arranged on the preset area and the inner surface of the blind hole, and the metal layers are electrically connected with the conductive layer of the bonding pad and the Cu connector respectively.
Optionally, the metal layer is sputtered to the surfaces of the blind via and the cover wafer by means of physical vapor deposition.
Optionally, a part of the metal layer corresponding to the preset region is a reserved region, an under-ball metal layer is arranged on the outer surface of the reserved region, and the under-ball metal layer is electrically connected with the reserved region and the micro-bump respectively.
Optionally, the under-ball metal layer includes a Ni plating layer and an Au plating layer, and the Ni plating layer is close to one side of the reserved area;
the thickness of the Ni-plated layer and the thickness of the Au-plated layer are both 2-4 mu m.
Optionally, the groove is formed through a photoetching process and a dry etching process in sequence; or the groove is formed by a laser ablation method.
Optionally, the substrate has a thickness of 20 μm to 300 μm; and/or the thickness of the cover wafer is 10-500 μm; and/or the thickness of the glue layer is 0.1-100 mu m.
The utility model discloses beneficial effect does:
in the packaging structure of the filter wafer of the embodiment, the cover wafer is formed by forming the groove on the silicon wafer, which is equivalent to integrally forming the support cofferdam and the protection layer, so that the whole structure is simple and the assembly is convenient; the connection of the cover wafer and the substrate only needs one glue layer, which is beneficial to reducing the thickness of the whole packaging structure, and the substrate and the cover wafer are both made of silicon materials and are firmly and stably connected after being bonded by the glue layer; in addition, the groove processing process does not cause pollution to the functional area on the wafer level. The utility model discloses a wave filter wafer level packaging structure, packaging process is simple, the difficult contaminated function district of packaging process, and whole thickness structure is thinner.
Drawings
FIG. 1 is a diagram of a prior art filter wafer level package structure;
fig. 2 is a schematic diagram of a wafer level package structure of a filter according to an embodiment of the present invention;
FIG. 3 is an enlarged view at B in FIG. 2;
fig. 4 is a schematic structural diagram of a cover wafer according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a mating body according to an embodiment of the present invention;
fig. 6 is a schematic structural view of a matching body after thinning a cover wafer according to an embodiment of the present invention;
fig. 7 is a schematic structural view of the matching body provided with the blind hole according to the embodiment of the present invention;
FIG. 8 is an enlarged view taken at A in FIG. 7;
fig. 9 is a schematic structural view of a matching body of the present invention after a metal layer is sputtered on a cover wafer;
fig. 10 is a schematic structural view of a Cu connector filled in a blind hole of a mating body according to an embodiment of the present invention;
FIG. 11 is a schematic structural view of a mating body with a portion of a metal layer removed according to an embodiment of the present invention;
fig. 12 is a schematic structural view of a metal layer under balls plated on a reserved area of a mating body according to an embodiment of the present invention;
fig. 13 is a schematic structural view of a micro-bump welded on an under-ball metal layer of a mating body according to an embodiment of the present invention;
FIG. 14 is a schematic view of a structure of a mating body according to an embodiment of the present invention with a grinding tape adhered to a cover wafer;
fig. 15 is a schematic structural view of a mating body according to an embodiment of the present invention after thinning a substrate.
In the figure:
1' -a filter wafer; 11' -a substrate; a 12' -functional region; 13' -pad; 2' -supporting the cofferdam; a 3' -protective layer; 4' -a containment chamber; 5' -micro bump;
1-a filter wafer; 11-a substrate; 12-a functional region; 13-a pad; 131-a passivation layer; 132-a conductive layer;
2-covering the wafer; 21-a groove;
3-glue layer;
4-a ligand; 41-blind hole;
5-micro bump welding;
6-grinding the adhesive tape;
7-a metal layer; 71-a reserved area;
an 8-Cu linker;
9-under-ball metal layer.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
In the description of the present invention, unless expressly stated or limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, detachably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description of the present embodiment, the terms "upper", "lower", "right", etc. are used in an orientation or positional relationship based on that shown in the drawings only for convenience of description and simplicity of operation, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used only for descriptive purposes and are not intended to have a special meaning.
The embodiment provides a wafer-level packaging structure of a filter, which is suitable for a wafer level of an FBAR (film bulk acoustic resonator) filter and a wafer level of a BAW (bulk acoustic wave) filter. As shown in fig. 2 and fig. 3, the filter wafer level package structure includes a filter wafer 1, a cover wafer 2 and micro-bump pads 5, wherein the filter wafer 1 includes a substrate 11, a functional region 12 and a plurality of solder pads 13 are disposed on an upper surface of the substrate 11, the cover wafer 2 is made of a silicon wafer, the cover wafer 2 is adhered to the upper surface of the substrate 11 through a glue layer 3, a groove 21 is formed on one side of the cover wafer 2 close to the substrate 11, the functional region 12 is accommodated in the groove 21, the micro-bump pads 5 are disposed on the cover wafer 2, and the micro-bump pads 5 are electrically connected to the solder pads 13.
In the wafer-level packaging structure of the filter of the embodiment, the cover wafer 2 is formed by forming the grooves 21 on the silicon wafer, which is equivalent to integrally forming the supporting cofferdam and the protective layer, and the whole structure is simple and convenient to assemble; the connection between the cover wafer 2 and the substrate 11 only needs one glue layer 3, which is beneficial to reducing the thickness of the whole packaging structure, and the substrate 11 and the cover wafer 2 are both made of silicon materials and are firmly and stably connected after being bonded by the glue layer 3; in addition, the groove 21 processing process does not cause contamination of the functional region 12 on the wafer level. The utility model discloses a wave filter wafer level packaging structure, packaging process is simple, packaging process is difficult for polluting functional area 12, and whole thickness structure is thinner.
Specifically, in this embodiment, when the cover wafer 2 and the substrate 11 are bonded, the glue is printed on the area of the cover wafer 2 not provided with the groove 21 to prevent the glue from contaminating the functional area 12 and the groove 21, and then the cover wafer 2 and the substrate 11 are aligned and bonded permanently. The cover wafer 2 and the bonding pad 13 are tightly bonded by the glue layer 3, and the functional region 12 is sealed between the groove 21 and the substrate 11. Optionally, in this embodiment, the thickness of the glue layer 3 is 0.1 μm to 100 μm, and a thinner thickness is ensured as much as possible on the premise of ensuring the adhesive strength.
Preferably, the substrate 11 has a thickness of 20 μm to 500 μm, and the cover wafer 2 has a thickness of 10 μm to 500 μm. In general, the thickness of the substrate 11 is determined according to the finished thickness of the filter wafer 1, in this embodiment, the cover wafer 2 and the substrate 11 are made of silicon materials and are supported by each other, so after the cover wafer 2 and the substrate 11 are bonded, both the cover wafer 2 and the substrate 11 are ground and thinned to a thinner thickness range, and the entire package structure can still have sufficient structural strength. In this embodiment, the silicon material is used as the cover wafer 2, so that the thickness of the package structure can be greatly reduced, and the overall thickness of the filter wafer level package structure is substantially the same as the wafer level initial thickness.
Preferably, the groove 21 is formed through a photolithography process and a dry etching process in this order. The forming is carried out by an etching process, the forming precision is high, and the surface quality of the groove 21 is good. In other embodiments, the groove 21 may also be formed by laser ablation, so that the groove 21 is directly formed on the cover wafer 2, which is more efficient and convenient to process. Specifically, a region to be grooved is etched on the lower surface of the silicon wafer by using a photolithography method, and then a groove 21 is etched in the region to be grooved by using a dry etching method. In this embodiment, the depth of the groove is 5 μm to 100 μm, the size of the cross section of the groove 21 is not smaller than the size of the functional region 12, and after the cover wafer 2 is bonded to the substrate 11, the center of the groove 21 coincides with the projection of the center of the functional region 12 on the substrate 11, so as to ensure that the functional region 12 is centrally disposed in the space formed by the groove 21 and does not contact with the bottom of the groove 21.
As shown in fig. 8, for some filter wafers 1, the bonding pad 13 includes a conductive layer 132, and passivation layers 131 are respectively disposed on the upper and lower sides of the conductive layer 132, and the passivation layers 131 cannot be electrically connected. In order to realize the electrical connection between the micro bump 5 and the pad 13, as shown in fig. 3, a blind via 41 is formed on the filter wafer level package structure, the blind via 41 sequentially penetrates the cover wafer 2, the glue layer 3 and the pad 13 from one side of the cover wafer 2, a Cu connector 8 is disposed in the blind via 41, and the Cu connector 8 is electrically connected to the conductive layer 132 of the pad 13 and the micro bump 5, respectively. The Cu connector 8 in the blind via 41 completely penetrates the pad 13, so that the conductive layer 132 in the middle layer is exposed, and the pad 13 is electrically connected to the micro bump 5 through the Cu connector 8 and the conductive layer 132. Specifically, in the present embodiment, the blind hole 41 is processed by laser drilling. Laser drilling is to utilize the laser beam irradiation of high density to be processed the material, makes the material heated to gasification temperature fast in order to form the cavity, consequently, laser drilling all can realize to different materials, and the laser beam can punch cover wafer 2, glue layer 3 and bonding pad 13 in proper order promptly, and the blind hole 41 that passes multilayer different materials is through laser drilling one shot forming, and processing is convenient, efficient.
Preferably, the Cu connector 8 is formed in the blind hole 41 by electroplating, and the Cu connector 8 is directly formed in the blind hole 41 without being assembled into the blind hole 41 after the Cu connector 8 is processed, thereby improving the packaging efficiency.
Due to the inconsistent materials of the passivation layer 131 and the Cu connector 8, if the Cu connector 8 is directly plated in the blind via 41, the Cu connector 8 cannot grow on the passivation layer 131, so the blind via 41 is difficult to fill, and finally the electrical connection between the Cu connector 8 and the conductive layer 132 is weak, resulting in poor reliability of the electrical connection between the micro bump 5 and the pad 13. Preferably, as shown in fig. 3, a region of the upper side of the cover wafer 2 within a predetermined size range of the blind via 41 is a predetermined region, the predetermined region and the inner surface of the blind via 41 are provided with a metal layer 7, and the metal layer 7 is electrically connected to the conductive layer 132 of the pad 13 and the Cu connector 8, respectively. By arranging the metal layer 7 in the blind hole 41, the consistency of the material of the inner surface of the blind hole 41 is ensured, and the metal layer is electrically connected with the conductive layer 132, so that when the Cu connector 8 is electroplated, the Cu connector 8 can completely fill the blind hole 41, the stability of the electrical connection between the Cu connector 8 and the conductive layer 132 is ensured, the metal layer 7 positioned in the preset area is convenient for increasing the connection area with the micro-bump welding point 5, and the stability of the connection between the micro-bump welding point 5 is ensured. Specifically, in the present embodiment, the metal layer 7 is sputtered to the blind via 41 and the surface of the cover wafer 2 by physical vapor deposition. The physical vapor deposition is a mode of bombarding the target material by high-energy particles under a vacuum condition, so that target material atoms escape and are finally deposited on the surface of a piece to be deposited, the mode can realize that the metal layer 7 covers the preset area and the inner surface of the blind hole 41 at one time, and can ensure that the thickness of the metal layer 7 is uniform. Specifically, the thickness of the metal layer 7 is 2 μm, and in other embodiments, the thickness of the metal layer 7 is set reasonably according to the bottom size of the blind hole 41 and other factors.
The micro bump 5 is usually made of tin material and is connected by a welding process, and the metal layer 7 and the Cu connector 8 are made of different materials from the micro bump 5, so that the direct welding difficulty is very high, preferably, as shown in fig. 3, a portion of the metal layer 7 corresponding to the predetermined area is a reserved area 71, an under-ball metal layer 9 is disposed on the outer surface of the reserved area 71, and the under-ball metal layer 9 is electrically connected with the reserved area 71 and the micro bump 5, respectively. By means of the metal layer 9 under the ball, on the basis of ensuring that the conductive layer 132 can be electrically connected with the micro-bump 5, the connection firmness of the micro-bump 5 and the reserved area 71 can also be realized.
Specifically, the ubm layer 9 includes two layers, which are a Ni plating layer and an Au plating layer in this order, and the Ni plating layer is close to the reserved area 71 side. Can guarantee through the mode of chemical plating that Ni-plated layer and Au-plated layer evenly distributed are on reservation district 71, and when welding little protruding solder joint 5, Ni-plated layer and Au-plated layer can carry out diffusion infiltration to little protruding solder joint 5 and reservation district 71 respectively under welding temperature, finally guarantee little protruding solder joint 5's firm in connection. In the embodiment, the thickness of the Ni-plated layer and the Au-plated layer is 2-4 μm, and the cost is controlled as much as possible on the basis of ensuring the connection firmness.
Alternatively, the micro-bump 5 may be formed by directly using a finished solder ball, or by printing a solder paste on the reserved area 71 and then forming the micro-bump 5 from the solder paste by a high-temperature reflow method. The specific process of making the ball by printing solder paste is prior art and will not be described herein.
In general, before the filter wafer 1 is packaged, the substrate 11 is an integral large board, a specific number of pads 13 are correspondingly arranged in each functional region 12, the functional region 12 and the plurality of pads 13 form a unit, a plurality of the units are distributed on the substrate 11 in a matrix manner, and after the packaging is finished, the units are cut to obtain an independent filter wafer level packaging structure. Before dicing, a dicing film (not shown) is preferably attached to the substrate 11, and dicing is performed according to dicing streets on the dicing film.
In summary, the packaging process of the filter wafer level package structure of the present embodiment includes:
as shown in fig. 4, a groove 21 is opened on one side of the silicon wafer by an etching process to form a cover wafer 2;
as shown in fig. 5, the side of the cover wafer 2 provided with the groove 21 is bonded to the upper side of the substrate 11 through the glue layer 3 to form the matching body 4, and the functional region 12 is accommodated in the space enclosed by the substrate 11 and the groove 21;
as shown in fig. 6, the cover wafer 2 is ground to be thinner to 10 μm to 500 μm;
as shown in fig. 7 and 8, a blind via 41 is opened from the side of the cover wafer 2 to the mating body 4 by a laser drilling process to expose the conductive layer 132 of the pad 13;
as shown in fig. 9, sputtering the metal layer 7 on the mating body 4 by physical vapor deposition, wherein the metal layer 7 covers the surface of the cover wafer 2 away from the substrate 11 and the inner surface of the blind via 41;
as shown in fig. 10, the blind via 41 sputtered with the metal layer 7 is filled with the Cu connection body 8 by an electroplating process;
as shown in fig. 11, the metal layer 7 is removed from the portion of the cover wafer 2 except the predetermined region, and only the reserved region 71 is reserved;
as shown in fig. 12, an under-ball metal layer 9 is plated on the reserved area 71 by chemical plating;
as shown in fig. 13, the micro bump 5 is soldered on the ubm layer 9;
as shown in fig. 14, a polishing tape 6 is adhered to the cover wafer 2, and the micro bump 5 is covered by the polishing tape 6;
as shown in fig. 15, the substrate 11 is polished to be thinner than 20 μm to 300 μm, the polishing tape 6 is torn off, a dicing film is attached to the substrate 11, and dicing is performed according to dicing streets on the dicing film, so as to obtain an independent filter wafer level package structure.
Obviously, the above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and for those skilled in the art, there are variations on the specific embodiments and the application scope according to the idea of the present invention, and the content of the description should not be construed as a limitation to the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. A wafer level package structure of a filter, comprising:
the filter wafer (1) comprises a substrate (11), wherein a functional area (12) and a plurality of welding pads (13) are arranged on the upper surface of the substrate (11);
the cover wafer (2) is made of a silicon wafer, the cover wafer (2) is bonded to the upper surface of the substrate (11) through a glue layer (3), a groove (21) is formed in one side, close to the substrate (11), of the cover wafer (2), and the functional area (12) is contained in the groove (21);
the micro-bump (5) is arranged on the cover wafer (2), and the micro-bump (5) is electrically connected with the welding pad (13).
2. The structure of claim 1, wherein the structure has a blind via (41), the blind via (41) penetrates the cover wafer (2), the glue layer (3) and the pad (13) in sequence from one side of the cover wafer (2), and a Cu connector (8) is disposed in the blind via (41), and the Cu connector (8) is electrically connected to the conductive layer (132) of the pad (13) and the micro bump (5), respectively.
3. The filter wafer level package structure of claim 2, wherein the blind holes (41) are made by a laser drilling process.
4. The filter wafer level package structure of claim 2, wherein the Cu connectors (8) are formed in the blind holes (41) by electroplating.
5. The wafer-level package structure of claim 2, wherein an area of the upper side of the cover wafer (2) within a predetermined size range of the blind via (41) is a predetermined area, the predetermined area and an inner surface of the blind via (41) are provided with a metal layer (7), and the metal layer (7) is electrically connected to the conductive layer (132) of the pad (13) and the Cu connector (8), respectively.
6. The filter wafer level package structure of claim 5, wherein the metal layer (7) is sputtered to the blind via (41) and the surface of the cover wafer (2) by physical vapor deposition.
7. The wafer-level package structure of claim 5, wherein a portion of the metal layer (7) corresponding to the predetermined area is a reserved area (71), an under-ball metal layer (9) is disposed on an outer surface of the reserved area (71), and the under-ball metal layer (9) is electrically connected to the reserved area (71) and the micro bump (5), respectively.
8. The filter wafer level package structure of claim 7, wherein the under ball metal layer (9) comprises a Ni-plated layer and an Au-plated layer, the Ni-plated layer being adjacent to the side of the reserved area (71);
the thickness of the Ni-plated layer and the thickness of the Au-plated layer are both 2-4 mu m.
9. The filter wafer level package structure according to any one of claims 1 to 8, wherein the recess (21) is formed by a photolithography process and a dry etching process in sequence; or the groove (21) is formed by a laser ablation method.
10. The filter wafer level package structure according to any of claims 1 to 8, wherein the thickness of the substrate (11) is 20 μm to 300 μm; and/or the thickness of the cover wafer (2) is 10-50 μm; and/or the thickness of the glue layer (3) is 0.1-100 mu m.
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| CN202023166844.3U CN213846626U (en) | 2020-12-24 | 2020-12-24 | Wafer-level packaging structure of filter |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113572445A (en) * | 2021-09-23 | 2021-10-29 | 深圳新声半导体有限公司 | Filter chip packaging structure and method for packaging filter chip |
| US11677381B2 (en) | 2021-10-19 | 2023-06-13 | Shenzhen Newsonic Technologies Co., Ltd. | Film bulk acoustic resonator structure and fabricating method |
-
2020
- 2020-12-24 CN CN202023166844.3U patent/CN213846626U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113572445A (en) * | 2021-09-23 | 2021-10-29 | 深圳新声半导体有限公司 | Filter chip packaging structure and method for packaging filter chip |
| US11677381B2 (en) | 2021-10-19 | 2023-06-13 | Shenzhen Newsonic Technologies Co., Ltd. | Film bulk acoustic resonator structure and fabricating method |
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