CN213817829U

CN213817829U - Ethernet port flow speed limiting system based on FPGA

Info

Publication number: CN213817829U
Application number: CN202022325010.6U
Authority: CN
Inventors: 鞠小育; 陈守卫; 胡川
Original assignee: Shenzhen Wintop Optical Technology Co ltd
Current assignee: Shenzhen Wintop Optical Technology Co ltd
Priority date: 2020-10-19
Filing date: 2020-10-19
Publication date: 2021-07-27
Anticipated expiration: 2030-10-19

Abstract

The utility model provides an ethernet port flow speed-limiting system based on FPGA, including CPU unit, first PHY unit, FPGA unit, second PHY unit and network interface, network interface with second PHY unit input/output both way junction, second PHY unit with FPGA unit input/output both way junction, the FPGA unit with first PHY unit input/output both way junction, first PHY unit with the SGMII interface input/output both way junction of CPU unit, the output of CPU unit pass through the IIC bus with FPGA unit connection. The utility model has the advantages that: the flow limitation of the Ethernet port can be realized, and the requirements of an intelligent substation can be met.

Description

Ethernet port flow speed limiting system based on FPGA

Technical Field

The utility model relates to an ethernet port flow speed-limiting system especially relates to an ethernet port flow speed-limiting system based on FPGA.

Background

The existing Ethernet switching chip does not support the port speed limiting function and is difficult to meet the requirements of a controllable substation switch.

Disclosure of Invention

In order to solve the problems in the prior art, the utility model provides an ethernet port flow speed-limiting system based on FPGA.

The utility model provides an ethernet port flow speed-limiting system based on FPGA, including CPU unit, first PHY unit, FPGA unit, second PHY unit and network interface, network interface with second PHY unit input/output both way junction, second PHY unit with FPGA unit input/output both way junction, the FPGA unit with first PHY unit input/output both way junction, first PHY unit with the SGMII interface input/output both way junction of CPU unit, the output of CPU unit pass through the IIC bus with FPGA unit connection.

As a further improvement of the present invention, the CPU unit has at least two SGMII interfaces.

As a further improvement of the present invention, the first PHY unit and the second PHY unit each have an RGMII interface, a 100base-TX interface and a 100base-FX interface.

As a further improvement of the present invention, the second PHY unit is connected to an SFP interface.

As a further improvement of the present invention, the network interface is an RJ45 interface.

As a further improvement of the utility model, the FPGA unit includes counter, time-recorder and controller, the output of CPU unit pass through the IIC bus with the input of controller is connected, the output of controller with the input of counter is connected, second PHY unit respectively with the input of counter, time-recorder is connected, the output of time-recorder with the input of counter is connected, the output of counter with first PHY unit is connected.

The utility model has the advantages that: by the scheme, the flow limitation of the Ethernet port can be realized, and the requirements of an intelligent substation can be met.

Drawings

Fig. 1 is the utility model discloses a schematic diagram of ethernet port flow speed-limiting system based on FPGA.

Fig. 2 is an RGMII timing diagram of the ethernet port flow rate limiting system based on FPGA of the present invention.

Fig. 3 is a schematic diagram of an FPGA unit of the ethernet port flow speed limiting system based on the FPGA.

Detailed Description

The present invention will be further described with reference to the following description and embodiments.

As shown in fig. 1 to fig. 3, an ethernet port flow rate limiting system based on an FPGA includes a CPU (central processing unit) unit 101, a first PHY (port physical layer) unit 102, an FPGA (field programmable gate array) unit 103, a second PHY unit 104, and a network interface 105, where the network interface 105 is bidirectionally connected to input and output of the second PHY unit 104, the second PHY unit 104 is bidirectionally connected to input and output of the FPGA unit 103, the FPGA unit 103 is bidirectionally connected to input and output of the first PHY unit 102, the first PHY unit 102 is bidirectionally connected to input and output of an SGMII interface of the CPU unit 101, and an output end of the CPU unit 101 is connected to the FPGA unit 103 through an IIC bus.

The CPU unit 101 has at least two SGMII interfaces, preferably two SGMII interfaces, which are respectively connected to the two first PHY units 102.

The first PHY unit 102 and the second PHY unit 104 each have an RGMII interface, a 100base-TX interface, and a 100base-FX interface.

The second PHY unit 104 is connected to an SFP (optical module) interface 106.

The network interface 105 is an RJ45 interface.

The FPGA unit 103 includes a counter 1, a timer 2, and a controller 3, an output end of the CPU unit 101 is connected to an input end of the controller 3 through an IIC bus, an output end of the controller 3 is connected to an input end of the counter 1, the second PHY unit 104 is connected to input ends of the counter 1 and the timer 2, an output end of the timer 2 is connected to an input end of the counter 1, and an output end of the counter 1 is connected to the first PHY unit 102.

An Ethernet port flow rate limiting system based on FPGA comprises the following working processes:

1. 100M data enters the second PHY unit 104 from the RJ45 interface, and the second PHY unit 104 converts the data into RGMII interface data to the FPGA unit 103;

2. FPGA unit 103 parses RGMII data: the rising edge of RGMII sends the lower four bits of a byte of data and the falling edge sends the remaining upper four bits of data. The receiving end clock samples the double edges, and the RGMII time sequence is shown in figure 2;

3. the CPU unit 101 gives the FPGA unit 103 a percentage value of the flow limit through the IIC bus. The FPGA unit 103 converts the value into a counting threshold, and when a data packet enters the FPGA unit 103, counting and timing are started at the same time, and when the data packet in unit time exceeds the threshold, redundant data packets are discarded, so that flow limitation is realized;

4. the FPGA unit 103 sends the data packet after the flow limitation to the first PHY unit 102, and the first PHY unit 102 converts the RGMII data into SGMII data and sends the SGMII data to the CPU.

The utility model provides a pair of ethernet port flow speed limit system based on FPGA can realize ethernet port flow restriction, can satisfy intelligent substation's requirement.

The utility model provides a pair of ethernet port flow speed-limiting system based on FPGA is applicable to intelligent substation, electric power industry.

The foregoing is a more detailed description of the present invention, taken in conjunction with the specific preferred embodiments thereof, and it is not intended that the invention be limited to the specific embodiments shown and described. To the utility model belongs to the technical field of ordinary technical personnel, do not deviate from the utility model discloses under the prerequisite of design, can also make a plurality of simple deductions or replacement, all should regard as belonging to the utility model discloses a protection scope.

Claims

1. The utility model provides an ethernet port flow speed limit system based on FPGA which characterized in that: the device comprises a CPU unit, a first PHY unit, an FPGA unit, a second PHY unit and a network interface, wherein the network interface is bidirectionally connected with the input and the output of the second PHY unit, the second PHY unit is bidirectionally connected with the input and the output of the FPGA unit, the FPGA unit is bidirectionally connected with the input and the output of the first PHY unit, the first PHY unit is bidirectionally connected with the input and the output of the SGMII interface of the CPU unit, the output end of the CPU unit is connected with the FPGA unit through an IIC bus, the CPU unit is provided with at least two SGMII interfaces, the FPGA unit comprises a counter, a timer and a controller, the output end of the CPU unit is connected with the input end of the controller through the IIC bus, the output end of the controller is connected with the input end of the counter, the second PHY unit is respectively connected with the input ends of the counter and the timer, and the output end of the timer is connected with the input end of the counter, the output end of the counter is connected with the first PHY unit, the first PHY unit and the second PHY unit are respectively provided with an RGMII interface, a 100base-TX interface and a 100base-FX interface, and the network interface is an RJ45 interface.