CN213782014U - Three-dimensional interconnected system-in-package - Google Patents
Three-dimensional interconnected system-in-package Download PDFInfo
- Publication number
- CN213782014U CN213782014U CN202022922934.4U CN202022922934U CN213782014U CN 213782014 U CN213782014 U CN 213782014U CN 202022922934 U CN202022922934 U CN 202022922934U CN 213782014 U CN213782014 U CN 213782014U
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- China
- Prior art keywords
- frame plate
- package
- wiring substrate
- heat dissipation
- heat
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a system in package of three-dimensional interconnection in system packaging field, including the heat dissipation frame plate and respectively encapsulate the wiring substrate who fixes both sides about the heat dissipation frame plate, the fixed surface of the relative heat dissipation frame plate of wiring substrate has chip and electron device, be equipped with the fretwork region on the bottom plate of heat dissipation frame plate, two upper and lower wiring substrates are through the electrically conductive connector electricity conduction interconnection of fretwork region department fixed. The utility model discloses a signal transmission between two upper and lower wiring substrate is realized to electrically conductive connector, more changes the single equipment plane of conventional base plate surface mounting components and parts into vertical direction's three-dimensional packaging structure to adopt the heat dissipation that the system was realized to the frame plate that dispels the heat, make the system encapsulation integrated level high, the radiating effect is good.
Description
Technical Field
The utility model relates to a system in package field specifically is a system in package of three-dimensional interconnection.
Background
In a system-in-package design, more components are placed by the need to be in a smaller volume of space. SiP faces problems of high packing density and difficult heat dissipation.
Generally, a system-in-package (soc) needs to reasonably distribute a signal processing chip, a memory chip, a clock chip, a transceiver chip, and other passive components in the same package, and a typical structure is shown in fig. 1. The carrier board in the package body plays a role of physical support, electrical interconnection and heat dissipation channel, and usually, in order to increase the number of components placed on the assembly plane, the upper and lower surfaces of the carrier board are utilized, or a plurality of carrier boards are packaged and interconnected among the boards are realized. However, the increase of the number of the carrier plates also means the lengthening of the heat dissipation path, which is not beneficial to the heat dissipation of the system.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a system in package of three-dimensional interconnect to solve the problem that proposes among the above-mentioned background art.
In order to achieve the above object, the utility model provides a following technical scheme:
a three-dimensional interconnected system-in-package comprises a heat dissipation frame plate and wiring substrates which are respectively packaged and fixed on the upper side and the lower side of the heat dissipation frame plate, wherein a chip and an electronic device are fixed on the surface of the wiring substrate, which is opposite to the heat dissipation frame plate, a hollow area is arranged on a bottom plate of the heat dissipation frame plate, and the upper wiring substrate and the lower wiring substrate are electrically interconnected through a conductive connector fixed at the hollow area.
As the improvement scheme of the utility model, in order to make the heat dissipation frame plate conduct heat more efficiently, the heat dissipation frame plate (3) is made of metal material with the heat conductivity of more than 150W/m.K.
As the utility model discloses a modified scheme, in order to facilitate the heat dissipation of chip, the surface of the relative heat dissipation frame plate of wiring substrate and the back and the heat dissipation frame plate laminating of chip of part chip flip-chip bonding.
As the improved scheme of the utility model, for the ease of improving the radiating efficiency of chip, contact through heat conduction silicone grease or heat conduction gasket between the back of chip and the heat dissipation frame plate.
As the improved scheme of the utility model, in order to improve the efficiency of heat conduction, be equipped with the miniflow channel intermediate layer in the bottom plate of heat dissipation framed panel, it has the heat dissipation liquid to circulate in the miniflow channel intermediate layer.
As the improved scheme of the utility model, electrically conductive connector includes insulating support frame and runs through and fix a plurality of electrically conductive pins in insulating support frame, the both ends and the rigid connection of wiring substrate or the elastic connection of electrically conductive pin.
As the improved scheme of the utility model, the conductive connector includes the insulation support frame and fixes the multilayer soft winding displacement that adopts the flexbleboard to make in the insulation support frame.
As a development of the present invention, in order to reduce crosstalk of the signal line, the insulating support frame is made of an organic material having a dielectric constant of 4 or more.
As the utility model discloses an improvement scheme, in order to improve the precision that electrically conductive connector and wiring substrate are connected, be equipped with the counterpoint weld column on the insulation support frame, the last pad of counterpointing that is equipped with of wiring substrate, the counterpoint weld column is fixed through counterpoint pad and wiring substrate.
As the improved scheme of the utility model, the bottom surface of the wiring substrate of below still is equipped with draws forth the end array.
Has the advantages that: the utility model discloses a signal transmission between two upper and lower wiring substrate is realized to electrically conductive connector, more changes the single equipment plane of conventional base plate surface mounting components and parts into vertical direction's three-dimensional packaging structure to adopt the heat dissipation that the system was realized to the frame plate that dispels the heat, make the system encapsulation integrated level high, the radiating effect is good.
Drawings
FIG. 1 is a block diagram of a typical system-in-package in the prior art;
FIG. 2 is a schematic view of the structure of the present invention;
FIG. 3 is a schematic view of the system of the present invention from a certain top view angle after packaging;
fig. 4 is a schematic view of the system at a certain elevation angle after packaging;
FIG. 5 is a diagram of one embodiment of the conductive connector of the present invention;
fig. 6 is a schematic structural view of the heat dissipation frame plate of the present invention.
In the figure: 1-an electronic device; 2-a wiring substrate; 3-heat dissipation frame plate; 4-a conductive connector; 5-leading-out terminal array; 6-a hollowed-out area; 7-an insulating support frame; 8-conductive pins; 9-para-position welding columns; 10-alignment pads.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Embodiment 1, referring to fig. 2 to 4, a three-dimensional interconnected system-in-package includes a heat-dissipating frame plate 3 and wiring substrates 2 respectively fixed on upper and lower sides of the heat-dissipating frame plate 3, wherein the wiring substrates 2 and the heat-dissipating frame plate 3 preferably form a sealing structure by bonding or welding. The surface of the wiring substrate 2 opposite to the heat dissipation frame plate 3 is fixed with chips and electronic devices 1, and the number of the chips and the electronic devices is determined by specific circuit functions. As shown in fig. 6, the heat dissipation frame plate 3 is a special-shaped structure, a hollow area 6 is provided on a bottom plate thereof, and the upper and lower wiring substrates 2 are electrically connected to each other through a conductive connector 4 fixed at the hollow area 6.
In the present embodiment, the wiring substrate 2 is an aluminum oxide or aluminum nitride multilayer co-fired ceramic, or a PCB multilayer wiring board, and depending on the specific requirements, when the aluminum oxide or aluminum nitride multilayer co-fired ceramic is selected, the conductor material of the circuit is gold or tungsten, etc., and when the PCB multilayer wiring board is used, the conductor material is copper. The wiring substrate 2 is generally provided with wiring layers such as a signal layer, a power supply layer, and a ground layer, and the wiring layers are interconnected by metal vias. The surface of the wiring substrate 2 is metal-coated with gold to form a pad or a bonding point for fixing with a chip or an electronic device. According to the requirement, the bottom of the lower wiring substrate 2 can be provided with a bonding pad with gold-coated surface, and a ball grid array or a column grid array is welded through the bonding pad to form a leading-out terminal array 5 which is used as an output port of the system-in-package.
Within a limited size range, such as the planar size requirement of a package size of 37.5mm × 37.5mm, 4 chips of 19mm × 8mm and 16 chips of 6.5mm × 5.6mm, as well as other electronic devices, need to be arranged. In this embodiment, 2 chips a and 8 chips B are respectively assembled on a single wiring substrate 2, and signal conduction is realized between the wiring substrates 2 through the conductive connector 4. The conductive connector 4 realizes signal conduction of the upper wiring substrate and the lower wiring substrate by adopting a vertical electric connection mode, is beneficial to improving the integration level of a system, can also carry out heat dissipation of the system by adopting the middle heat dissipation frame plate 3, and avoids overlong heat dissipation paths.
In the present embodiment, the heat dissipating frame plate 3 is made of a metal material having a thermal conductivity of 150W/m · K or more, preferably a metal material such as aluminum or kovar, and has excellent mechanical strength and heat dissipating performance, and serves as a physical support for the entire package system.
In a preferred embodiment, a chip with a portion of higher thermal power is flip-chip bonded to the surface of the wiring substrate 2 opposite to the heat dissipation frame plate 3 by using micro-bump or gold wire bonding, the back surface of the chip is attached to the heat dissipation frame plate 3, and other electronic devices such as resistance-capacitance elements are soldered to the surfaces of the two wiring substrates 3 opposite to each other. When the chip works, the heat diffusion can be rapidly realized through the heat dissipation frame plate 3, and the heat generated by the chip is conducted on the heat dissipation frame plate 3.
As a preferred embodiment, the back surface of the chip is in contact with the heat dissipation frame plate 3 through a heat conductive silicone grease or a heat conductive gasket, so that the thermal resistance can be reduced, the heat dissipation performance can be improved, and the heat conduction speed of the chip can be increased.
In a preferred embodiment, a micro channel interlayer is disposed in the bottom plate of the heat dissipation frame plate 3, and a heat dissipation liquid is circulated in the micro channel interlayer for accelerating heat dissipation in the heat dissipation frame plate 3.
As a preferred embodiment, as shown in fig. 5, the conductive connector 4 includes an insulating support 7 and a plurality of conductive pins 8 penetrating and fixed in the insulating support 7, specifically, the conductive connector 4 may be made by a method of forming an array of single-pin conductive pins 8 and then performing plastic molding to form the insulating support 7, and the conductive pins 8 may be of an elastic structure and elastically connected to the wiring substrate 2, or may be of a rigid structure and rigidly connected to the wiring substrate 2 by welding, bonding, or the like.
The diameter of the conductive pins 8 can be made to be 0.2mm, and the conductive pins are arranged in an array with the interval of 0.5mm and used as electric signal channels, and the number of the channels can reach 320.
As a preferred embodiment, the conductive connector 4 includes an insulating support 7 and a multi-layered flexible flat cable made of flexible sheets fixed in the insulating support 7.
In a preferred embodiment, the insulating support 7 is made of a material with excellent insulating properties such as organic plastic, and preferably an organic material with dielectric properties of 4 or more such as epoxy resin and phenolic resin, so as to reduce signal crosstalk between the conductive pins 8.
In a preferred embodiment, the insulating support frame 7 is provided with alignment posts 9, the wiring substrate 2 is provided with alignment pads 10, and the alignment posts 9 are fixed to the wiring substrate 2 by soldering via the alignment pads 10.
When the assembly is carried out, firstly, a wiring substrate 2 is prepared, and a special-shaped heat dissipation frame plate 3 and a conductive connector are manufactured according to the drawing; then, the chip and the electronic device are soldered or bonded to the surface of the wiring substrate 2, and the wiring substrate 2, the conductive connector 4 and the heat dissipation frame plate 3 are aligned and assembled by using a suitable jig, and are soldered and aligned with the alignment solder post 9 on the conductive connector 4 by designing an alignment pad 10 on the wiring substrate 2. The radiating frame plate 3 is bonded or welded with the two wiring substrates 2 to form a closed structure; finally, as necessary, a lead terminal, which is a solder ball or a solder column, is soldered to the bottom of the lower wiring substrate 2.
Although the present description is described in terms of embodiments, not every embodiment includes only a single embodiment, and such description is for clarity only, and those skilled in the art should be able to integrate the description as a whole, and the embodiments can be appropriately combined to form other embodiments as will be understood by those skilled in the art.
Therefore, the above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application; all changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Claims (10)
1. The three-dimensional interconnected system-in-package is characterized by comprising a heat dissipation frame plate (3) and wiring substrates (2) which are respectively packaged and fixed on the upper side and the lower side of the heat dissipation frame plate (3), wherein a chip and an electronic device (1) are fixed on the surface of the wiring substrate (2) opposite to the heat dissipation frame plate (3), a hollow area (6) is arranged on a bottom plate of the heat dissipation frame plate (3), and the upper wiring substrate and the lower wiring substrate (2) are electrically interconnected through a conductive connector (4) fixed at the hollow area (6).
2. The system-in-package of a three-dimensional interconnect according to claim 1, wherein the heat-dissipating frame plate (3) is made of a metal material having a thermal conductivity of 150W/m-K or more.
3. The system-in-package of claim 2, wherein a portion of the chip is flip-chip bonded or gold wire bonded to the surface of the wiring substrate (2) opposite to the heat-dissipating frame plate (3) and the back surface of the chip is attached to the heat-dissipating frame plate (3).
4. System in package with three dimensional interconnects according to claim 3, characterized in that the back side of the chip is in contact with the heat sink frame plate (3) through a thermally conductive silicone grease or a thermally conductive pad.
5. The system-in-package of claim 1 or 2, wherein the bottom plate of the heat-dissipating frame plate (3) is provided with a micro-channel interlayer, and a heat-dissipating liquid is circulated in the micro-channel interlayer.
6. The system-in-package of claim 1, wherein the conductive connector (4) comprises an insulating support frame (7) and a plurality of conductive pins (8) penetrating and fixed in the insulating support frame (7), and both ends of the conductive pins (8) are rigidly or elastically connected to the wiring substrate (2).
7. The system-in-package of claim 1, characterized in that the conductive connector (4) comprises an insulating support frame (7) and a plurality of flexible flat cables made of flexible plates fixed in the insulating support frame (7).
8. System-in-package according to claim 6 or 7, characterised in that said insulating support (7) is made of an organic material with a dielectric constant above 4.
9. The system-in-package of claim 8, characterized in that the insulating support frame (7) is provided with alignment bonding posts (9), the wiring substrate (2) is provided with alignment bonding pads (10), and the alignment bonding posts (9) are fixed to the wiring substrate (2) through the alignment bonding pads (10).
10. The system-in-package of a three-dimensional interconnect according to claim 1, characterized in that the bottom surface of the underlying wiring substrate (2) is further provided with an array of terminals (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022922934.4U CN213782014U (en) | 2020-12-07 | 2020-12-07 | Three-dimensional interconnected system-in-package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022922934.4U CN213782014U (en) | 2020-12-07 | 2020-12-07 | Three-dimensional interconnected system-in-package |
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| Publication Number | Publication Date |
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| CN213782014U true CN213782014U (en) | 2021-07-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202022922934.4U Active CN213782014U (en) | 2020-12-07 | 2020-12-07 | Three-dimensional interconnected system-in-package |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114630491A (en) * | 2022-03-22 | 2022-06-14 | 广东松普微波技术有限公司 | Radio frequency 3D micro-packaging integrated structure, radio frequency packaging device and method thereof |
-
2020
- 2020-12-07 CN CN202022922934.4U patent/CN213782014U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114630491A (en) * | 2022-03-22 | 2022-06-14 | 广东松普微波技术有限公司 | Radio frequency 3D micro-packaging integrated structure, radio frequency packaging device and method thereof |
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