CN213752539U - Drive circuit of holding relay - Google Patents
Drive circuit of holding relay Download PDFInfo
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- CN213752539U CN213752539U CN202022758391.7U CN202022758391U CN213752539U CN 213752539 U CN213752539 U CN 213752539U CN 202022758391 U CN202022758391 U CN 202022758391U CN 213752539 U CN213752539 U CN 213752539U
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Abstract
The utility model relates to a drive circuit of hold relay, include: the circuit comprises a first triode, a second triode, a first resistor, a second resistor, a third resistor, a capacitor and a first diode; one end of the first resistor is connected with the control pin, and the other end of the first resistor is respectively connected with the base of the first triode and one end of the second resistor; the second resistor is set as a pull-up resistor of the first triode, and the other end of the second resistor is connected with a direct-current power supply; the second triode is connected with one end of the first triode and one end of the third resistor respectively; a series circuit composed of a holding relay and a capacitor is arranged between the collector and the emitter of the second triode; the anode of the first diode is connected with the series circuit; the cathode of the first diode and the other end of the third resistor are both grounded. The utility model has the characteristics of control pin is few, the low power dissipation, with low costs, and can realize the power down protection, make relay link more intelligent and safety.
Description
Technical Field
The utility model relates to a relay technical field, especially a drive circuit who keeps relay.
Background
A hold relay is an electronic control device that turns on or off an output circuit to be controlled when an input amount reaches a prescribed value. Many conventional hold-up relays use the H-bridge drive circuit shown in fig. 1. The holding relay shown in fig. 1 can keep the magnetic field injected by the previous driving pulse in the electromagnetic coil unchanged, i.e. the driving current is not required to be added during normal operation, and only the reverse pulse with a certain time length is added when the contact state is required to be changed. However, the circuit shown in fig. 1 has the disadvantages of many components and many control pins. A conventional hold relay also has a circuit that uses a chip shown in fig. 2 to realize driving. The chip driving can reduce the number of components, but has the defects of more pins and small chip driving voltage range.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a main aim at provides a drive circuit who keeps relay, has that the control pin is few, the low power dissipation, characteristics with low costs, and can realize the power down protection, makes relay connection end intelligent and safety more.
The utility model adopts the following technical scheme:
a drive circuit for a retention relay, comprising: the circuit comprises a first triode, a second triode, a first resistor, a second resistor, a third resistor, a capacitor and a first diode; one end of the first resistor is connected with the control pin, and the other end of the first resistor is respectively connected with the base electrode of the first triode and one end of the second resistor; the second resistor is set as a pull-up resistor of the first triode, and the other end of the second resistor is connected with a direct-current power supply; the second triode is connected with one end of the first triode and one end of the third resistor respectively; a series circuit formed by the holding relay and the capacitor is arranged between the collector and the emitter of the second triode; the anode of the first diode is connected with the series circuit; and the cathode of the first diode and the other end of the third resistor are both grounded.
Preferably, the drive circuit of the hold relay further includes: the third triode, the fourth resistor and the fifth resistor; one end of the first resistor is connected with the control pin through the third triode and the fourth resistor; the fifth resistor is set as a pull-down resistor of the third triode.
Preferably, the drive circuit of the hold relay further includes: a second diode; the anode of the second diode is connected with the first triode; and the cathode of the second triode is connected with the second triode.
Preferably, the first triode is an NPN triode or a PNP triode.
Preferably, the second triode is an NPN triode; the collector of the second triode is connected with the first triode; the emitter of the second triode is connected with the anode of the first diode; and the base electrode of the second triode is grounded.
Preferably, the second triode is a PNP triode; the emitting electrode of the second triode is connected with the first triode; and the collector and the base of the second triode are both connected with the anode of the first diode.
Preferably, the third triode is an NPN triode or a PNP triode.
Preferably, one end of the capacitor is connected to the first triode, and the other end of the capacitor is connected to one end of the hold relay; the other end of the hold relay is connected to the anode of the first diode.
Preferably, one end of the hold relay is connected to the first triode, and the other end of the hold relay is connected to one end of the capacitor; the other end of the capacitor is connected with the anode of the first diode.
Preferably, the control pin is connected with the MCU.
Compared with the prior art, the beneficial effects of the utility model are as follows:
(1) the driving circuit of the utility model can drive the hold relay through two or three triodes, a capacitor, a diode and a plurality of resistors, and can control the two-way work of the hold relay through using a control pin, thereby saving the pin resource and having the advantages of low cost and low power consumption;
(2) the drive circuit of the utility model can set the control pin to be a fixed level (high level or low level) after the MCU is powered down by setting the pull-up resistor connected with the first triode or the pull-down resistor connected with the third triode, namely, the relay can be automatically restored to the state before the MCU is powered down, so that the relay connection end is more intelligent and safe;
(3) the driving circuit of the utility model ensures the conduction of each triode by arranging the first diode;
(4) the utility model discloses a drive circuit through setting up the second diode, can prevent the electric current backward flow.
The above description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention can be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following description lists the embodiments of the present invention.
The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments thereof, taken in conjunction with the accompanying drawings.
Drawings
FIG. 1 is a prior art H-bridge driver circuit;
FIG. 2 is a prior art driving circuit using a chip;
fig. 3 is a circuit diagram of a first embodiment of the present invention;
fig. 4 is a first circuit diagram of a second embodiment of the present invention;
fig. 5 is a second circuit diagram of a second embodiment of the present invention;
fig. 6 is a first circuit diagram of a third embodiment of the present invention;
fig. 7 is a circuit diagram ii of a third embodiment of the present invention.
Detailed Description
In order to make the technical solution and advantages of the present invention more clearly understood, the following description is given with reference to the accompanying drawings and embodiments,
the present invention will be described in further detail. It should be understood that the embodiments described herein are merely illustrative of the present invention and are not intended to limit the scope of the invention.
For simplicity and clarity of description, the aspects of the present invention are described below by describing several representative embodiments. Numerous details of the embodiments are set forth to provide an understanding of the principles of the invention. It is clear, however, that the solution according to the invention can be implemented without being limited to these details. Some embodiments are not described in detail, but rather only to give a framework, in order to avoid unnecessarily obscuring aspects of the present invention. Hereinafter, "including" means "including but not limited to", "according to … …" means "at least according to … …, but not limited to … … only". In view of the language convention of chinese, the following description, when it does not specifically state the number of a component, means that the component may be one or more, or may be understood as at least one.
Example one
Referring to fig. 3, the present invention provides a driving circuit of a hold relay, including: the circuit comprises a first triode Q1, a second triode Q2, a first resistor R1, a second resistor R2, a third resistor R3, a capacitor C1 and a first diode D1; one end of the first resistor R1 is connected with a control pin I/O, and the other end of the first resistor R1 is respectively connected with the base of the first triode Q1 and one end of the second resistor R2; the second resistor R2 is set as a pull-up resistor of the first triode Q1, and the other end of the second resistor R2 is connected to a dc power supply VCC; the second triode Q2 is respectively connected with one end of the first triode Q1 and one end of the third resistor R3; a series circuit consisting of a holding relay and the capacitor C1 is arranged between the collector and the emitter of the second triode Q2; the anode of the first diode D1 is connected to the series circuit; the cathode of the first diode D1 and the other end of the third resistor R3 are both grounded.
In this embodiment, the first transistor Q1 is a PNP transistor or an NPN transistor. When the first transistor Q1 is a PNP transistor, the emitter of the first transistor Q1 is connected to the other end of the second resistor R2, and the collector of the first transistor Q1 is connected to the second transistor Q2. Fig. 3 illustrates a PNP transistor as an example. When the first transistor Q1 is an NPN transistor, the collector of the first transistor Q1 is connected to the other end of the second resistor R2, and the emitter of the first transistor Q1 is connected to the second transistor Q2.
In this embodiment, the second transistor Q2 may be a PNP transistor or an NPN transistor, which is not limited in this embodiment.
In this embodiment, the driving circuit of the hold relay further includes: a second diode D2; the anode of the second diode D2 is connected with the first triode Q1; the cathode of the second diode D2 is connected to the second transistor Q2.
The second diode D2 can act as a backflow prevention. That is, if the dc voltage fluctuates during charging, the voltage on the Q2 side of the second transistor is lower than the capacitor C1, and no backflow occurs.
In this embodiment, the anode of the first diode D1 is connected to the series circuit; the cathode of the first diode D1 is grounded. The second transistor Q2 can be turned on instantaneously after power down because the first diode D1 has a voltage drop of 0.7 v.
In this embodiment, electric capacity with hold relay's hookup location can exchange, the embodiment of the utility model provides a do not do specific restriction.
Further, the control pin I/O is connected to an MCU, and the MCU sends a high-low level signal to the control pin I/O.
In this embodiment, when the MCU sets the control pin I/O to low level, the first transistor Q1 is turned on, the second transistor Q2 is turned off, the second diode D2 is turned on, the polar capacitor C1 (or non-polar capacitor C1) is charged, the first terminal JDQ-1(JDQ is an abbreviation of relay and can be understood as a coil of the relay) of the hold-up relay is at high potential instantaneously, the second terminal JDQ-2 of the hold-up relay is connected to ground through the second diode D2 and is at low potential, and at this time, a forward current flows through the hold-up relay, and the hold-up relay becomes in a forward state; when the MCU sets the control pin I/O to be high level or the MCU loses power (the setting of the second resistor R2 makes the MCU lose power, the control pin I/O end is high level), the capacitor C1 discharges, the first triode Q1 is cut off, the first diode D1 and the second diode D2 are cut off in reverse direction, meanwhile, the second triode Q2 is conducted instantly, the second end JDQ-2 of the relay is kept at high potential, the first end JDQ-1 of the relay is kept at low potential instantly, at this time, the reverse current flows through the relay, and the relay is changed into reverse state. Therefore, this embodiment not only can control hold relay two-way work, can also make hold relay can fall the state before the electricity of automatic recovery after MCU falls the power failure, further makes relay link more intelligent and safety.
Example two
The utility model relates to a drive circuit of latching relay, include: the circuit comprises a first triode Q1, a second triode Q2, a first resistor R1, a second resistor R2, a third resistor R3, a capacitor C1 and a first diode D1; one end of the first resistor R1 is connected with a control pin I/O, and the other end of the first resistor R1 is respectively connected with the base of the first triode Q1 and one end of the second resistor R2; the second resistor R2 is set as a pull-up resistor of the first triode Q1, and the other end of the second resistor R2 is connected to a dc power supply VCC; the second triode Q2 is respectively connected with one end of the first triode Q1 and one end of the third resistor R3; a series circuit consisting of a holding relay and the capacitor C1 is arranged between the collector and the emitter of the second triode Q2; the anode of the first diode D1 is connected to the series circuit; the cathode of the first diode D1 and the other end of the third resistor R3 are both grounded.
The difference between this embodiment and the first embodiment is that the driving circuit of the hold relay further includes: a third triode Q3, a fourth resistor R4 and a fifth resistor R5; one end of the first resistor R1 is connected with the control pin I/O through the third triode Q3 and the fourth resistor R4; the fifth resistor R5 is set as a pull-down resistor of the third transistor Q3.
In this embodiment, the first transistor Q1 is a PNP transistor or an NPN transistor. Fig. 4 and 5 illustrate a PNP transistor as an example. When the first transistor Q1 is a PNP transistor, the emitter of the first transistor Q1 is connected to the other end of the second resistor R2, and the collector of the first transistor Q1 is connected to the second transistor Q2. When the first transistor Q1 is an NPN transistor, the collector of the first transistor Q1 is connected to the other end of the second resistor R2, and the emitter of the first transistor Q1 is connected to the second transistor Q2.
In this embodiment, the driving circuit of the hold relay further includes: a second diode D2; the anode of the second diode D2 is connected with the first triode Q1; the cathode of the second diode D2 is connected to the second transistor Q2.
The second diode D2 can act as a backflow prevention. That is, if the dc voltage fluctuates during charging, the voltage on the Q2 side of the second transistor is lower than the capacitor C1, and no backflow occurs.
In this embodiment, the anode of the first diode D1 is connected to the series circuit; the cathode of the first diode D1 is grounded. The second transistor Q2 can be turned on instantaneously after power down because the first diode D1 has a voltage drop of 0.7 v.
In this embodiment, the second transistor Q2 is an NPN transistor.
Referring to fig. 4 and 5, when the second transistor Q2 is an NPN transistor, the cathode of the second diode D2 is connected to the collector of the second transistor Q2, the emitter of the second transistor Q2 is connected to the anode of the first diode D1, and the base of the second transistor Q2 is grounded.
In fig. 4, one end of the capacitor C1 is connected to the first transistor Q1 through the second diode D2, and the other end of the capacitor C1 is connected to one end of the hold relay; the other end of the hold relay is connected to the anode of the first diode D1.
In fig. 5, one end of the hold relay is connected to the first transistor Q1 through the second diode D2, and the other end of the hold relay is connected to one end of the capacitor C1; the other end of the capacitor C1 is connected to the anode of the first diode D1.
In this embodiment, the control pin I/O is connected to an MCU, and the MCU sends high and low level signals to the control pin I/O.
In this embodiment, when the MCU sets the control pin I/O to a high level, the third transistor Q3 and the first transistor Q1 are turned on, the second transistor Q2 is turned off, the first diode D1 is turned on, the polar capacitor C1 (or the non-polar capacitor C1) is charged, the first terminal JDQ-1(JDQ is an abbreviation of the relay and can be understood as a coil of the relay) of the hold relay is instantaneously at a high potential, the second terminal JDQ-2 of the hold relay is connected to ground through the first diode D1 and is at a low potential, and at this time, a forward current flows through the hold relay, so that the hold relay becomes in a forward state; when the MCU sets the control pin I/O to be low level or the MCU loses power (the setting of the fourth resistor R4 makes the MCU lose power, the control pin I/O end is low level), the capacitor C1 discharges, the third triode Q3 and the first triode Q1 are cut off, the second diode D2 and the first diode D1 are cut off in reverse direction, meanwhile, the second triode Q2 is switched on instantly, the second end JDQ-2 of the relay is high potential, the first end JDQ-1 of the relay is low potential instantly, at the moment, reverse current flows through the relay, and the relay is changed into reverse state. Therefore, this embodiment not only can control hold relay two-way work, can also make hold relay can fall the state before the electricity of automatic recovery after MCU falls the power failure, further makes relay link more intelligent and safety.
EXAMPLE III
The utility model relates to a drive circuit of latching relay, include: the circuit comprises a first triode Q1, a second triode Q2, a first resistor R1, a second resistor R2, a third resistor R3, a capacitor C1 and a first diode D1; one end of the first resistor R1 is connected with a control pin I/O, and the other end of the first resistor R1 is respectively connected with the base of the first triode Q1 and one end of the second resistor R2; the second resistor R2 is set as a pull-up resistor of the first triode Q1, and the other end of the second resistor R2 is connected to a dc power supply VCC; the second triode Q2 is respectively connected with one end of the first triode Q1 and one end of the third resistor R3; a series circuit consisting of a holding relay and the capacitor C1 is arranged between the collector and the emitter of the second triode Q2; the anode of the first diode D1 is connected to the series circuit; the cathode of the first diode D1 and the other end of the third resistor R3 are both grounded.
The difference between this embodiment and the first embodiment is that the driving circuit of the hold relay further includes: a third triode Q3, a fourth resistor R4 and a fifth resistor R5; one end of the first resistor R1 is connected with the control pin I/O through the third triode Q3 and the fourth resistor R4; the fifth resistor R5 is set as a pull-down resistor of the third transistor Q3.
In this embodiment, the first transistor Q1 is a PNP transistor or an NPN transistor. Fig. 4 and 5 illustrate a PNP transistor as an example. When the first transistor Q1 is a PNP transistor, the emitter of the first transistor Q1 is connected to the other end of the second resistor R2, and the collector of the first transistor Q1 is connected to the second transistor Q2. When the first transistor Q1 is an NPN transistor, the collector of the first transistor Q1 is connected to the other end of the second resistor R2, and the emitter of the first transistor Q1 is connected to the second transistor Q2.
In this embodiment, the driving circuit of the hold relay further includes: a second diode D2; the anode of the second diode D2 is connected with the first triode Q1; the cathode of the second diode D2 is connected to the second transistor Q2.
The second diode D2 can act as a backflow prevention. That is, if the dc voltage fluctuates during charging, the voltage on the Q2 side of the second transistor is lower than the capacitor C1, and no backflow occurs.
In this embodiment, the anode of the first diode D1 is connected to the series circuit; the cathode of the first diode D1 is grounded. The second transistor Q2 can be turned on instantaneously after power down because the first diode D1 has a voltage drop of 0.7 v.
The difference between this embodiment and the second embodiment is that the second transistor Q2 is a PNP transistor.
Referring to fig. 6 and 7, when the second transistor Q2 is a PNP transistor, the cathode of the second diode D2 is connected to the emitter of the second transistor Q2, the collector of the second transistor Q2 is connected to the anode of the first diode D1, and the base of the second transistor Q2 is connected to the collector of the second transistor Q2.
In fig. 6, one end of the capacitor C1 is connected to the first transistor Q1 through the second diode D2, and the other end of the capacitor C1 is connected to one end of the hold relay; the other end of the hold relay is connected to the anode of the first diode D1.
In fig. 7, one end of the hold relay is connected to the first transistor Q1 through the second diode D2, and the other end of the hold relay is connected to one end of the capacitor C1; the other end of the capacitor C1 is connected to the anode of the first diode D1.
In this embodiment, the control pin I/O is connected to an MCU, and the MCU sends high and low level signals to the control pin I/O.
In this embodiment, when the MCU sets the control pin I/O to a high level, the third transistor Q3 and the first transistor Q1 are turned on, the second transistor Q2 is turned off, the first diode D1 is turned on, the polar capacitor C1 (or the non-polar capacitor C1) is charged, the first terminal JDQ-1(JDQ is an abbreviation of the relay and can be understood as a coil of the relay) of the hold relay is instantaneously at a high potential, the second terminal JDQ-2 of the hold relay is connected to ground through the first diode D1 and is at a low potential, and at this time, a forward current flows through the hold relay, so that the hold relay becomes in a forward state; when the MCU sets the control pin I/O to be low level or the MCU loses power (the setting of the fourth resistor R4 makes the MCU lose power, the control pin I/O end is low level), the capacitor C1 discharges, the third triode Q3 and the first triode Q1 are cut off, the second diode D2 and the first diode D1 are cut off in reverse direction, meanwhile, the second triode Q2 is switched on instantly, the second end JDQ-2 of the relay is high potential, the first end JDQ-1 of the relay is low potential instantly, at the moment, reverse current flows through the relay, and the relay is changed into reverse state. Therefore, this embodiment not only can control hold relay two-way work, can also make hold relay can fall the state before the electricity of automatic recovery after MCU falls the power failure, further makes relay link more intelligent and safety.
The above-mentioned be the utility model discloses a concrete implementation way, nevertheless the utility model discloses a design concept is not limited to this, and the ordinary use of this design is right the utility model discloses carry out immaterial change, all should belong to the act of infringement the protection scope of the utility model.
Claims (10)
1. A drive circuit for a hold-down relay, comprising: the circuit comprises a first triode, a second triode, a first resistor, a second resistor, a third resistor, a capacitor and a first diode; one end of the first resistor is connected with the control pin, and the other end of the first resistor is respectively connected with the base electrode of the first triode and one end of the second resistor; the second resistor is set as a pull-up resistor of the first triode, and the other end of the second resistor is connected with a direct-current power supply; the second triode is connected with one end of the first triode and one end of the third resistor respectively; a series circuit formed by the holding relay and the capacitor is arranged between the collector and the emitter of the second triode; the anode of the first diode is connected with the series circuit; and the cathode of the first diode and the other end of the third resistor are both grounded.
2. The drive circuit for a retention relay according to claim 1, further comprising: the third triode, the fourth resistor and the fifth resistor; one end of the first resistor is connected with the control pin through the third triode and the fourth resistor; the fifth resistor is set as a pull-down resistor of the third triode.
3. The drive circuit for a retention relay according to claim 1, further comprising: a second diode; the anode of the second diode is connected with the first triode; and the cathode of the second triode is connected with the second triode.
4. The drive circuit of a retention relay according to claim 1, wherein the first transistor is an NPN transistor or a PNP transistor.
5. The drive circuit of a hold relay according to claim 1, wherein the second transistor is an NPN transistor; the collector of the second triode is connected with the first triode; the emitter of the second triode is connected with the anode of the first diode; and the base electrode of the second triode is grounded.
6. The drive circuit of a hold relay according to claim 1, wherein the second transistor is a PNP transistor; the emitting electrode of the second triode is connected with the first triode; and the collector and the base of the second triode are both connected with the anode of the first diode.
7. The drive circuit of a retention relay according to claim 2, wherein the third transistor is an NPN transistor or a PNP transistor.
8. The drive circuit of a hold relay according to claim 1, wherein one end of the capacitor is connected to the first transistor, and the other end of the capacitor is connected to one end of the hold relay; the other end of the hold relay is connected to the anode of the first diode.
9. The drive circuit of the hold relay according to claim 1, wherein one end of the hold relay is connected to the first transistor, and the other end of the hold relay is connected to one end of the capacitor; the other end of the capacitor is connected with the anode of the first diode.
10. The drive circuit of a hold relay according to claim 1, wherein the control pin is connected to an MCU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022758391.7U CN213752539U (en) | 2020-11-25 | 2020-11-25 | Drive circuit of holding relay |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022758391.7U CN213752539U (en) | 2020-11-25 | 2020-11-25 | Drive circuit of holding relay |
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| Publication Number | Publication Date |
|---|---|
| CN213752539U true CN213752539U (en) | 2021-07-20 |
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| CN202022758391.7U Active CN213752539U (en) | 2020-11-25 | 2020-11-25 | Drive circuit of holding relay |
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| CN (1) | CN213752539U (en) |
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- 2020-11-25 CN CN202022758391.7U patent/CN213752539U/en active Active
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